MUNCHEN TECHNISCHE UNIVERSITAT Lehrstuhl f ur Integrierte Systeme

Chip Multicore Processors Tutorial 10

July 3, 2013

Task 10.1: Why On-Chip Coherence is Here to Stay

Read the article Why On-Chip Cache Coherence is Here to Stay, Martin et al. Summarize the central statements and proposed ideas to cope with the scalability challenges.

Task 10.2: Scalability of Interconnects

Given is a simple embedded system with P processor cores and an embedded SRAM 32-bit wide memory. The memory has one cycle latency for accesses. a) A simple data bus (no pipelining) is used to connect the processor cores and the memory. What is the average bandwidth for each processor core assuming all cores generate consecutive memory accesses? b) The bus and memory allow for 4-beat bursts. How does the achievable bandwidth change? c) Develop a simple schematic sketch that shows the dierences between a simple bus and a simple crossbar for the given scenario. d) How does the bandwidth change for a crossbar? What is the limiting factor? In what dierent scenario can the performance be improved? e) How can a bi-drectional ring improve the setup with respect to bandwidth and latency? Elaborate scenarios where a ring is advantegeous and where it is disadvantageous.

Task 10.3: Turn Model

a) What is the dierence between XY-routing and west-rst-routing? b) Change the Channel-Dependency diagram of XY-routing so that it reects west-rst routing. Mark all forbidden turns and potentially add new routes.
0E 0L 0S 2N 1L

1W 1S 2E 3N 3L 2L 3W

y x

c) Check whether the depicted routing function is a valid turn model. If not, show the potential cycle.