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  • 2012EEE2188 DSP Experiment 4

    Загружено:

    Abhiroop Verma
    15 просмотров3 страницы
    This document describes two implementations of a finite impulse response (FIR) filter on a C54x digital signal processor: 1. An asymmetric 4-tap FIR filter that loads coefficients from a circular buffer and multiplies and accumulates input samples from a linear buffer to calculate the output. 2. A symmetric 4-tap FIR filter that uses the FIRSADD instruction to simultaneously add and multiply two input samples with coefficients from a circular buffer to calculate the output.

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    lab file

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    This document describes two implementations of a finite impulse response (FIR) filter on a C54x digital signal processor: 1. An asymmetric 4-tap FIR filter that loads coefficients from a circular buffer and multiplies and accumulates input samples from a linear buffer to calculate the output. 2. A symmetric 4-tap FIR filter that uses the FIRSADD instruction to simultaneously add and multiply two input samples with coefficients from a circular buffer to calculate the output.

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    Attribution Non-Commercial (BY-NC)
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    15 просмотров3 страницы

    2012EEE2188 DSP Experiment 4

    Загружено:

    Abhiroop Verma
    This document describes two implementations of a finite impulse response (FIR) filter on a C54x digital signal processor: 1. An asymmetric 4-tap FIR filter that loads coefficients from a circular buffer and multiplies and accumulates input samples from a linear buffer to calculate the output. 2. A symmetric 4-tap FIR filter that uses the FIRSADD instruction to simultaneously add and multiply two input samples with coefficients from a circular buffer to calculate the output.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 3

    FIR Filter Implementation

    A. Asymmetric FIR Filter (4-tap Filter)


    N M .set 4 .set 4 .mmregs .def start

    start BCLR C54CM BCLR AR0LC ;Linear Mode AMOV #010000h,XAR0 ;Starting Address for Input BCLR AR1LC ;Linear Mode AMOV #010020h,XAR1 ;Starting Address for Output BSET CDPLC ;Circular Addressing BSET SATD ;To Saturate Accumulator BSET FRCT ;To shift Accumulator left by one bit AMOV #000100h,XCDP ;Starting Address for coefficient MOV #0h,BSAC ;Offset for circular Addressing of CDP MOV #N,BKC ;Size of Block for Circular Addressing MOV #0,AC0 MOV #(M+N-2),BRC0 ;Initializing for local block repeat MOV #N,T0 ;Offset to move pointer of AR0 back. RPTBLOCAL LOOP MPYM *AR0-,*CDP+,AC0 RPT #N-3 MACM *AR0-,*CDP+,AC0 MACM *(AR0+T0),*CDP+,AC0 LOOP MOV HI(AC0),*AR1+ ;Storing Output IDLE

    B. FIR Filter (Using FIRSADD)


    N M .set 4;h .set 4;x .mmregs .def start

    start BCLR C54CM BCLR AR0LC ;Linear Mode AMOV #01000h,XAR0 ;Starting Address for Input X AMOV #01000h-N+1,XAR2 ;Second Pointer for X BCLR AR1LC ;Linear Mode AMOV #010020h,XAR1 ;Starting Address for Output BSET CDPLC ;Circular Addressing BSET SATD ;To Saturate Accumulator BSET FRCT ;To shift Accumulator left by one bit AMOV #000100h,XCDP ;Starting Address for coefficient H MOV #0h,BSAC ;Offset for circular Addressing of CDP MOV #N/2,BKC ;Size of Block for Circular Addressing MOV #0,AC0 MOV #0,AC1 MOV #(M+N-2),BRC0 ;Initializing for local block repeat BR0+1 times MOV #N/2,T0 ;Offset to move pointer of AR0 back. RPTBLOCAL LOOP

    MOV #0,AC0 MOV #0,AC1 ADD *AR2+,*AR0-,AC0 FIRSADD *AR2,*AR0,*CDP+,AC0,AC1 MACM *CDP+,AC0,AC1 MOV *(AR0+T0),*AR0 LOOP MOV HI(AC1),*AR1+ ;Storing Output IDLE

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