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D FLIP FLOP VHDL CODE USING BEHAVIOURAL MODELING

Library ieee declaration.

library IEEE; In ieee library std_logic_1164 package is declared for std_logic data types (predefined data types). use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------------------entity dff is Port ( D,clk,reset : in STD_LOGIC; Q,Qbar : out STD_LOGIC); end dff;
Entity describes circuit external ports. D , clk, rst: - input port to D flip flop. Q, Qbar: - output port to D flip flop. Q:- present state, Qbar: - next state.

-------------------------------------------------------------architecture Behavioral_dff of dff is begin Architecture begins. -------------------------------------------------------------process (D,clock,reset) begin if (reset='1' )then Q<='0'; Qbar<='1'; elsif (clock'event and clock='1') then Q <= D; Qbar <= not D; end if; end process;

In a process all the statements will be executed sequentially. Reset is having highest priority. If clock rising edge is +ve and reset is 0 then flip flop will work otherwise its output will be previous state. Truth table of D flip flops. clock 0 1 1 D x 0 1 Q Previous state 0 1 QBAR Previous sate 1 0

------------------------------------------------------------end Behavioral_dff; End of architecture.

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