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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

J-K_TO_D FLIP FLOP CONVERSION VHDL CODE

AND RESEARCH (OP2R) J-K_TO_D FLIP FLOP CONVERSION VHDL CODE  Library ieee declaration.  In “ieee”

Library ieee declaration.

In “ieee” library std_logic_1164 package is declared for std_logic data types (predefined data

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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 Entity describes circuit external ports.  D, clock, reset: - input port to D
 Entity describes circuit external ports.
 D, clock, reset: - input port to D flip flop.
 Q, Q1: - output port to D flips flop.
 Component (jk_ff) declaration.
 Declarative part of D flip-flop’s architecture.
 Components represent the structure of
converted flip-flop.
Architecture begins.
 Statements part of the architecture.
 Components are port mapped to
perform D flip flop operation.
are port mapped to perform D flip flop operation. entity JK_to_D is Port ( D,clock,reset :

entity JK_to_D is Port ( D,clock,reset : in STD_LOGIC; Q,Q1 : inout STD_LOGIC); end JK_to_D;

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architecture structural_con of JK_to_D is

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component jk_ff port (j,k,clk,rst:in std_logic; x,y:inout std_logic); end component;

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begin

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ff: jk_ff port map (D,not D,clock,reset,Q,Q1);

--------------------------------------------------------------------------

end structural_con;

RTL VIEW:-

end structural_con; RTL VIEW:- INFOOP2R.WIX.COM/OP2R
end structural_con; RTL VIEW:- INFOOP2R.WIX.COM/OP2R

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

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