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S-R_TO_T FLIP FLOP CONVERSION VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity SR_to_T is
Port ( T,clock,reset : in STD_LOGIC;
Q,Q1 : inout STD_LOGIC);
end SR_to_T;

Library ieee declaration.

In ieee library std_logic_1164 package is
declared for std_logic data types (predefined data
types).

Entity describes circuit external ports.

T, clock, reset: - input port to T flip-flop.
Q, Q1: - output port to T flip-flop.

--------------------------------------------------------architecture structural_con of SR_to_T is

--------------------------------------------------------signal s1,s2:std_logic;
----------------------------------- Signal s1, s2 are declared to hold a
component s_rff
particular value. These are acting as inout
port (s,r,clk,rst:in std_logic;
ports.
x,y:inout std_logic);
Components (s_rff and and1) declaration.
Declarative part of T flip-flops
end component;
architecture.
----------------------------------- Components represent the structure of
component and1 is
converted flip-flop circuit.
port (a,b:in std_logic;
And1 component represents AND
c:out std_logic);
operation in digital circuit.
end component;
-----------------------------------begin
------------------------------------------------------------------------ Statements part of the
a1:and1 port map (T, Q1, s1);
architecture.
a2:and1 port map (T, Q, s2);
Components are port mapped to
ff: s_rff port map (s1,s2,clock,reset,Q,Q1);
perform T flip flop operation.
-------------------------------------------------------------------------end structural_con;

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