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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

TWOS COMPLEMENT VHDL CODE USING DATA FLOW MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.all;

Std_logic_1164. Package for std_logic (predefined data types). Std_logic_unsigned package: - for unsigned arithmetic operation of predefined data types.

-----------------------------------------------------------------entity twos_comp is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); z : out STD_LOGIC_VECTOR (3 downto 0)); end twos_comp; -----------------------------------------------------------------architecture Behavioral_2scomp of twos_comp is signal s: std_logic_vector(3 downto 0); --------------------------------------------begin s<= not i; z<= s+ 1; ---------------------------------------------end Behavioral_2scomp;

Entity declaration. i: - input port bits. z: - output port bits.(2s complement of input).

Concurrent statements. Expression for 2s complement circuit that are calculated using k-map and Boolean function.

RTL VIEW:-

OUT PUT WAVEFORMS:-

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