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INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING DATA FLOW MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic (predefined data types).

entity half_subtractor is Port ( a, b: in STD_LOGIC; diff ,borrow: out STD_LOGIC); end half_subtractor; --------------------------------------------architecture Behavioral of half_subtractor is begin ---------------------------------------------sum<= a xor b; carry<= ((not a) and b); ---------------------------------------------and Behavioral;

Entity declaration. a, b: - input port bits (bits to be added) Sum, carry: - output port bits

Concurrent statement of half adder circuit. These are the circuit expressions which are formed by k-map or Boolean function.

RTL VIEW:-

OUT PUT WAVEFORMS:-

INFOOP2R.WIX.COM/OP2R