DATE: 13-03-2014

13MV0036

4. LOW POWER ANALYSIS FOR VARIOUS MODULES

Objective:

To apply the low power constraints to 4-bit array multiplier, finite state machine, MAC
unit

ARRAY MULTIPLIER:
Before applying low power constraints:
Setup.g file:
########################################################################
############
#
MAIN SETUP (root attributes & setup variables)
#
########################################################################
############
#### Setup
set LOCAL_DIR "."
set SYNTH_DIR $LOCAL_DIR/work
set hdl_path $LOCAL_DIR/
set library_path /root/Cadence_tools/rclabs/90nm
#set TCL_PATH $LOCAL_DIR/
set
set
set
set

library {slow.lib}
LEF_LIBRARY gsclib045_tech.lef
CAP_TABLE gpdk045.extended.capTbl
file_list {project.v}

set WL_MODEL_LIB $library

set WL_MODEL
"tsmc18_wl10"
set WL_MODE
enclosed
set
set
set
set
set

DESIGN main
SYN_EFF high
MAP_EFF high
DATE [exec date +%m%d.%H%M]
SYN_PATH "."

set_attr lib_search_path $library_path

set_attr hdl_search_path $hdl_path
#set_attr script_search_path $TCL_PATH
set_attr library ${library}
read_hdl ${file_list}
elaborate main
#set the constraints for the design
#include constraints.g

Constraints.g file:

#Apply clocks

DATE: 13-03-2014

13MV0036

set clk [define_clock -p 4200 -name clk [find /des* -port \ports_in/clk]]
#define_clock -p 6000 -name clk [find /des* -port clk]
set_attr clock_source_late_latency 200 [find / -clock clk]
set_attr clock_network_late_latency 200 [find / -clock clk]
set_attr clock_setup_uncertainty 100 [find / -clock *]
set_attr slew_fall 20 [find / -clock clk]
set_attr slew_rise 20 [find / -clock clk]
# Apply external delays
external_delay -input 500 -clock clk [all_inputs]
external_delay -output 500 -clock clk [all_outputs]

Area report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 01:03:46 pm
Module:
arraymul4bit
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
------------------------------------------------------------------arraymul4bit
89
582
0
582
<none> (D)
FA1
14
70
0
70
<none> (D)
FA8
11
58
0
58
<none> (D)
FA4
5
40
0
40
<none> (D)
FA5
4
34
0
34
<none> (D)
FA3
6
34
0
34
<none> (D)
FA2
8
33
0
33
<none> (D)
HA3
4
33
0
33
<none> (D)
FA6
7
30
0
30
<none> (D)
HA1
2
23
0
23
<none> (D)
FA7
1
21
0
21
<none> (D)
HA2
4
20
0
20
<none> (D)
HA4
1
12
0
12
<none> (D)
(D) = wireload is default in technology library

Power report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 01:03:28 pm
Module:
arraymul4bit
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library

DATE: 13-03-2014

13MV0036

============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------arraymul4bit
89 3945.643 259581.172 263526.814
FA8
11
381.731 21932.401 22314.132
FA1
14
363.605 30000.558 30364.163
FA4
5
264.446 13659.693 13924.139
FA5
4
234.293
8070.332
8304.625
HA1
2
229.656
5373.844
5603.500
HA3
4
198.254
9628.061
9826.314
FA3
6
181.603 12935.203 13116.806
FA2
8
159.867 13210.174 13370.041
FA6
7
158.585
6143.340
6301.925
HA2
4
118.949
5386.248
5505.197
HA4
1
95.531
4625.756
4721.288
FA7
1
93.146
5238.207
5331.353

Timing report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 01:13:02 pm
Module:
arraymul4bit
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-----------------------------------------------------------(clock clk)
launch
0 R
latency
+400
400 R
(in_del_1)
ext delay
+500
900 F
i1[1]
in port
2 12.2
0
+0
900 F
g131/A
+0
900
g131/Y
CLKINVX4
3 13.6
35
+30
930 R
g117/B
+0
930
g117/Y
NOR2X2
2 6.0
37
+36
967 F
HA1/a
g18/A
+0
967
g18/Y
CLKAND2X2
2 4.6
48 +131
1098 F
HA1/cout
FA1/cin
g60/B
+0
1098
g60/Y
NAND2X1
1 2.8
45
+47
1145 R
g58/B
+0
1145
g58/Y
NAND2X1
3 8.3 131 +110
1254 F
FA1/cout
FA2/cin

DATE: 13-03-2014

13MV0036

g57/B
+0
1254
g57/Y
NAND2X1
1 2.8
60
+66
1321 R
g56/B0
+0
1321
g56/Y
OAI21X1
4 9.8 167 +137
1458 F
FA2/sout
FA5/a
g60/A
+0
1458
g60/Y
CLKINVX1
1 2.6
65
+67
1524 R
g59/A
+0
1524
g59/Y
MXI2X1
2 5.4 129 +106
1631 F
g58/A
+0
1631
g58/Y
CLKINVX1
1 2.6
56
+60
1691 R
g56/A
+0
1691
g56/Y
MXI2X1
1 3.8 100
+90
1781 F
FA5/sout
HA4/a
g17/A
+0
1781
g17/CO
ADDHX1
1 8.6
78 +152
1933 F
HA4/cout
FA8/cin
g55/A
+0
1933
g55/CO
ADDFHX2
1 6.3
81 +239
2172 F
FA8/cout
FA7/cin
g55/CI
+0
2172
g55/CO
ADDFHX1
3 4.8
86 +215
2387 F
FA7/cout
FA6/cin
g59/A
+0
2387
g59/Y
INVXL
1 1.7
48
+57
2444 R
g56/A
+0
2444
g56/Y
MXI2XL
1 0.0
51
+54
2499 F
FA6/sout
pro[6]
out port
+0
2499 F
(ou_del_1)
ext delay
+500
2999 F
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
2700 R
latency
+400
3100 R
uncertainty
-100
3000 R
-----------------------------------------------------------Timing slack :
1ps
Start-point : i1[1]
End-point
: pro[6]

After applying low power constraints

Power report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:24:39 pm
Module:
arraymul4bit
Technology library:
slow

DATE: 13-03-2014

13MV0036

Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------arraymul4bit
65 2234.777 135022.539 137257.316
FA4
3
225.925
7626.283
7852.207
FA5
3
223.895
7567.944
7791.839
FA1
11
182.016 10626.587 10808.603
HA1
2
149.044
3650.342
3799.386
FA2
8
147.329 15242.088 15389.417
FA6
7
138.362
8364.952
8503.314
FA3
5
136.269
9657.231
9793.501
HA2
1
95.531
5122.226
5217.757
HA3
1
95.531
4761.745
4857.276
HA4
1
95.531
6453.875
6549.406
FA7
1
93.146
6544.530
6637.676
FA8
1
93.146
6451.672
6544.818
============================================================

Area report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:24:39 pm
Module:
arraymul4bit
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
------------------------------------------------------------------arraymul4bit
65
391
0
391
<none> (D)
FA1
11
42
0
42
<none> (D)
FA2
8
35
0
35
<none> (D)
FA5
3
33
0
33
<none> (D)
FA4
3
33
0
33
<none> (D)
FA6
7
30
0
30
<none> (D)
FA3
5
26
0
26
<none> (D)
FA8
1
21
0
21
<none> (D)
FA7
1
21
0
21
<none> (D)
HA1
2
17
0
17
<none> (D)
HA4
1
12
0
12
<none> (D)
HA3
1
12
0
12
<none> (D)
HA2
1
12
0
12
<none> (D)
(D) = wireload is default in technology library

DATE: 13-03-2014

13MV0036

FINITE STATE MACHINE:

Before applying low power constraints:
Area report:
============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 10:43:26 am
Module:
fsm1
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
-------------------------------------------------------------------fsm1
14
282
0
282
<none> (D)
mux_ns_18_6
2
61
0
61
<none> (D)
mux_z_18_6
1
31
0
31
<none> (D)
mux_ps_8_5
2
31
0
31
<none> (D)
mux_29_6
2
31
0
31
<none> (D)
mux_25_6
2
31
0
31
<none> (D)
mux_34_5
1
15
0
15
<none> (D)
mux_33_6
1
15
0
15
<none> (D)
mux_21_6
1
15
0
15
<none> (D)
(D) = wireload is default in technology library

Power report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 10:45:19 am
Module:
fsm1
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------fsm1
10
668.801 33816.934 34485.735
mux_25_6
2
108.365 3228.238 3336.603
mux_29_6
2
108.365 3228.238 3336.603
mux_ns_18_6
2
102.375 5583.472 5685.847
mux_21_6
1
54.182 2367.166 2421.348
mux_z_18_6
1
51.187 1157.100 1208.287

DATE: 13-03-2014

13MV0036

Timing report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 10:42:40 am
Module:
fsm1
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-----------------------------------------------------------------(clock clk)
launch
0 R
latency
+400
400 R
(in_del_1)
ext delay
+500
900 R
x
(u) in port
7 49.0
0
+0
900 R
mux_34_5/ctl
g1/sel0
+0
900
g1/z
(u) unmapped_bmux3
1 7.0
0 +126
1026 R
mux_34_5/z
mux_z_18_6/in_3
g1/data3
+0
1026
g1/z
unmapped_bmux6
1 0.0
0 +212
1238 R
mux_z_18_6/z
z
out port
+0
1238 R
(ou_del_1)
ext delay
+500
1738 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
1500 R
latency
+400
1900 R
uncertainty
-100
1800 R
-----------------------------------------------------------------Timing slack :
62ps
Start-point : x
End-point
: z
(u) : Net has unmapped pin(s).

After applying low power constraints

Power report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 10:46:02 am
Module:
fsm1
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed

DATE: 13-03-2014

13MV0036

Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------fsm1
8
271.085 24988.996 25260.081
mux_ns_18_6
3
28.212
594.247
622.459
mux_z_18_6
1
25.332
0.000
25.332

Area report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 10:46:02 am
Module:
fsm1
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
-------------------------------------------------------------------fsm1
8
60
0
60
<none> (D)
mux_ns_18_6
3
13
0
13
<none> (D)
mux_z_18_6
1
6
0
6
<none> (D)
(D) = wireload is default in technology library

MAC UNIT:
Before applying low power constraints:
Area report:
============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:40:08 pm
Module:
mac_array
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
--------------------------------------------------------------------mac_array
181
1575
0
1575
<none> (D)
m1
80
610
0
610
<none> (D)
FA6
7
53
0
53
<none> (D)
FA7
7
53
0
53
<none> (D)
FA8
7
53
0
53
<none> (D)
FA3
7
53
0
53
<none> (D)

DATE: 13-03-2014
FA4
FA5
FA2
FA1
HA4
HA3
HA2
HA1
add_50_14
mux_mac_44_6

13MV0036
7
7
7
7
2
2
2
2
81
10

53
53
53
53
15
15
15
15
545
153

0
0
0
0
0
0
0
0
0
0

53
53
53
53
15
15
15
15
545
153

<none>
<none>
<none>
<none>
<none>
<none>
<none>
<none>
<none>
<none>

(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)
(D)

(D) = wireload is default in technology library

Power report:

For more accurate power reporting use build_rtl_power_models after generic

synthesis.
============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:39:51 pm
Module:
mac_array
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
----------------------------------------------------mac_array
181 5085.776 289960.906 295046.682
m1
80 2413.561 73939.801 76353.362
FA1
7
222.139
5523.202
5745.341
FA2
7
222.139
5594.161
5816.300
FA5
7
222.139
6529.712
6751.851
FA4
7
222.139
6673.267
6895.407
FA3
7
222.139
5400.714
5622.853
FA8
7
222.139
6891.923
7114.062
FA7
7
222.139
7783.816
8005.955
FA6
7
222.139
4936.963
5159.103
HA1
2
60.458
2497.197
2557.656
HA2
2
60.458
2253.724
2314.183
HA3
2
60.458
3269.218
3329.677
HA4
2
60.458
3706.290
3766.749
add_50_14
81
908.760 123753.282 124662.042
mux_mac_44_6
10
541.825 19461.794 20003.619

Timing report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1

DATE: 13-03-2014

13MV0036

Generated on:
Mar 13 2014 03:41:24 pm
Module:
mac_array
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-------------------------------------------------------------(clock clk)
launch
0 R
latency
+400
400 R
(in_del_1)
ext delay
+500
900 R
i2[1]
in port
4 36.2
0
+0
900 R
m1/i2[1]
g122/A
+0
900
g122/Y
NAND2X8
1 10.5
40
+41
941 F
fopt/A
+0
941
fopt/Y
CLKINVX4
3 10.9
33
+39
980 R
FA1/a
g71/A
+0
980
g71/Y
XOR3X1
2 3.5
94 +350
1330 F
FA1/sout
HA3/a
g18/B
+0
1330
g18/Y
AND2X1
2 7.5
70 +136
1467 F
HA3/cout
FA5/cin
g75/B0
+0
1467
g75/Y
OAI21X1
1 2.7
96
+55
1522 R
g74/A
+0
1522
g74/Y
NAND2X1
2 6.4 109 +105
1627 F
FA5/cout
FA4/cin
g73/C
+0
1627
g73/Y
XOR3X1
1 6.3 115 +212
1840 R
FA4/sout
FA8/a
g55/CI
+0
1840
g55/S
ADDFHXL
1 6.3 104 +328
2168 F
FA8/sout
m1/pro[4]
g701/CI
+0
2168
g701/CO
ADDFHX2
1 6.3
81 +235
2402 F
g698/CI
+0
2402
g698/CO
ADDFHX2
1 6.3
81 +228
2630 F
g695/CI
+0
2630
g695/CO
ADDFHX2
1 6.3
81 +228
2858 F
g692/CI
+0
2858
g692/CO
ADDFHX1
2 6.3
97 +225
3083 F
g690/A
+0
3083
g690/Y
NAND2X1
2 3.3
58
+68
3152 R
g687/B
+0
3152

DATE: 13-03-2014

13MV0036

g687/Y
NAND2XL
1 1.7
77
+67
3218 F
g685/B0
+0
3218
g685/Y
OAI21XL
1 1.5
96
+59
3278 R
mac_reg[9]/RN
DFFTRX4
+0
3278
mac_reg[9]/CK
setup
10 +234
3511 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
3200 R
latency
+400
3600 R
uncertainty
-100
3500 R
-------------------------------------------------------------Timing slack :
11ps
Start-point : i2[1]
End-point
: mac_reg[9]/RN

After applying low power constraints:

Power report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:41:24 pm
Module:
mac_array
Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------------mac_array
124 5727.517 193154.058 198881.575
m1
72 3272.283 33275.072 36547.355
FA1
6
386.086
3238.561
3624.647
HA1
3
270.947
2646.169
2917.115
FA5
4
234.293
2456.973
2691.267
FA4
4
225.300
899.421
1124.721
FA7
3
221.832
1903.858
2125.690
FA2
11
161.351
2570.844
2732.195
FA3
5
136.269
1820.531
1956.801
FA6
5
131.991
1478.730
1610.720
HA2
4
116.441
585.528
701.969
HA4
1
95.531
2503.762
2599.294
HA3
2
95.435
561.849
657.284
FA8
1
85.832
2288.909
2374.741
RC_OI_HIER_INST3
10
166.245 10306.627 10472.872

Area report:

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Mar 13 2014 03:41:24 pm
Module:
mac_array

DATE: 13-03-2014

13MV0036

Technology library:
slow
Operating conditions:
slow (balanced_tree)
Wireload mode:
enclosed
Area mode:
timing library
============================================================
Instance
Cells Cell Area Net Area Total Area Wireload
------------------------------------------------------------------------mac_array
124
945
0
945
<none> (D)
m1
72
496
0
496
<none> (D)
FA1
6
56
0
56
<none> (D)
FA2
11
41
0
41
<none> (D)
FA5
4
34
0
34
<none> (D)
FA4
4
33
0
33
<none> (D)
FA7
3
33
0
33
<none> (D)
HA1
3
28
0
28
<none> (D)
FA6
5
26
0
26
<none> (D)
FA3
5
26
0
26
<none> (D)
FA8
1
21
0
21
<none> (D)
HA2
4
20
0
20
<none> (D)
HA3
2
13
0
13
<none> (D)
HA4
1
12
0
12
<none> (D)
RC_OI_HIER_INST3
10
45
0
45
<none> (D)
(D) = wireload is default in technology library

Result:
Low power constraints has been applied to 4-bit array multiplier, finite state machine,
MAC unit and observed that the power, area has been reduced when constraints, clock gating
and vcd file is added .