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SecondYear
Lab1
Itisrequiredtodesignandimplementthe16bitALUshowninthefigurebelowthat supportsthefollowingoperations
OperationCode 0000 0001 0010 0011 0100 0101 0110 0111 1000
Description O=A O=A+B O=A+B+Cin O=AB O=ABCin O=A+1 O=A1 O=A&&B O=A||B
Themoduleshouldhavetwo16bitinputports,oneforeachoperand.Another4bit inputporttospecifytheALUoperationand1bitinputascarryorborrowinput.The outputoftheALUisa16bitoutputporttoholdtheresult,1bitforcarryorborrowout threebitsforoverflowflag,Negativeflag,andzeroflag.Youshouldtestthemodule usingtheTestbenchwaveform.Specifyingmeaningfultestcasesisamust. Requirements: Youarerequiredtodeliverareportcontainingthefollowing: 1. ProblemStatement. 2. VHDLsourcecodesnippetsfordifferentoperations 3. Testbenchforeachoperation. Policies: DuedateisTuesday,Apr.9th,2014. Youshouldbringyourvhdlcode(*.vhdl),testbenchwaveforms(*.tbw), packagepinsassignment(*.ucf),andprogrammingfiles(*.bit). Nolatesubmissionwillbeaccepted.