`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date:
17:39:54 01/30/2014
// Design Name:
// Module Name:
rf
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module rf (
// Outputs
read1data, read2data, err,
// Inputs
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
);
input
input
input
input
input
input

clk, rst;
[2:0] read1regsel;
[2:0] read2regsel;
[2:0] writeregsel;
[15:0] writedata;
write;

output [15:0] read1data;

output [15:0] read2data;
output
err;
wire [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
wire [15:0] out0, out1, out2, out3, out4, out5, out6, out7;
wire [7:0] en, tmp_en;
// 8 16-bit registers
register_16bit r0(.In(in0), .Out(out0), .Enable(en[0]), .clk(clk), .rst(
rst));
register_16bit r1(.In(in1), .Out(out1), .Enable(en[1]), .clk(clk), .rst(
rst));
register_16bit r2(.In(in2), .Out(out2), .Enable(en[2]), .clk(clk), .rst(
rst));
register_16bit r3(.In(in3), .Out(out3), .Enable(en[3]), .clk(clk), .rst(
rst));
register_16bit r4(.In(in4), .Out(out4), .Enable(en[4]), .clk(clk), .rst(
rst));
register_16bit r5(.In(in5), .Out(out5), .Enable(en[5]), .clk(clk), .rst(
rst));
register_16bit r6(.In(in6), .Out(out6), .Enable(en[6]), .clk(clk), .rst(
rst));
register_16bit r7(.In(in7), .Out(out7), .Enable(en[7]), .clk(clk), .rst(

rst));
// send writedata to every In port of registers
assign in0 = writedata;
assign in1 = writedata;
assign in2 = writedata;
assign in3 = writedata;
assign in4 = writedata;
assign in5 = writedata;
assign in6 = writedata;
assign in7 = writedata;
// 3-8 decoder to generate temp_en
decoder_3to8 decoder_in(.A(writeregsel), .Y(tmp_en));
assign en = tmp_en & {8{write}};
// 16-bit 8-to-1 mux to generate read1data and read2data
mux_8to1_16bit mux_read1(.In0(out0), .In1(out1), .In2(out2), .In3(out3),
.In4(out4), .In5(out5), .In6(out6), .In7(out7),
.Sel(read1regsel), .Out(read1data));
mux_8to1_16bit mux_read2(.In0(out0), .In1(out1), .In2(out2), .In3(out3),
.In4(out4), .In5(out5), .In6(out6), .In7(out7),
.Sel(read2regsel), .Out(read2data));
// error signal
assign err = ~ (^tmp_en);
endmodule

module register_16bit(In, Out, Enable, clk, rst);

parameter BITWIDTH = 16;
input [BITWIDTH-1 : 0] In;
input Enable;
input clk, rst;
output [BITWIDTH-1 : 0] Out;
dff_en dff_en_16_register[BITWIDTH-1 : 0] (.q(Out), .d(In), .clk(clk), .
rst(rst), .en(Enable));
endmodule

// DFF with enable port

module dff_en(q, d, clk, rst, en);
input d, en;
input clk, rst;
output q;
wire inner_d;

assign inner_d = en ? d : q;
// instantiate DFF with inner_d being sent to d
dff dff_with_en(.q(q), .d(inner_d), .clk(clk), .rst(rst));
endmodule
// D-flipflop
module dff (q, d, clk, rst);
output
input
input
input

q;
d;
clk;
rst;

reg

state;

assign #(1) q = state;

always @(posedge clk) begin
state = rst? 0 : d;
end
endmodule

// 3 to 8 decoder
module decoder_3to8(A, Y);
input [2:0] A;
output [7:0] Y;
assign
assign
assign
assign
assign
assign
assign
assign

Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]

=
=
=
=
=
=
=
=

(A
(A
(A
(A
(A
(A
(A
(A

==
==
==
==
==
==
==
==

3'd0)?
3'd1)?
3'd2)?
3'd3)?
3'd4)?
3'd5)?
3'd6)?
3'd7)?

1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1

:
:
:
:
:
:
:
:

1'b0;
1'b0;
1'b0;
1'b0;
1'b0;
1'b0;
1'b0;
1'b0;

endmodule

module mux_8to1_16bit(In0, In1, In2, In3, In4, In5, In6, In7, Sel, Out);
parameter BITWIDTH = 16;
input [BITWIDTH-1:0] In0, In1, In2, In3, In4, In5, In6, In7;
input [2:0] Sel;
output [BITWIDTH-1:0] Out;
// instantiate an array of 16 mux_8to1_1bit modules

mux_8to1_1bit mux_8to1_16bit_array[BITWIDTH-1:0](.In0(In0), .In1(In1), .

In2(In2), .In3(In3),
.In4(In4), .In5(In5), .In6(
In6), .In7(In7),
.S(Sel), .Out(Out));
endmodule
module mux_8to1_1bit(In0, In1, In2, In3, In4, In5, In6, In7, S, Out);
input In0, In1, In2, In3, In4, In5, In6, In7;
input [2:0] S;
output Out;
wire tmp0, tmp1;
mux_4to1_1bit mux_up(.InA(In0), .InB(In1), .InC(In2), .InD(In3), .S(S[1:
0]), .Out(tmp0));
mux_4to1_1bit mux_down(.InA(In4), .InB(In5), .InC(In6), .InD(In7), .S(S[
1:0]), .Out(tmp1));
mux_2to1_1bit mux_final(.InA(tmp0), .InB(tmp1), .S(S[2]), .Out(Out));
endmodule
module mux_4to1_1bit(InA, InB, InC, InD, S, Out);
input InA, InB, InC, InD;
input [1:0] S;
output Out;
wire tmp1, tmp0;
mux_2to1_1bit mux_2to1_AC(.InA(InA), .InB(InC), .S(S[1]), .Out(tmp0));
mux_2to1_1bit mux_2to1_BD(.InA(InB), .InB(InD), .S(S[1]), .Out(tmp1));
mux_2to1_1bit mux_2to1_Out(.InA(tmp0), .InB(tmp1), .S(S[0]), .Out(Out));
endmodule
module mux_2to1_1bit(InA, InB, S, Out);
input InA, InB;
input S;
output Out;
wire S_N;
wire A_S, B_S;
not1 not_1_mux(.in1(S), .out(S_N));
nand2 nand_1_mux(.in1(InA), .in2(S_N), .out(A_S));
nand2 nand_2_mux(.in1(InB), .in2(S), .out(B_S));
nand2 nand_3_mux(.in1(A_S), .in2(B_S), .out(Out));
endmodule
module not1 (in1,out);
input in1;
output out;

assign out = ~in1;

endmodule
module nand2 (in1,in2,out);
input in1,in2;
output out;
assign out = ~(in1 & in2);
endmodule