A

ZZZ1

ZZZ2

ZZZ3

ZZZ4

ZZZ5

PCB

LA-7012P

LS-7012P

LS-7013P

LS-7014P

15"DAZ@

15"DA@

15"DA@

15"DA@

15"DA@

Compal Confidential
Schematics Document
2

PAW20
Montevina
3

with Intel Cantiga + ICH9 core logic

REV:1.0A
2010-12-24
4

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Cover Sheet
Size Document Number
Custom

Rev
1.0

LA7012P

Date: Friday, December 24, 2010

Sheet
E

of

41

Compal confidential
File Name :

Clock Generator
page16

For 15"
LS-7012P 8PIN PWR/B
LS7013P Audio/B
LS7014P Touch/B

For 14"
LS-7011P 4PIN PWR/B
LS7013P Audio/B
LS7014P Touch/B

Mobile Penryn

SLG8SP556VTR

uPGA-478 CPU

page4,5,6

H_A#(3..35)
H_D#(0..63)

FSB
667/800MHz

CRT Connector
LVDS
Connector

DDR3-SO-DIMM X2

Intel Cantiga GMCH

page21

GM45
uFCBGA 1329

page22

BANK 0, 1, 2, 3
Dual Channel
DDR3-667/800(1.5V)

page 14,15

up to 4G

page 7,8,9,10,11,12,13

DMI

2Channel Speaker

C-Link

page26

Audio Codec

AZALIA

Analog MIC_Int

page26

CONEXTAN
CX20671 page26

Wire Less Mini

card Slot 1

Intel ICH9-M

6*PCI-E BUS

CMOS Camera

14*USB2.0

page23

page22

SPI ROM
BIOS

BlueTooth CONN

6*SATA serial
page 17,18,19,20

page30

USB CONN X1(Right)

page29

LPC BUS

USB PORT X1(Left)

3

page29

EC

AR8151/8152
10/100/Giga LAN

USB PORT X1(Left)

ENE KB926 E0

page29

page27

page24

HP X 1+
MIC_Ext X1

page30

Card Reader RTS5139

Int.KBD

RJ45 CONN

page32

page25

SPI ROM
BIOS page28

SATA HDD CONN

page28

SATA ODD CONN

Touch Pad

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

page32

page32

Audio Jack SB CONN

Title

Compal Electronics, Inc.

MB Block Diagram

Size Document Number

Custom
Date:

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

E

of

41

SMBUS Control Table

DDR3 Voltage Rails

+5VS
+3VS
power
plane

+1.5VS
+CPU_CORE

+5VALW

+1.5V

+VGA_CORE
+1.8VS

+B
+3VALW

+0.75VS

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
ICH_SMBCLK
ICH_SMBDATA

KB926 SODIMM CLK CHIP WLAN

WWAN

SOURCE

BATT

KB926

+3VALW

V
X
X

+3VALW
KB926

+3VALW
ICH

+3VALW

X
X
X

X
X
V
+3VS

X
X
V
+3VS

ICH9

Therml

X
X
X

X
V
+3VS
X

X
X
V
+3VALW

+1.05VS
State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM
0DDR SO-DIMM
1CLOCK GENERATOR (EXT.)

HEX
A0
A4
D2

ADDRESS

10100000
10100100
11010010

@ FUNCTION
Structure
45@
BT@
CMOS@

Description
45 BOM
Blue Tooth function
CMOS CAMERA function

NON-USE

PCIE PORT LIST

PORT

1
2
3
4
5
6
7
8

USB PORT LIST

PORT

DEVICE

0
1
2
3
4
5
6
7
8
9
10
11
12
13

LAN
WLAN

DEVICE

RIGHT SIDE
LEFT SIDE
CMOS
CARD READER
WIRELESS
BT
USB PORT(ESATA)

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

MB Notes List

Size
B
Date:

Document Number

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

E

of

41

PVT ESD solution.

Please close to R715

ME@
JCPU1A

<7> H_ADSTB#1

<18> H_STPCLK#
<18> H_INTR
<18>
H_NMI
<18>
H_SMI#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

A20M#
FERR#
IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

D5
C6
B4
A3

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
D2
D22
D3
F6

RSVD pins on the CPU

should be left as NO
CONNECT

LOCK#

HIT#
HITM#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_DEFER#
H_DRDY#
H_DBSY#

F1

H_BR0#

D20
B3

H_IERR#
H_INIT#

H4

H_LOCK#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

G6
E4

H_HIT#
H_HITM#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

THERMAL

+1.05VS

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0#

H_IERR#

R714 1

2 56_0402_5%

H_PROCHOT#

R715 1

2 68_0402_5%

+1.05VS

<7>

C864
0.1U_0402_16V4Z
1

H_INIT#

<18>

H_LOCK# <7>
H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>
H_HIT# <7>
H_HITM# <7>

+3VS

XDP_DBRESET# <19>

+3VS

H_PROCHOT#

PROCHOT#
THERMDA
THERMDC

ICH

<18> H_A20M#
<18> H_FERR#
<18> H_IGNNE#

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

IERR#
INIT#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

ADDR GROUP_1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

<7> H_A#[17..35]

K3
H2
K2
J3
L1

BR0#

H5
F21
E1

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

DEFER#
DRDY#
DBSY#

H1
E2
G5

H_ADS#
H_BNR#
H_BPRI#

THERMTRIP#

D21
A24
B25
C7

H_THERMDA
H_THERMDC
H_THERMTRIP#

BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

U1

1
H_THERMTRIP# <8,18>
1
C832

H CLK

C831
0.1U_0402_16V4Z

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
+3VS

R713
10K_0402_5%
2

<7>
<7>
<7>
<7>
<7>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

ADS#
BNR#
BPRI#

CONTROL

<7> H_ADSTB#0

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

XDP/ITP SIGNALS

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

VDD

SMCLK

EC_SMB_CK2
EC_SMB_DA2

DP

SMDATA

H_THERMDC
2
2200P_0402_50V7K
THERM#

DN

ALERT#

1
R716

2
10K_0402_5%

THERM#

GND

H_THERMDA

EC_SMB_CK2 <27>
EC_SMB_DA2 <27>

EMC1402-1-ACZL-TR_MSOP8

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

RESERVED

<7> H_A#[3..16]

ADDR GROUP_0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

Address:100_1100

Penryn

10/01 Add for reduce noise

09/16 Add C834 For ESD

H_RESET#
XDP_DBRESET#
3

XDP Reserve for debug , Please close to CPU side

@
C651

+3VS

100P_0402_50V8J
2

XDP_DBRESET# R7181

2 @ 1K_0402_5%

XDP_TDI

R8 1

54.9_0402_1%

XDP_TMS

R9 1

54.9_0402_1%

XDP_TDO

R10 1

2 @ 54.9_0402_1%

XDP_TRST#

R11 1

54.9_0402_1%

XDP_TCK

R12 1

54.9_0402_1%

1
C834
0.1U_0402_16V4Z

+1.05VS

Place closely pin C1

Place closely pin C20

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Penryn(1/3)-AGTL+THM,FAN

Size Document Number

Custom
Date:

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

E

of

41

ME@
JCPU1D
ME@
JCPU1B

<7> H_DSTBN#0
<7> H_DSTBP#0
<7> H_DINV#0
<7> H_D#[16..31]

R14
R16

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

+CPU_GTLREF
TEST1
1
2 @ 1K_0402_5%
TEST2
1
2 @ 1K_0402_5%
T1
TEST3
T2
TEST4
TEST5
T3
T4
TEST6
T157
TEST7
CPU_BSEL0
<16> CPU_BSEL0
CPU_BSEL1
<16> CPU_BSEL1
CPU_BSEL2
<16> CPU_BSEL2

AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

DATA GRP 1

<7> H_DSTBN#1
<7> H_DSTBP#1
<7> H_DINV#1

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

DATA GRP 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

DATA GRP 2

H_D#[0..15]

DATA GRP 3

<7>

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3

R719
R15
R720
R18

H_D#[32..47]

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

<7>

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63]

<7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
1
1
1
1

2
2
2
2

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP# <8,18,40>
H_DPSLP# <18>
H_DPWR# <7>
H_PWRGOOD <18>
H_CPUSLP# <7>
H_PSI#
<40>

Penryn

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 5mils and Space 25mils (55Ohms)

FSB

BCLK

BSEL2

BSEL1

BSEL0

533

133

667

166

800

200

1067

266

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

Penryn
.

Layout note: Z0=55 ohm

0.5" max for GTLREF.
+1.05VS
1

09/29 Add for power noise

PVT for ESD solution

+CPU_GTLREF

R19
1K_0402_1%
H_DPRSTP#

H_DPRSTP#

H_DPSLP#

H_PSI#

H_PWRGOOD

R20
2K_0402_1%

C652
470P_0402_50V7K

C630
470P_0402_50V7K

C636
100P_0402_50V8J

C642
470P_0402_50V7K

Close to CPU pin AD26

within 500mils.

Close to Power IC
(PU9.12) within
500mils.

Close to CPU pin E5

within 500mils.

Close to CPU pin B5

within 500mils.

Compal Secret Data

Security Classification
Issued Date

Close to Power IC

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

C637
330P_0402_50V7K

Close to CPU pin D6

within 500mils.

Compal Electronics, Inc.

Penryn(2/3)-AGTL+GND

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

of

41

+1.05VS Place these inside socket cavity on L8

+CPU_CORE

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE

1
C81
330U_D2E_2.5VM_R9M

+
2

(North side Secondary)

330U_D2E_2.5VM_R9M
1
1
+ C86
2

330U_D2E_2.5VM_R9M
1

+ C82

2
330U_D2E_2.5VM_R9M

0.1U_0402_10V6K

C9

0.1U_0402_10V6K

C10

0.1U_0402_10V6K

C11

0.1U_0402_10V6K

C12

0.1U_0402_10V6K

C835
0.1U_0402_10V6K

2
D

SF000002O00 to SGA19331D10

+CPU_CORE

1
Place these capacitors on L1
(North side,Secondary Layer)
2

C18
10U_0805_6.3V6M

C19
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C836
10U_0805_6.3V6M

+CPU_CORE

1
+1.05VS

Place these capacitors on L1

(North side,Secondary Layer)
2

C26
10U_0805_6.3V6M

C27
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C837
10U_0805_6.3V6M

1
+

C60
330U_D2E_2.5VM_R9M

+CPU_CORE

2
1
Place these capacitors on L1
(South side,Secondary Layer)
2

C35
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C37
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C39
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

C42
10U_0805_6.3V6M

NEAR PIN B26

+CPU_CORE

20mils

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AF7

VCCSENSE

AE7

VSSSENSE

<40>
<40>
<40>
<40>
<40>
<40>
<40>

+1.5VS

1
Place these capacitors on L1
(South side,Secondary Layer)
2

C43
10U_0805_6.3V6M

C44
10U_0805_6.3V6M

C45
10U_0805_6.3V6M

C46
10U_0805_6.3V6M

C47
10U_0805_6.3V6M

C48
10U_0805_6.3V6M

C49
10U_0805_6.3V6M

C50
10U_0805_6.3V6M

Mid Frequence Decoupling

VCCSENSE <40>
VSSSENSE <40>

Penryn

09/29 Add for power noise

C8

+ C94

PVT Change C82 and C94 from

0.01U_0402_16V7K

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

C51

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

+CPU_CORE

ME@
JCPU1C

10U_0805_10V4Z
C52

+CPU_CORE

Close to Power IC
The trace width/space/other is

CPU_VID0

18/7/25.

CPU_VID1
CPU_VID2

Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
Length matched to within 25 mils.

CPU_VID3
CPU_VID4
CPU_VID5

C650

100P_0402_50V8J

C649

100P_0402_50V8J

C648

100P_0402_50V8J

C647

100P_0402_50V8J

C646

100P_0402_50V8J

C644

100P_0402_50V8J

1
C643

100P_0402_50V8J

CPU_VID6

+CPU_CORE
R21
100_0402_1%
2

VCCSENSE

R22
100_0402_1%
1
2

VSSSENSE

Close to CPU pin

within 500mils.

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(3/3)-PWR+Bypass

Size Document Number

Custom
Date:

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

1

of

41

H_A#[3..35]

<4>
<5>

H_RESET#
H_CPUSLP#

H_RESET#
H_CPUSLP#
H_VREF

C12
E11
A11
B11

H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

J8
L3
Y13
Y1

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

L10
M7
AA5
AE6

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L9
M8
AA6
AE5

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

B15
K13
F13
B13
B14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

B6
F12
C8

H_RS#0
H_RS#1
H_RS#2

CANTIGA ES_FCBGA1329
GM45@

H_ADS#
<4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR#
<4>
H_BPRI# <4>
H_BR0#
<4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

<5>
<5>
<5>
<5>

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

<5>
<5>
<5>
<5>

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<5>
<5>
<5>
<5>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<4>
<4>
<4>
<4>
<4>

H_RS#0
H_RS#1
H_RS#2

<4>
<4>
<4>

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+1.05VS

+1.05VS
1

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

<4>

R23
1K_0402_1%

R24
221_0603_1%
H_VREF

H_RCOMP

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_SWNG

H_SWING
H_RCOMP

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

1
R25
2K_0402_1%

1
C53
0.1U_0402_16V4Z

R26
24.9_0402_1%

R27
100_0402_1%
2

C5
E3

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H_SWNG
H_RCOMP

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63]

HOST

U3A
<5>

within 100 mils from NB

C54
0.1U_0402_16V4Z

Near B3 pin

U3

PVT ESD solution.

Please close to R23
GL40

+1.05VS

GL40@

C70
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(1/7)-AGTL+

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

of

41

U3B

1 = iTPM Host Interface is Disabled

*(Default)

0 = Intel Management Engine Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality

Internal pull-up

CFG7

1 = Intel Management Engine Crypto TLS cipher suite with

confidentiality *(Default)

CFG10

Internal pull-up

0 = Lane Reversal Enable

1 = Normal Operation *(Default)

Internal pull-up

0 = PCIe Loopback Enable

1 = Disable*(Default)

Internal pull-up

01
00
10
11

Internal pull-up

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled *(Default)

CFG[13:12]

CFG16

AY21

= All Z Mode Enabled

= Reserved
= XOR Mode Enabled
= Normal Operation *(Default)

BG23
BF23
BH18
BF18

CFG19 Internal pull-down

0 = Normal Operation
1 = DMI Lane Reversal Enable

CFG20

0 = Only PCIE or [SDVO/DP/HDMI] is operational.

Internal pull-down

(PCIE/SDVO select)

RSVD15
RSVD16
RSVD17
RSVD20

RSVD

CFG9

B31
B2
M1

RSVD22
RSVD23
RSVD24
RSVD25

*(Default)
* (Default)

CLK

1 = PCIE/[SDVO/DP/HDMI] are operating simu.

+1.05VS

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

BC28
AY28
AY36
BB36

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

BA17
AY16
AV16
AR13

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1

BD17
AY17
BF15
AY13

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BG22
BH21

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BF28
BH28

SMRCOMP_VOH
SMRCOMP_VOL

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

AV42
AR36
BF17
BC36

+DDR_MCH_REF
SM_PWROK
SM_REXT
SM_DRAMRST#

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B38
A38
E41
F41

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

PEG_CLK
PEG_CLK#

F43
E43

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AE41
AE37
AE47
AH39

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AE40
AE38
AE48
AH40

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AE35
AE43
AE46
AH42

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AD35
AE44
AF46
AH43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

B33
B32
G33
F33
E33

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

<14>
<14>
<15>
<15>

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

For DDR3 : 1.5V power rail

For DDR2 : 1.8V power rail

<14>
<14>
<15>
<15>

+1.5V

M_ODT0
M_ODT1
M_ODT2
M_ODT3
1
R29

<14>
<14>
<15>
<15>

R28
80.6_0402_1%

20mil

For Crestline: 20ohm

For Calero: 80.6ohm
For Cantiga: 80.6ohm

2
80.6_0402_1%
R30
R53

1
1

2
2

0_0402_5%
@ 12K_0402_5%

R721 1
R32 1
SM_DRAMRST#

<14,15>

CLK_MCH_DREFCLK
<16>
CLK_MCH_DREFCLK#
<16>
MCH_SSCDREFCLK
<16>
MCH_SSCDREFCLK#
<16>

1.5V_PGOOD <39>
DDR3_SM_PWROK <27>

2 @ 10K_0402_5%
499_0402_1%
2

SM_DRAMRST# is only for DDR3.

DDR2 left it No Connect
+1.5V

CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>

MCH_CFG_12
MCH_CFG_13

R46

2@ 2.21K_0402_1%

MCH_CFG_16

R49
R50

1
1

2@ 4.02K_0402_1%
2@ 4.02K_0402_1%

MCH_CFG_19
MCH_CFG_20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST#_R
H_THERMTRIP#
DPRSLPVR

R29
B7
N33
P32
AT40
AT11
T20
R32

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26

0_0402_5%

VGATE

R727 1

2 @ 0_0402_5%

PLT_RST#

R728 1

2 100_0402_5%

PM_POK_R
<19> PM_BMBUSY#
<5,18,40> H_DPRSTP#
<14,15> PM_EXTTS#0

PLT_RST#_R

<4,18> H_THERMTRIP#
<19,40> DPRSLPVR

Place closely pin U3.R32

Place closely pin PR132.2

DPRSLPVR

DPRSLPVR

1
C861
1000P_0402_50V7K

C862
1000P_0402_50V7K

09/16 Add C838 For noise

Place closely pin AT11

Place closely pin B7

Place closely pin AR36

H_DPRSTP#
A

SM_PWROK

PLT_RST#_R
1

1
C838
0.1U_0402_16V4Z

1
C631
470P_0402_50V7K

C638
2

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

<19>
<19>
<19>
<19>

<19>
<19>
<19>
<19>

1
C55
0.01U_0402_25V7K

R724
3.01K_0402_1%

SMRCOMP_VOL
1

1
C57
0.01U_0402_25V7K

C58
2.2U_0603_6.3V4Z

R43
1K_0402_1%

R726
1K_0402_1%
GFX_VR_EN

C34

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AH37
AH36
AN36
AJ35
AH34

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#

N28
M28
G36
E36
K36
H36

TSATN#

B12

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

B28
B30
B29
C29
A28

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF

CL_CLK0
<19>
CL_DATA0 <19>
M_PWROK <19>
CL_RST# <19>

T110
T109
SDVO_SCLK
MCH_CLKREQ#
MCH_ICH_SYNC#
MCH_TSATN#

R57

C59
0.1U_0402_16V4Z

R729
499_0402_1%

Strap Pin Table

SDVO_CTRLDATA
(Internal pull-down)

0 = SDVO interface disabled *(Default)

1 = SDVO interface enabled

DDPC_CTRLDATA
(Internal pull-down)

0 = Digital display (iHDMI/DP) interface disabled *(Default)

1 = Digital display (iHDMI/DP) interface enabled

MCH_CLKREQ# <16>
MCH_ICH_SYNC#
<19>
1

2 56_0402_5%

+3VS
SDVO_SCLK
2
R56 @

+1.05VS

1 2.2K_0402_5%

Notice: Please check HDA power rail to select HDA controller.

GM45@

Issued Date

Compal Secret Data

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C56
2.2U_0603_6.3V4Z

+1.05VS

Security Classification

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

For independent Power Rail : connect to PWM CORE VID

For Common Power Rail : left it No Connect

CANTIGA ES_FCBGA1329

100P_0402_50V8J

<19>
<19>
<19>
<19>

For AMT function

NC

PM

<17,23,24>

PM_EXTTS#0
PM_EXTTS#1

ME

<19,40>

R51

+3VS

R48
10K_0402_5%

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

SMRCOMP_VOH

2@ 2.21K_0402_1%
2@ 2.21K_0402_1%

<19,27> ICH_POK

1
1

<19>
<19>
<19>
<19>

R44
R45

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

MCH_CFG_9
MCH_CFG_10

GRAPHICS VID

2@ 2.21K_0402_1%
2@ 2.21K_0402_1%

MISC

1
1

<27>

HDA

R41
R42

TSATN#

DMI

+3VS

TSATN#

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

MCH_CFG_5
MCH_CFG_6
MCH_CFG_7

2@ 2.21K_0402_1%
2@ 2.21K_0402_1%
2@ 2.21K_0402_1%

3
1
Q42
MMBT3904_SOT23-3
@

<16> MCH_CLKSEL0
<16> MCH_CLKSEL1
<16> MCH_CLKSEL2

CFG

R725 1
R39 1
R40 1

T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28

R47
10K_0402_5%

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

R723
1K_0402_5%
@

MCH_TSATN#

R64
10K_0402_1%

C61
0.1U_0402_16V4Z

R34
1K_0402_1%

+3VS

1
R722
54.9_0402_1%
@

R58
10K_0402_1%

+DDR_MCH_REF
<14>
<14>
<15>
<15>

R33
1K_0402_5%
@

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

+1.5V

AR24
AR21
AU24
AV20

Layout Note:
+DDR_MCH_REF trace
width and spacing is 20/20.
CLOSE TO PIN.AV42

<14>
<14>
<15>
<15>

can support disble by SW.

0 = iTPM Host Interface is enabled

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

Internal pull-up

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

CFG6

0 = DMI x 2
1 = DMI x 4 *(Default)

AP24
AT21
AV24
AU20

Internal pull-up

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

CFG5

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

COMPENSATION

M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24

011 = FSB667
010 = FSB800
000 = FSB1067

CFG[2:0]

DDR CLK/ CONTROL/

Strap Pin Table

Title

Compal Electronics, Inc.

Cantiga(2/7)-DMI/DDR/STRP

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

of

41

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_RAS#
SA_CAS#
SA_WE#

BB20
BD20
AY20

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS[0..2]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<14><15> DDR_B_D[0..63]

DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_WE# <14>

DDR_A_DM[0..7]

<14>

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

MEMORY

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

DDR_A_MA[0..14]

<14>

<14>

<14>

AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3

CANTIGA ES_FCBGA1329
GM45@

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

BC16
BB17
BB33

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

SB_RAS#
SB_CAS#
SB_WE#

AU17
BG16
BF14

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

BD21
BG18
AT25

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

U3E

SYSTEM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR

AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12

SYSTEM

U3D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

<14> DDR_A_D[0..63]

DDR

DDR_B_BS[0..2]

<15>

DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_WE# <15>

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

<15>

<15>

DDR_B_DQS#[0..7]

DDR_B_MA[0..14]

<15>

<15>

CANTIGA ES_FCBGA1329
GM45@

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(3/7)-DDR3 A/B CH

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

of

41

Place the resistor within 500mils

(1.27mm)of the (G)MCH

2 10K_0402_5%

L_CTRL_CLK

R731 1

2 10K_0402_5%

L_CTRL_DATA

2
2.2K_0402_5%
2
2.2K_0402_5%

EDID_CLK

1
R732
1
R734

<22> EDID_CLK
<22> EDID_DATA
<22> GMCH_ENVDD

EDID_DATA

1
R735

For Cantiga:2.37kohm
For Crestline:2.4kohm
For Calero: 1.5Kohm

ENBKL

GMCH_PWM
ENBKL
L_CTRL_CLK
L_CTRL_DATA
EDID_CLK
EDID_DATA
GMCH_ENVDD

<22> GMCH_PWM
<27>
ENBKL

<22> LVDS_ACLK#
<22> LVDS_ACLK

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

C44
B43
E37
E38

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL

LVDS_ACLK#
LVDS_ACLK

C41
C40
B37
A37

LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDS_A0#
LVDS_A1#
LVDS_A2#

H47
E46
G40
A40

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

LVDS_A0
LVDS_A1
LVDS_A2

H48
D45
F40
B40

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3

A41
H38
G37
J37

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

B42
G38
F37
K37

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

2 LVDS_IBG
2.37K_0402_1%

R259
100K_0402_1%

<22> LVDS_A0#
<22> LVDS_A1#
<22> LVDS_A2#

Note: All LVDS data

signals/and it's compliments
should be routed
Differentially

<22> LVDS_A0
<22> LVDS_A1
<22> LVDS_A2

R481 1
R482 1
R483 1

2 75_0402_5%
2 75_0402_5%
2 75_0402_5%

2
2
2

150_0402_1%
150_0402_1%
150_0402_1%

<21> DAC_BLU

DAC_RED
DAC_GRN
DAC_BLU

<21> DAC_GRN
<21> DAC_RED

<21> CRT_HSYNC

TVA_DAC
TVB_DAC
TVC_DAC

H24

TV_RTN

C31
E32

TV_DCONSEL_0
TV_DCONSEL_1

DAC_BLU

E28

CRT_BLUE

DAC_GRN

G28

CRT_GREEN

DAC_RED

J28

CRT_RED

G29

CRT_IRTN

H32
J32
J29
E29

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF

L29

CRT_VSYNC

<21> CRT_DDC_CLK
<21> CRT_DDC_DATA
1
2
R74
33_0402_5%

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC_R

CRT_VSYNC_R

20mil
R75

33_0402_5%

T37
T36

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

PEGCOMP

Please check Power

source if want
support IAMT

<21> CRT_VSYNC

VGA

R736 1
R72 1
R73 1

F25
H25
K25

PEG_COMPI
PEG_COMPO

R733 49.9_0402_1%

TV

Layout Note: Place 150 termination

resistors close to GMCH

TVA_DAC
TVB_DAC
TVC_DAC

+VCC_PEG

LVDS

L32
G32
M32
M33
K33
J33
M29

GRAPHICS

R730 1

PCI-EXPRESS

PEGCOMP trace width

and spacing is 20/25 mils.

U3C

+3VS

10/01
change R74,R75 from 30ohm to 33ohm

CANTIGA ES_FCBGA1329

GM45@
R78
1.02K_0402_1%

For Cantiga:1.02kohm
For Crestline:1.3kohm
For Calero: 255ohm

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.

Cantiga(4/7)-VGA/LVDS

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

10

of

41

+3VS_DAC_CRT

+1.05VS

4.7U_0805_10V4Z
C92

1
1U_0603_10V4Z

C93

AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16

C66
C74

C75

CRT
PLL

+1.05VS_HPLL

C84
0.1U_0402_16V4Z

440mA
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

B22
B21
A21

R737
1
2
0_0805_5%

+1.05VS_HPLL: 24mA
L33 (4.7UF*1, 0.1UF*1)
2
1
+1.05VS
MBK2012121YZF_2P

POWER

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9

MCK3225151YZF 1210

+1.5VS_TVDAC

+1.5VS
R739

C85

2.2U_0603_6.3V4Z

+V1.05VS_AXF

2
1
0_0603_5%

10U_0805_10V4Z

10U_0805_10V4Z

+1.05VS

C89
0.1U_0402_16V4Z

1
2
0_0805_5%
1

C88
0.022U_0402_16V7K

0.1U_0402_16V4Z

747.5mA
C91

C83

+1.05VS_A_SM

VCCA_PEG_PLL

+1.5V

R83

C87

50mA
AA48

VCCA_PEG_BG

C80

20 mils
+1.05VS_PEGPLL

R740

C90
220U_6.3V_M

VSSA_LVDS

+1.5VS_PEG_BG

R738
2
1
0_0603_5%

+1.05VS

OSCON

VCCA_LVDS

R81
0_0603_5%

VCC_SM_CK: 119.85mA
(10UF*1, 0.1UF*1)

C79

AD48

VCCA_SM:720mA
(22UF*2, 4.7UF*1, 1UF*1)

J47

VCCA_MPLL

+1.5V_SM_CK

+1.05VS_DPLLB

C78

+1.5VS

J48

0.41mA
+1.5VS_PEG_BG: 0.414mA
(0.1UF*1)

10mA

C77

1000P_0402_50V7K
C76

0.1U_0402_16V4Z

VCCA_HPLL

AE1

24mA

139.2mA

10U_0805_10V4Z

AD1

+1.05VS_MPLL

+1.05VS_DPLLA
+1.05VS_DPLLB: 64.8mA
(470UF*1, 0.1UF*1)

0.1U_0402_16V4Z

VCCA_DPLLB

+1.05VS_HPLL

10U_0805_10V4Z

+1.8V_TXLVDS

VCCA_DPLLA

A PEG A LVDS

F47

32.4mA
L48

+1.05VS_DPLLB

VTT

32.4mA
+1.05VS_DPLLA

+1.05VS

C839

VSSA_DAC_BG

MCK3225151YZF 1210

1U_0603_10V4Z

B25

4.7U_0805_10V4Z

C73
10U_0805_10V4Z

C72
0.022U_0402_16V7K

C71
0.1U_0402_16V4Z

1
2
R82
10_0603_5%

C69

+3VS_DAC_BG

+3VS

VCCA_DAC_BG

+1.05VS

+V1.05VS_AXF

10U_0805_10V4Z

+3VS_DAC_BG

A25

C68

5mA

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

C67

VCCA_DAC_BG: 2.68mA (0.1UF*1, 0.01UF*1)

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

R80

10U_0805_10V4Z

B27
A26

0.47U_0402_6.3V6K

73mA

+3VS_DAC_CRT

+1.05VS_DPLLA

852mA
0.1U_0402_16V4Z

OSCON
220U_6.3V_M
C65
1

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

VCC_AXF: 321.35mA
(10UF*1, 1UF*1)

20 mils

U3H

4.7U_0805_10V4Z

AXF

C64
10U_0805_10V4Z

C63
0.022U_0402_16V7K

2
C62
0.1U_0402_16V4Z

1
R79
0_0603_5%

A SM

+3VS

VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)
C

37.95mA

+VCC_PEG

DMI

VCC_HDA

+1.5VS_TVDAC
B

M25

1mA
L28

+1.5VS_QDAC

VCCD_TVDAC
VCCD_QDAC

157.2mA
+1.05VS_HPLL

AF1

+1.05VS_PEGPLL

AA47

50mA

VCCD_HPLL
VCCD_PEG_PLL

D TV/CRT

35mA

+1.5VS_PEG_PLL: 50mA
(0.1UF*1)

2
1
0_0603_5%

+1.8VS

+1.8V_TXLVDS: 118.8mA
(22UF*1, 1000PF*1)

+1.05VS
+VCC_PEG
R744

+1.05VS

C108

OSCON

C104
220U_6.3V_M

2.2U_0603_6.3V4Z

2
1
0_0805_5%

20mils
+1.05VS

VTTLF1
VTTLF2
VTTLF3

+VCC_DMI

A8
L1
AB2

+VCCP_D

D38

2 @
+1.05VS
RB751V_SOD323

R746 @
2
1
10_0402_5%

R747
2
1
0_0402_5%

+3VS_HV

+3VS

C116

GM45@

10U_0805_10V4Z

CANTIGA ES_FCBGA1329

C115

10U_0805_10V4Z

C114

LVDS

2.2U_0603_6.3V4Z

1U_0603_10V4Z

VCCD_LVDS_1
VCCD_LVDS_2

+VCC_DMI

VCC_DMI: 456mA
(0.1UF*1)

0.47U_0402_6.3V6K
C113

+1.8V_LVDS

AH48
AF48
AH47
AG47

0.47U_0402_6.3V6K
C112

M38
L37

C100

L1
BLM18PG121SN1D_0603
2
1

0.47U_0402_6.3V6K
C111

30mA

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4

VTTLF

A32

+1.05VS_PEGPLL

TV

PEG

V48
U48
V47
U47
U46

456mA

C106
0.1U_0402_16V4Z

HDA

1782mA
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

R742

C109

C107

C35
B35
A35

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C105
0.022U_0402_16V7K

C99
+3VS_HV

+1.8V_TXLVDS

20 mils

+1.05VS

10U_0805_10V4Z

VCCA_TV_DAC_1
VCCA_TV_DAC_2

K47

+1.8V_TXLVDS

105.3mA
VCC_HV_1
VCC_HV_2
VCC_HV_3

1.05VS_MPLL: 139.2mA
(22UF*1, 0.1UF*1)

C102

B24
A24

+3VS_TVDAC

0_0603_5%

L34

80mA
VCC_TX_LVDS

+1.05VS_MPLL

2
1
MBK2012121YZF_2P

C103

+3VS_TVDAC

+1.5V_SM_CK

10U_0805_10V4Z

C98

BF21
BH20
BG20
BF20

C101
1000P_0402_50V7K

VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z

AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23

+3VS_TVDAC: 40mA
(0.1UF*1, 0.01UF*1 for
each DAC)
79mA

+3VS
R743
1

C97

10U_0805_10V4Z

1
C96

C95

1U_0402_6.3V4Z

2
1
0_0603_5%

HV

R741

A CK

+1.05VS_A_SM_CK

VCCA_SM_CK: 220mA
(22UF*1, 2.2UF*1, 0.1UF*1)

SM CK

149.5mA

R745
2
1
0_0805_5%

10/01 Danson
Change D38 from SC1H751H010 to SCS00000Z00 .

VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)

+1.5VS_QDAC

1.8V_LVDS: 60.311111mA
(1UF*1)

+1.8V_LVDS

R748
R98

C840
1U_0603_10V4Z

+1.5VS

C120
10U_0805_10V4Z

2
1
0_0603_5%

C119
10U_0805_10V4Z

C118

0.1U_0402_16V4Z

C117
1U_0402_6.3V4Z

2
1
0_0603_5%

+1.8VS

1
A

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(6/7)-VCC-1

Size

Document Number

Rev
1.0

LA7012P
Date:

Sheet

Friday, December 24, 2010

1

11

of

41

U3F

C139
0.1U_0402_16V4Z
2 @

+1.05VS

VCC

AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

+1.05VS
10U_0805_10V4Z

0.1U_0402_16V4Z

1
C851
1U_0603_10V4Z

C853

2
C852
220U_6.3V_M

C854

C138

10U_0805_10V4Z

OSCON

VCC_AXG_SENSE
VSS_AXG_SENSE

PLACE AS CLOSE PIN AS COULD.

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7
1

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.47U_0402_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

Compal Secret Data

Security Classification
Issued Date

0.1U_0402_16V4Z

GM45@

0.1U_0402_16V4Z

2
CANTIGA ES_FCBGA1329
A

C857

VCC_AXG_SENSE
VSS_AXG_SENSE

C856

T11
T12

C855

AJ14
AH14

CANTIGA ES_FCBGA1329
GM45@

1 C841
4.7U_0603_6.3V6K

C143

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42

C142

Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14

C141

VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC

8000mA

C129
0.22U_0402_10V4Z

C140

BA36
BB24
BD16
BB21
AW16
AW13
AT13

C845
0.1U_0402_16V4Z

GFX

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44

GFX NCTF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

VCC

EMI +1.5V decoupling

NCTF

C850
0.1U_0402_16V4Z
@

VCC

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35

POWER

AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32

POWER

VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60

SM

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35

VCC

C844
220U_6.3V_M

C846

C849

0.1U_0402_16V4Z
C848

0.22U_0402_10V4Z
C847

0.22U_0402_10V4Z
C843

10U_0805_10V4Z

VCC CORE

3060mA

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

0.01U_0402_16V7K

OSCON

U3G

10U_0805_10V4Z
C842

+1.05VS

AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29

VCC SM LF

+1.5V

AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33

+1.05VS

Check : power

4140mA

Title

Compal Electronics, Inc.

Cantiga(6/7)-VCC-1

Size

Document Number

Rev
1.0

LA7012P
Date:

Friday, December 24, 2010

Sheet
1

12

of

41

VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233

BA16

VSS_235

AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11

VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

VSS

VSS NCTF

U3J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199

CANTIGA ES_FCBGA1329
GM45@

VSS SCB

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

NC

U3I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

VSS_351
VSS_352
VSS_353
VSS_354

U24
U28
U25
U29

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5

BH48
BH1
A48
C1
A3

NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

CANTIGA ES_FCBGA1329
GM45@

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(7/7)-GND

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

13

of

41

+VREF_DQ_DIMMA

+1.5V

+1.5V

4BA2/6W

<9> DDR_A_D[0..63]

+1.5V
1

<9> DDR_A_DM[0..7]
JDIMM1

DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

Pre MP ADD for ESD solution

<9> DDR_A_DQS[0..7]
DDR_A_D4
DDR_A_D5

<9> DDR_A_DQS#[0..7]
<9> DDR_A_MA[0..14]

DDR_A_DQS#0
DDR_A_DQS0

R297
1K_0402_1%

+1.5V

Near R297

+VREF_DQ_DIMMA
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D6
DDR_A_D7

C659
0.1U_0402_16V4Z

C347
2.2U_0603_6.3V4Z

2
D

C303
0.1U_0402_10V6K

DDR_A_D0
DDR_A_D1

R305
1K_0402_1%

DDR_A_D12
DDR_A_D13

+VREF_DQ_DIMMA

DDR_A_DM1
SM_DRAMRST#

SM_DRAMRST#

<8,15>

DDR_A_D14
DDR_A_D15

For Arranale only +VREF_DQ_DIMMA

supply from a external 1.5V voltage divide
circuit.
07/17/2009

DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29

Place closely pin JDIMM1.30

DDR_A_DQS#3
DDR_A_DQS3

SM_DRAMRST#
DDR_A_D30
DDR_A_D31
1

C639

@
C

<8> DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

<9> DDR_A_BS2

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<8> M_CLK_DDR0
<8> M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

<9> DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

<9> DDR_A_WE#
<9> DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

<8> DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D34
DDR_A_D35

DDR_A_DM4
2

DDR_A_D38
DDR_A_D39

Layout Note:
Place near DIMM

+1.5V

C316
0.1U_0402_10V6K

1
+
2

C569
220U_6.3V_M

OSCON

6*0603 10uf (PER CONNECTOR)

DDR_A_DM6

VTT(0.75V) =

DDR_A_D54
DDR_A_D55

3*0805 10uf

4*0402 1uf

VREF =

DDR_A_D60
DDR_A_D61

1*0402 0.1uf

DDR_A_DQS#7
DDR_A_DQS7

+0.75VS

1*0402 2.2uf

VDDSPD (3.3V)=

C301
10U_0603_6.3V6M

PM_EXTTS#0 <8,15>
CLK_SMBDATA <15,16>
CLK_SMBCLK <15,16>

1U_0603_10V4Z

PM_EXTTS#0

1*0402 2.2uf

1U_0603_10V4Z

1*0402 0.1uf

DDR_A_D62
DDR_A_D63

+0.75VS

1/76BA1/86W

FOX_AS0A626-U4RN-7F
ME@

Compal Secret Data

Security Classification
Issued Date

DDR3 SO-DIMM A H=4mm Reverse type

5

C317
0.1U_0402_10V6K

C315
0.1U_0402_10V6K

C314
0.1U_0402_10V6K

C308

10U_0603_6.3V6M

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

DDR_A_D52
DDR_A_D53

C570

10U_0603_6.3V6M

VDDQ(1.5V) =

DDR_A_D46
DDR_A_D47

C309

DDR_A_DQS#5
DDR_A_DQS5

10U_0603_6.3V6M

DDR_A_D44
DDR_A_D45

C300

DDR_A_D36
DDR_A_D37

+VREF_DQ_DIMMA

10U_0603_6.3V6M

<8>

M_ODT1 <8>

C606

206

DDR_CS0_DIMMA#
M_ODT0 <8>

C310

G2

M_ODT1

1U_0603_10V4Z

G1

DDR_A_BS1 <9>
DDR_A_RAS# <9>

DDR_CS0_DIMMA#
M_ODT0

C607

205

M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>

DDR_A_BS1
DDR_A_RAS#

1U_0603_10V4Z

R571
10K_0402_5%

C617
0.1U_0402_10V6K

C608
2.2U_0603_6.3V4Z

+3VS
A

M_CLK_DDR1
M_CLK_DDR#1

C605

DDR_A_D58
DDR_A_D59
1 R570
2
10K_0402_5%

DDR_A_MA2
DDR_A_MA0

10U_0603_6.3V6M

DDR_A_DM7

1224 Change C639 to @ for download image fail issue

DDR_A_MA6
DDR_A_MA4

C581

DDR_A_D56
DDR_A_D57

DDR_A_MA11
DDR_A_MA7

C586

DDR_A_D50
DDR_A_D51

10U_0603_6.3V6M

DDR_A_DQS#6
DDR_A_DQS6

100P_0402_50V8J

DDR_A_MA14

C588

DDR_A_D48
DDR_A_D49

<8>

10U_0603_6.3V6M

DDR_A_D42
DDR_A_D43

DDR_CKE1_DIMMA

C589

DDR_A_DM5

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

10U_0603_6.3V6M

DDR_A_D40
DDR_A_D41

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

C355
2.2U_0603_6.3V4Z

DDR_A_DQS#4
DDR_A_DQS4

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

C346
0.1U_0402_10V6K

DDR_A_D32
DDR_A_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_CKE1_DIMMA

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

DDRIII SO-DIMM A

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

14

of

41

+VREF_DQ_DIMMB

+1.5V

4BA2/6W

+1.5V

<9> DDR_B_DQS#[0..7]
<9> DDR_B_D[0..63]
+1.5V

JDIMM2

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

<9> DDR_B_DM[0..7]
DDR_B_D4
DDR_B_D5

<9> DDR_B_DQS[0..7]

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

R341
1K_0402_1%

<9> DDR_B_MA[0..14]

DDR_B_DQS#0
DDR_B_DQS0

+VREF_DQ_DIMMB
2

DDR_B_DM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

DDR_B_D6
DDR_B_D7

1
C384

C382

DDR_B_D0
DDR_B_D1

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_B_D12
DDR_B_D13
R340
1K_0402_1%

DDR_B_DM1
SM_DRAMRST#

SM_DRAMRST#

<8,14>

+VREF_DQ_DIMMB

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

For Arranale only +VREF_DQ_DIMMB

supply from a external 1.5V voltage divide
circuit.
07/17/2009

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

Place closely pin JDIMM2.30

DDR_B_D30
DDR_B_D31

SM_DRAMRST#

C640

<8> DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

<9> DDR_B_BS2

DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

<8> M_CLK_DDR2
<8> M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

<9> DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

<9> DDR_B_WE#
<9> DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

<8> DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

M_ODT3 <8>

DDR_B_D36
DDR_B_D37

C306
0.1U_0402_10V6K

C305
0.1U_0402_10V6K

C304
0.1U_0402_10V6K

DDR_B_D44
DDR_B_D45

C307
0.1U_0402_10V6K

C312

C575

DDR_B_D38
DDR_B_D39

+1.5V
10U_0603_6.3V6M

DDR_B_DM4

10U_0603_6.3V6M

+VREF_DQ_DIMMB

C590

206

M_ODT3

Layout Note:
Place near DIMM

<8>

10U_0603_6.3V6M

G2

DDR_CS2_DIMMB#
M_ODT2 <8>

DDR_B_DQS#5
DDR_B_DQS5

VDDQ(1.5V) =

DDR_B_D46
DDR_B_D47

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

DDR_B_D52
DDR_B_D53

Layout Note:
Place near DIMM

VTT(0.75V) =

DDR_B_DM6

3*0805 10uf

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61

1*0402 0.1uf

4*0402 1uf
+0.75VS

1*0402 2.2uf

VDDSPD (3.3V)=

DDR_B_DQS#7
DDR_B_DQS7

1*0402 0.1uf

1*0402 2.2uf

DDR_B_D62
DDR_B_D63

PM_EXTTS#0

PM_EXTTS#0 <8,14>
CLK_SMBDATA <14,16>
CLK_SMBCLK <14,16>
+0.75VS

1/76BA1/86W

C598
1U_0603_10V4Z

G1

DDR_B_BS1 <9>
DDR_B_RAS# <9>

DDR_CS2_DIMMB#
M_ODT2

10U_0603_6.3V6M

205

M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>

DDR_B_BS1
DDR_B_RAS#

C299
1U_0603_10V4Z

M_CLK_DDR3
M_CLK_DDR#3

C595
1U_0603_10V4Z

C616
0.1U_0402_10V6K

C618
2.2U_0603_6.3V4Z

+3VS

1 R572
2
10K_0402_5%
1
2
R573 10K_0402_5%

DDR_B_MA2
DDR_B_MA0

C596
10U_0603_6.3V6M

DDR_B_D58
DDR_B_D59

DDR_B_MA6
DDR_B_MA4

C313

DDR_B_DM7

1224 Change C640 to @ for download image fail issue

10U_0603_6.3V6M

DDR_B_D56
DDR_B_D57

DDR_B_MA11
DDR_B_MA7

C311

DDR_B_D50
DDR_B_D51

100P_0402_50V8J

DDR_B_MA14

C576

DDR_B_DQS#6
DDR_B_DQS6

10U_0603_6.3V6M

DDR_B_D48
DDR_B_D49

<8>

C587

DDR_B_D42
DDR_B_D43

DDR_CKE3_DIMMB

10U_0603_6.3V6M

DDR_B_DM5

DDR_CKE3_DIMMB

C582

DDR_B_D40
DDR_B_D41

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

10U_0603_6.3V6M

DDR_B_D34
DDR_B_D35

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

C383
2.2U_0603_6.3V4Z

DDR_B_DQS#4
DDR_B_DQS4

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

C385
0.1U_0402_10V6K

DDR_B_D32
DDR_B_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

FOX_AS0A626-U8RN-7F
ME@

DDR3 SO-DIMM A H=8mm Reverse type

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

DDRIII SO-DIMM B

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

15

of

41

FSB

FSA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

REF
MHz

266

100

33.3

14.318

DOT_96 USB
MHz
MHz

+3VS

0_0805_5%

48.0
2

133

100

33.3

14.318

96.0

+3VSM_CK505
R668 1

+3VS

96.0

1
C811
10U_0805_10V4Z

1
C812
0.1U_0402_16V4Z

1
C813
0.1U_0402_16V4Z

1
C814
0.1U_0402_16V4Z

1
C815
0.1U_0402_16V4Z

1
C816
0.1U_0402_16V4Z

R669 1

R670
2.2K_0402_5%
<19,23> ICH_SMBDATA

200

100

33.3

14.318

96.0

+1.05VS

R673 1

0_0805_5%
1

166

100

333

33.3

100

33.3

14.318
14.318

96.0
96.0

48.0
2

48.0

100

100

33.3

14.318

96.0

48.0

400

100

33.3

14.318

96.0

48.0

1
C818
10U_0805_10V4Z

55

VDD_SRC

VDD_REF

+1.05VS

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

R678 1

CPU_BSEL0

1 2.2K_0402_5%

R676 1

+VDD_CK505
2 1K_0402_5%

MCH_CLKSEL0

<8>

1
C821
0.1U_0402_16V4Z

<19> CLK_48M_ICH

@
R686
1K_0402_5%

R690 1

CPU_BSEL1

<19> CLK_14M_ICH
2 1K_0402_5%

MCH_CLKSEL1

R685 1

R687 1

33_0402_5%

<19> CK_PWRGD

H_STP_CPU#

<19> H_STP_PCI#

1
CPU_BSEL2

R697 1

2 1K_0402_5%

MCH_CLKSEL2

<8>

T5

PCI4_SEL

<17> CLK_PCI_ICH

R706 1

33_0402_5%

ITP_EN

CPU_1#

67

CLK_MCH_BCLK#
CLK_MCH_DREFCLK

23

VDD_IO

38

VDD_SRC_IO

29

MCH_SSCDREFCLK#

SRC_2

32

CLK_MCH_3GPLL

SRC_2#

33

CLK_MCH_3GPLL#

SRC_3

35

SRC_3#

36

FS_B/TEST_MODE

REF_0/FS_C/TEST_

REF_1

LCDCLK#/27M_SS

SRC_4

39

SRC_4#

40

+3VS

+3VS

1
2

+3VS

C825

NC

53

CPU_STOP#

SRC_6

57

SRC_6#

56

SRC_7

61

CLK_PCIE_WLAN1

SRC_7#

60

CLK_PCIE_WLAN1#

PCI_STOP#

SRC_8/CPU_ITP

64

SRC_8#/CPU_ITP#

63

27P_0402_50V8J

14.31818MHZ X5H01431AFG1H-X

PCI_1

SRC_9

44

CLK_PCIE_LAN

14

PCI_2

SRC_9#

45

CLK_PCIE_LAN#

15

PCI_3
SRC_10

50

CLK_PCIE_ICH

16

PCI_4/SEL_LCDCL
SRC_10#

51

CLK_PCIE_ICH#

17

PCIF_5/ITP_EN

18

VSS_PCI

1
C657
470P_0402_50V7K

C828

CLK_XTAL_OUT

VSS_REF

SRC_11

48

CLK_PCIE_SATA

SRC_11#

47

CLK_PCIE_SATA#

VSS_48

CLKREQ_3#

37

26

VSS_IO

CLKREQ_4#

41

69

VSS_CPU

CLKREQ_6#

58
WLAN_CLKREQ1#
CLKREQ_LAN#

30

VSS_PLL3

CLKREQ_7#

65

34

VSS_SRC

CLKREQ_9#

43

SLKREQ_10#

49

CLKREQ_11#

46

SATA_CLKREQ#

USB_1/CLKREQ_A#

21

MCH_CLKREQ#

Routing the trace at least 10mil

VSS_SRC

42

VSS_SRC

73

VSS

27P_0402_50V8J

<4>

CLK_CPU_BCLK#

CPU

<4>

CLK_MCH_BCLK

<7>

CLK_MCH_BCLK#

NB

<7>

CLK_MCH_DREFCLK

<8>

CLK_MCH_DREFCLK#

<8>

MCH_SSCDREFCLK

<8>

MCH_SSCDREFCLK#
CLK_MCH_3GPLL

<8>

<8>

CLK_MCH_3GPLL#

<8>

CLK_PCIE_WLAN1

<23>

CLK_PCIE_WLAN1#

CLK_PCIE_LAN

<23>

<24>

CLK_PCIE_LAN#

<24>

CLK_PCIE_ICH

22

59

CLK_CPU_BCLK

NB(96MHz)
NB_SSC(100MHz)
MCH_PEGPLL

WLAN

SRC PORT LIST

PORT

DEVICE

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

MCH_DREFCLK
MCH_3GPLL

PCIE_WLAN1
PCIE_LAN
PCIE_ICH
PCIE_SATA
+3VS

13

Y4

CLK_XTAL_IN

PCI2_TME
@
R712
10K_0402_5%

R711
10K_0402_5%
2

R710
10K_0402_5%
2

PCI4_SEL

R709
10K_0402_5%

@
R708
10K_0402_5%

ITP_EN

@
R707
10K_0402_5%

Change Y4 from SJ114P3M720 to SJ100002600.

PVT EMI
Close to CLK_PCI_LPC

<14,15>
<14,15>

CKPWRGD/PD#

11

+3VS

2 0_0402_5%

USB_0/FS_A

XTAL_OUT

33_0402_5%

CLK_MCH_BCLK

MCH_SSCDREFCLK

68

28

CLK_XTAL_OUT

R705 1

CPU_1

LCDCLK/27M

XTAL_IN

<27> CLK_PCI_LPC

CLK_CPU_BCLK#

@
R704
0_0402_5%

CLK_CPU_BCLK

VDD_SRC_IO

PCI2_TME

71
70

52

54

2 @ 33_0402_5%

CPU_0
CPU_0#

CLK_SMBDATA
CLK_SMBCLK

VDD_SRC_IO

CLK_XTAL_IN

R700 1

CLK_SMBCLK

62

H_STP_PCI#

<5>

2 0_0402_5%

CLK_SMBDATA

10

CLK_MCH_DREFCLK#

@
R692
1K_0402_5%
2 10K_0402_5%

SCL

25

+1.05VS

R699 1

SDA

SRC_0/DOT_96

CK_PWRGD

<19> H_STP_CPU#

R696 1

CLK_SMBCLK

SRC_0#/DOT_96#

20

@
R691
0_0402_5%

FSC

<19,23> ICH_SMBCLK

R674 1

VDD_PLL3_IO

FSB
FSC

33_0402_5%

2 0_0402_5%

Q1B
4

2N7002DW-T/R7_SOT363-6

VDD_CPU_IO

FSA

<8>

<5>

+3VS
C824
0.1U_0402_16V4Z

31

+1.05VS

R688 1

1
C823
0.1U_0402_16V4Z

24

@
R679
1K_0402_5%

FSB

1
C822
0.1U_0402_16V4Z

66

2 0_0402_5%
1

<5>

1
C820
0.1U_0402_16V4Z

+3VSM_CK505 U30

Reserved

R680 2

1
C819
0.1U_0402_16V4Z

SA000020K00 (Silego : SLG8SP556VTR )

SA000020H00 (ICS : ICS9LPRS387AKLFT)

@
R675
56_0402_5%
FSA

CLK_SMBDATA

Q1A

48.0

R671
2.2K_0402_5%

2N7002DW-T/R7_SOT363-6
6
1

48.0
+VDD_CK505

2 0_0402_5%

C817
0.1U_0402_16V4Z

FSC

<19>

CLK_PCIE_ICH#

<19>

CLK_PCIE_SATA

<18>

CLK_PCIE_SATA#

WLAN_CLKREQ1#
CLKREQ_LAN#

<18>

LAN
ICH-DMIPCIE

<19>
<8>

1 10K_0402_5%

WLAN_CLKREQ1#
MCH_CLKREQ#
CLKREQ_LAN#

R695 2
R698 2
R701 2

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%

DEVICE

PCIE_WLAN1
PCIE_LAN
PCIE_SATA
MCH_3GPLL
A

SLG8SP556VTR_QFN72_10X10

Issued Date

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

Pin28/29 : LCDCLK / LCDCLK#
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS
5

Compal Secret Data

Security Classification

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

REQ PORT LIST

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

<23>

MCH_CLKREQ#

R693 2

PORT
ICH-SATA

<24>

SATA_CLKREQ#

SATA_CLKREQ#

Title

Compal Electronics, Inc.

Clock Generator CK505

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

16

of

41

09/16 Add C858 For ESD

Place closely pin C14
+3VS
PLT_RST#
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

PCI_DEVSEL#

1
R796
1
R797
1
R798
1
R799
1
R800
1
R801
1
R802
1
R803
1
R805
1
R806
1
R807
1
R808

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

PCI_PIRQA#

PCI_STOP#
U9B

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

+3VS

PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#

PCI

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

F1
G4
B6
A7
F13
F12
E6
F6

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

C858
0.1U_0402_16V4Z
D

T107
PCI_REQ2#
T108
PCI_REQ3#
PCI_GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

D8
B4
D6
A5

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

D3
E3
R1
C6
E4
C2
J4
A4
F5
D7

PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

C14
D4
R2

PLT_RST#
CLK_PCI_ICH
PCI_PME#

Place closely pin D4

CLK_PCI_ICH

PCI_IRDY#

1
R804

R811
0_0402_5%

C869
18P_0402_50V8J

CLK_PCI_ICH <16>
PCI_PME# <27>
2
@ 10K_0402_5%

+3VALW

PCI_RST#

PCI_RST#

<27>

PCI_PIRQB#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

PCI_FRAME#

PCI_TRDY#

PCI_REQ1#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ2#
PCI_REQ3#

J5
E1
J6
C4

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

H4
K6
F2
G2

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

R813
100K_0402_5%
2

1
R788
1
R789
1
R790
1
R791
1
R792
1
R793
1
R794
1
R795

PLT_RST#
1

PLT_RST# <8,23,24>

R814
100K_0402_5%

PCI_GNT0#

SB_SPI_CS#1
1

<19> SB_SPI_CS#1

1
R812

2
@ 1K_0402_5%

@
R810
1K_0402_5%

SPI@
R809
1K_0402_5%
PCI_GNT3#

Boot BIOS Strap

PCI_GNT#0

A16 Swap Override Strap

PCI_GNT#3

Low= A16 swap override Enable

High= Default*

SPI_CS#1

Boot BIOS Loaction

SPI

PCI

LPC*

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9M(1/4)-PCI

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

17

of

41

+3VS
R933
GATEA20
+RTCVCC

Y5

+1.05VS

2
20K_0402_5%

+RTCBATT

R823
1

@
2

+RTCVCC

R180

2MM
1
C873

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

1
2
20K_0402_5%

1
C248

2
1U_0603_10V4Z

2
1U_0603_10V6K
+3VALW

0.1U_0402_16V4Z

9/14 Add R937 by Danson.

R937
10K_0402_5%
C

R828 1
2GLAN_COMP
24.9_0402_1%
1 R829
1 R831

<26> HDA_BITCLK_CODEC
<26> HDA_SYNC_CODEC

1 R832

<26> HDA_RST_CODEC#

2 33_0402_5%
2 33_0402_5%
2 33_0402_5%

HDA_RST_R#

1
R834

2
33_0402_5%

<32> HDD_LED#

1
R835
SATA_LED#

+3VS
D30
2 @
1
RB751V_SOD323
1
2
R92
0_0402_5%

10/01 Danson

HDD

Change D30 from SC1H751H010 to SCS00000Z00 .

Add R92 from SATA_LED# to HDD_LED#.

ODD

<28>
<28>
<28>
<28>
<32>
<32>
<32>
<32>

RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14
G13
D14

LAN_RXD0
LAN_RXD1
LAN_RXD2

D13
D12
E13

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

B10

GPIO56

B28
B27

GLAN_COMPI
GLAN_COMPO

AE7

AG5

HDA_SDOUT

AG7
AE8

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16
AH16
AF17
AG17

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

2
10K_0402_5%

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

AH13
AJ13
AG14
AF14

K5
K4
L6
K2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4/LFRAME#

K3

LPC_FRAME#

LDRQ0#
LDRQ1#/GPIO23

J3
J1

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

R821

<27>

LPC_FRAME#

H_DPRSTP#

H_DPSLP#

56_0402_5%
R824
@
2
1

56_0402_5%

<27>
+1.05VS

GATEA20
H_A20M#

A20GATE
A20M#

N7
AJ27

DPRSTP#
DPSLP#

AJ25 H_DPRSTP_R#
H_DPSLP#
AE23

FERR#

AJ26

H_FERR#_S

CPUPWRGD

AD22

H_PWRGOOD

IGNNE#

AF25

H_IGNNE#

INIT#
INTR
RCIN#

AE22
AG25
L3

H_INIT#
H_INTR
KB_RST#

GATEA20
H_A20M#
R825 2

<27>
<4>

1 0_0402_5%
R827 1

H_IGNNE#

H_DPRSTP#

AF23
AF24

H_NMI
H_SMI#

AH27

H_STPCLK#

THRMTRIP#

AG26

THRMTRIP_ICH#

TP12

AG27

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AH11
AJ11
AG12
AF12

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AH9
AJ9
AE10
AF10

SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS

AH18
AJ18
AJ7
AH7

H_NMI
H_SMI#

R833 1

<4>

<4>
C

+1.05VS

R833 need to place within 2" of ICH9M

<4>
<4>

H_STPCLK#

H_FERR#

<5>

H_INIT# <4>
H_INTR <4>
KB_RST# <27>

NMI
SMI#

R826
56_0402_5%

H_DPRSTP# <5,8,40>
H_DPSLP# <5>

2 56_0402_5%

H_PWRGOOD

STPCLK#
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDOUT_R

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

HDA_BIT_CLK
HDA_SYNC

AF4
AG4
AH3
AE5

T111
HDD_LED#

A25
F20
C22

HDA_BITCLK_ICH AF6
HDA_SYNC_R
AH4

<26> HDA_SDIN0

<26> HDA_SDOUT_CODEC

RTCX1
RTCX2

+1.5VS

C23
C24

ICH_INTVRMEN B22
LAN100_SLP
A22

1
2
R365 @
10K_0603_5%

100_0603_1%
C872

ICH_RTCX2

2
15P_0402_50V8J

CLRP1

LPC_AD[0..3]

U9A

OSC

NC

10K_0402_5%

R830 must be place within 2" of R833 w/o stub.

R830
56_0402_5%

<4>
2 54.9_0402_1%

1
R822

close to RAM door

R819
10M_0402_5%

LPC

+RTCVCC

+RTCVCC

CPU

1
C871

OSC

RTC

NC

LAN / GLAN

2
32.768KHZ_12.5PF_Q13MC14610002

IHDA

330K_0402_1%
2 ICH_INTVRMEN

R935
KB_RST#

1M_0402_5%
2 SM_INTRUDER#

R820
1

1
D

ICH_RTCX1

2
15P_0402_50V8J
1

R936
1

1
C870

SATA

330K_0402_1%
2 LAN100_SLP

R934
1

2
10K_0402_5%

Change Y2 from SJ100001U00 to SJ100003300.

H_THERMTRIP#

H_THERMTRIP#

<4,8>

Place closely pin AG26

THRMTRIP_ICH#

R836 1
R837 1

2 @ 1K_0402_5%
2 @ 1K_0402_5%

C641
2

CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS

100P_0402_50V8J

CLK_PCIE_SATA# <16>
CLK_PCIE_SATA <16>

R838 1

2 24.9_0402_1%

10mils width less than 500mils

ICH9-M ES_FCBGA676

Need check

SATA PORT LIST

+3VS
2

XOR Chain Entrance Strap

HDA_SDOUT_R

ICH_TP3

R839
1K_0402_5%
@

HDA_SDOUT

PORT

Description

RSVD

Enter XOR Chain

Normal Operation

Set PCIE port config bit 1

0
1
4
5

DEVICE
HDD
ODD

Flash Descriptor Security Override Strap

GPIO33

Low= Descriptor Security override

High= Default* (Internal pull-up)

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9M(2/4)-LAN,ATA,LPC,RTC

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

18

of

41

+3VS

09/10 Add for Project ID

+3VS

XDP_DBRESET#

R4
G19

XDP_DBRESET#

R866 1

2 10K_0402_5%

ICH_RI#

R867 1

2 1K_0402_5%

ICH_PCIE_WAKE#

R868 1

2 8.2K_0402_5%

ICH_LOW_BAT#

R870 1

2 10K_0402_5%

LID_OUT#

R872 1

2 10K_0402_5%

WOL_EN

R915 1

2 10K_0402_5%

GPIO14

<4> XDP_DBRESET#

CL_RST#

2 10K_0402_5%

@
R853
10K_0402_5%

@
R859
10K_0402_5%

<16> H_STP_PCI#
<16> H_STP_CPU#

R862

PM_BMBUSY#

M6

1
2 LID_OUT#
R855
0_0402_5%
H_STP_PCI#
R_STP_CPU#

A17

<8> PM_BMBUSY#
<27> EC_LID_OUT#

LINKALERT#

2 @ 10K_0402_5%

R864 1

2 10K_0402_5%

R861 1

R856 1

2 0_0402_5%

PCI_CLKRUN#
<23,24> ICH_PCIE_WAKE#
<27>
SERIRQ
<27> EC_THERM#
VGATE

R869 1

2 10K_0402_5%

GPIO6

R876 1

2 10K_0402_5%

GPIO7

@ R927
2
1
0_0402_5%

<27,32> ODD_DA#

XDP_DBRESET#
R916 1

<27>
<27>

R878 1

2 10K_0402_5%

GPIO13

R879 1

2 @ 10K_0402_5%

GPIO17

R880 1

2 @ 10K_0402_5%

GPIO18

R882 1

2 10K_0402_5%

GPIO20

R883 1

2 10K_0402_5%

GPIO22

EC_SMI#
EC_SCI#

C833
0.1U_0402_16V4Z

Place closely pin D21

<32>

+3VS

R889 1

2 @ 100K_0402_5%

GPIO57

R890 1

2 @ 100K_0402_5%

DPRSLPVR

R891 1

2 @ 1K_0402_5%

ICH_RSVD

ODD_EN

SST_CTL

OCP#
GPIO6
GPIO7
EC_SMI#
EC_SCI#
GPIO13
GPIO17
GPIO18
GPIO20
GPIO22

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD
T99
T100
T101

<26> SB_SPKR
<8> MCH_ICH_SYNC#

VRMPWRGD
SB_SPKR

D21

SATA_CLKREQ#
GPIO38
GPIO39
GPIO48
GPIO49
GPIO57

<16> SATA_CLKREQ#

2 @ 10K_0402_5%

VRMPWRGD

T98

09/16 Add C833 For ESD

R888 1

E20
M5
AJ23

T96

+3VS

C860
1000P_0402_50V7K

L4

ICH_PCIE_WAKE#
SERIRQ
EC_THERM#

2 0_0402_5%

Place closely pin G19

A14
E19

A20
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
M7
AJ24
B21
AH20
AJ20
AJ21

CLK14
CLK48

clocks

RI#
SUS_STAT#/LPCPD#
SYS_RESET#

SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#

PMSYNC#/GPIO0
SMBALERT#/GPIO11
STP_PCI#
STP_CPU#
CLKRUN#
WAKE#
SERIRQ
THRM#
VRMPWRGD
TP11
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

S4_STATE#/GPIO26
PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

H1
AF3

CLK_14M_ICH
CLK_48M_ICH

P1

ICH_SUSCLK

C16
E16
G17

SLP_S3#
SLP_S4#
SLP_S5#

C10

S4_STATE#

CLK_14M_ICH
CLK_48M_ICH

<16>
<16>

SLP_S3#
SLP_S4#
SLP_S5#

G20

ICH_POK

M2

R865 1

B13

ICH_LOW_BAT#

R3

PBTN_OUT#

PBTN_OUT#

DPRSLPVR

D22

EC_RSMRST#R

R5

CK_PWRGD_R

R6

M_PWROK

B16

EC_RSMRST#R

WLAN
RP3

C891
C892

0.1U_0402_10V7K
0.1U_0402_10V7K

<23> PCIE_RXN3
<23> PCIE_RXP3
<23> PCIE_TXN3
<23> PCIE_TXP3

C884
C885

0.1U_0402_10V7K
0.1U_0402_10V7K

1
1

R899 1

2 @ 0_0402_5%

VRMPWRGD
C29
C28
D27
D26

@
Q9
RHU002N06_SOT323
ICH_SPI_CLK_1
ICH_SPI_CS0#

R919 1 SPI@
R920 2 SPI@

2 33_0402_5%
1 0_0402_5%

ICH_SPI_CLK
ICH_SPI_CS0#_R
SB_SPI_CS#1

D23
D24
F23

R422 1 SPI@

2 0_0402_5%

ICH_SPI_MOSI
ICH_SPI_MISO

D25
E23

<17> SB_SPI_CS#1
ICH_SPI_MOSI_1

<29> USB_OC#0
<29> USB_OC#1_7

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

SPI Flash (16Mb*1)

+3VS

20mils
SPI@
C1171
0.1U_0402_16V4Z

20mils
U33 SPI@
8

3
7
ICH_SPI_CS0#

ICH_SPI_CLK_1

ICH_SPI_MOSI_1

VCC

VSS

J29
J28
K27
K26

E29
E28
F27
F26

2
G
3

<40> CLK_ENABLE#

N29
N28
P27
P26

G29
G28
H27
H26
@
R898
330_0402_5%

10K_1206_8P4R_5%

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

+3VS

USB_OC#8
USB_OC#3
USB_OC#10
USB_OC#11

2 0_0402_5%

CK_PWRGD

R874 1
T97

2 0_0402_5%

M_PWROK <8>
VGATE
<8,40>

F24
B19

CL_CLK0

F22
C19

CL_DATA0

2 10K_0402_5%
CK_PWRGD

R875 1
1

<8>
2

C25
A19

CL_VREF0_ICH
CL_VREF1_ICH

F21
D18

CL_RST#

C881
0.1U_0402_16V4Z

<8>

D31
2 @

RB751V_SOD323
1 ACIN

GPIO14
+3VALW

2 3.24K_0402_1%

+3VS

R877
453_0402_1%
C

R881 1
1
CL_RST# <8>
@

A16
C18
C11
C20

<16>

2
1
2
R886
R887
@ 10K_0402_5%

ACIN

C882
@
0.1U_0402_16V4Z

<27,36>

2 3.24K_0402_1%

+3VALW

R885
453_0402_1%

1
@ 0_0402_5%

Change Q8 from SB000009S80 to SB000006780

FOR SB 16M SPI ROM

R900 1

2 22.6_0402_1% USBRBIAS

2 R893 @1
0_0402_5%

SPOK

N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
AG2
AG1

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
SPI_MOSI
SPI_MISO

2 R892 @1
0_0402_5%

EC_RSMRST#R

SPI

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47

USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

V27
V26
U29
U28

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<8>
<8>
<8>
<8>

Y27
Y26
W29
W28

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<8>
<8>
<8>
<8>

AB27
AB26
AA29
AA28

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

<8>
<8>
<8>
<8>

AD27
AD26
AC29
AC28

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

<8>
<8>
<8>
<8>

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

AF29
AF28
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2

DMI_IRCOMP

R897 1

USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

Q8

@
D32B
R895
2.2K_0402_5%

EC_RSMRST#

<27>

MMBT3906_SOT23-3
1
2
+3VALW
R894
4.7K_0402_5%

D32A
BAV99DW-7_SOT363

R896
1

2
B

4.7K_0402_5%

PCIE PORT LIST

PORT

CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

BAV99DW-7_SOT363

Within 500 mils

2 24.9_0402_1%

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

<29>
<29>
<29>
<29>
<22>
<22>

USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

<30>
<30>Card Reader
<23>
<23> WLAN
<30>
<30> BT
<29>
<29> LEFT USB

+1.5VS

RIGHT USB
LEFT USB
CMOS

1
2
3
4
5
6

USB PORT LIST

DEVICE

PORT

LAN

0
1
2
3
4
5
6
7
8
9
10
11

WLAN

DEVICE
RIGHT SIDE
LEFT SIDE
CMOS
CARD READER
WIRELESS
BT
LEFT SIDE

USBRBIAS
USBRBIAS#

ICH9-M ES_FCBGA676
Within 500 mils
Change U26 P/N from SA00000XT00 to SA000041N00 0915

HOLD
S
C
D

ICH_SPI_MISO_1

SPI@
ICH_SPI_MISO
2
1
R917
0_0402_5%

Compal Secret Data

Security Classification

Issued Date

MX25L1606EM2I-12G_SO8

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Change U33 footprint from WIESO_G6179-100000_8P to MX25L1606EM2I-12G_SO8 0920

Change Value from MX25L8005M2C-15G SOP 8P to MX25L1606EM2I-12G_SO8 0920

Title

Compal Electronics, Inc.

ICH9M(3/4)-USB,GPIO,PCIE

Size
C
Date:

C880
1000P_0402_50V7K

PCIE_IRX_PTX_N1
PCIE_IRX_PTX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1

4
3
2
1

R871 1

R873 1

PCIE_IRX_PTX_N1
PCIE_IRX_PTX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

L29
L28
M27
M26

USB_OC#5
USB_OC#7
USB_OC#9
USB_OC#0

<27>

<24>
<24>
<24>
<24>

10K_1206_8P4R_5%

5
6
7
8

2 R863
10K_0402_5%

D20

U9D

Direct Media Interface

LAN

RP2

<8,27>
1

<8,40>

RSMRST circuit

PCI - Express

USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4

4
3
2
1

ICH_POK
DPRSLPVR

2 499_0402_1%

M_PWROK

2 @ 100_0402_5%

Change D31 from SC1H751H010 to SCS00000Z00 .

10K_1206_8P4R_5%

5
6
7
8

M_PWROK

R860 1

ICH9-M ES_FCBGA676

Change Lan from Port6 to Port 1 for power consumption.

4
3
2
1

10/15 Change C880 from 100P to 1000P for noise.

@
R854
10K_0402_5%

<27>
<27>
<27>

<35,37>

5
6
7
8

C878
10P_0402_50V8J
@

+3VALW

T95

10/01

RP1

PROJECT_ID1
PROJECT_ID2

WOL_EN

10/12 Add C833 For Noise

+3VALW

C879
10P_0402_50V8J
2 @

F19

ICH_RI#

+3VS

10K_0402_5% 10@
2
1 R1052

PROJECT_ID2

1
+3VS

AH23
AF19
AE21
AD20

GPIO48

SMB

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

R857
10_0402_5%
@

R850
22_0402_5%
@

2 10K_0402_5%

+3VALW

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

R852 1

LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

G16
A13
E17
C17
B18

SATA
GPIO

GPIO39

<16,23> ICH_SMBCLK
<16,23> ICH_SMBDATA

SYS / GPIO

2 @ 10K_0402_5%

R847
10K_0402_5%

R849
10K_0402_5%

10K_0402_5% 20@
2
1 R1159
R846
8.2K_0402_5%

U9C

Power MGT

R858 1

PM_BMBUSY#

R845
2.2K_0402_5%

MISC
GPIO
Controller Link

2 @ 8.2K_0402_5%

R844
2.2K_0402_5%

R851 1

10K_0402_5% 10@
2
1 R1150

PROJECT_ID1

OCP#

2 10K_0402_5%

R848 1

+3VALW

CLK_14M_ICH

EC_THERM#

8.2K_0402_5%

+3VS

+3VALW

R843 1

CLK_48M_ICH

GPIO38

2 @ 10K_0402_5%

R842 1

Place closely pin B2 Place closely pin AC1

10K_0402_5% 20@
2
1 R943

1 2
B

PCI_CLKRUN#

SERIRQ

2 8.2K_0402_5%

2 10K_0402_5%

R841 1

R840 1

Document Number

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

1

19

of

41

+1.05VS
U9F

D33
RB751V_SOD323
1

R901
100_0402_5%

ICH_V5REF_RUN
1

20 mils
C893
1U_0603_10V4Z

Change D33 and D34 from

SC1H751H010 to SCS00000Z00 .

+5VALW +3VALW

D34
RB751V_SOD323

40 mils

+1.5VS_PCIE_ICH

10U_0805_10V4Z
1
+

C908
220U_6.3V_M

OSCON

C910

C911

C912

10U_0805_10V4Z

2
2.2U_0603_6.3V4Z

+1.5VS

AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15

C917
1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1342mA
+1.5VS
C924
1U_0603_10V4Z

AC9

1
AC18
AC19
2

AC21
G10
G9
AC12
AC13
AC14

11mA

AJ5

+1.5VS
C800
0.1U_0402_16V4Z

C801
0.1U_0402_16V4Z

11mA

2
C972
2
1

+3VS

VCC_LAN1_05_INT_ICH

0.1U_0402_16V4Z

19mA

Follow KHLBX and CRB.

1

close to AC7

CHB1608U301_0603
1
2
R910
1
+1.5VS

C804

(10UF*1, 2.2UF*1)
+1.5VS

4.7U_0805_10V4Z

R911
1
2
CHB1608U301_0603

23mA

1
2.2U_0603_6.3V4Z

2
10U_0805_10V4Z

80mA

D28
D29
E26
E27
A26

+3VS
1

A12
B12

+VCC_GLANPLL_ICH A27

C805
2

A10
A11

1mA

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

+1.05VS

+3VS

0.1U_0402_16V4Z
1

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
VCCLAN1_05[1]
VCCLAN1_05[2]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCCCL1_05
VCCCL1_5

VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN3_3
ICH9-M ES_FCBGA676

+3VS

308mA
1

1
C909
0.1U_0402_16V4Z

+3VS

1
C913
0.1U_0402_16V4Z

C914
0.1U_0402_16V4Z

+1.5VS

R906 @
0_0402_5%

R905
AJ4
AJ3

11mA
11mA

+VCC_HDA_ICH
+VCCSUS_HDA_ICH

0.1U_0402_16V4Z 1
C916
T102
T103
2

AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2

0_0402_5%
0.1U_0402_16V4Z
C915

AD8 VCCSUS1_5_ICH_1
F18

VCCSUS1_5_ICH_2

A18
D16
D17
E22

2
1
R908 @
0_0402_5%
0.1U_0402_16V4Z

C971

Follow KHLBX and CRB.

+3VALW

0.1U_0402_16V4Z
1

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

+3VALW

C920
4.7U_0603_6.3V6M

C923
0.1U_0402_16V4Z

+3VALW

C799
4.7U_0603_6.3V6K

G22 VCCCL1_05_ICH
G23 +VCCCL1_5_INT_ICH
A24
B24

2
R909
0_0402_5%

1
1

19mA

VCCCL3_3[1]
VCCCL3_3[2]

C906
0.1U_0402_16V4Z

C901
0.1U_0402_16V4Z

C907

VCC1_5_A[20]

(SATA)

(DMI)

+3VS

+3VS

C922

VCC1_5_A[18]
VCC1_5_A[19]

10U_0805_10V4Z

2mA

212mA
VCCSUS3_3[05]

48mA

VCC1_5_A[17]

C806

+3VS

C803
@ 1U_0603_10V4Z

C970

AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

0.1U_0402_16V4Z

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH9-M ES_FCBGA676

Follow KHLBX and CRB.

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCCSUS1_5[2]

GLAN POWER

C802
0.1U_0402_16V4Z

AA7
AB6
AB7
AC6
AC7

VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]

VCCSUS1_5[1]

10U_0805_6.3V6M

C900

VCCSUS1_05[1]
VCCSUS1_05[2]

USB CORE

+1.5VS
1

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]

ATX

AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10

C921

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

B9
F9
G3
G6
J2
J7
K7

+1.05VS

VCCSATAPLL

VCCPSUS

AD19
AF20
AG24
AC20

VCCSUSHDA

ARX

C919

10U_0805_10V4Z

C918

CHB1608U301_0603

+1.5VS_SATAPLL_ICH AJ19

1U_0603_10V4Z

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCCHDA

47mA

R907
1

+1.5VS

AG29
AJ6
AC10

23mA

VCCPUSB

+1.5VS

646mA

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

C897

C904

R904
0_0805_5%
1
2

AB23
AC23

R902
1
2
+1.5VS
CHB1608U301_0603

0.01U_0402_16V7K
C896

C903

V_CPU_IO[1]
V_CPU_IO[2]

0.1U_0402_16V4Z

1U_0603_10V4Z

W23
Y23

0.1U_0402_16V4Z

C902

C905

VCC_DMI[1]
VCC_DMI[2]

C899

0.1U_0402_16V4Z

ICH_V5REF_SUS

20 mils
1

VCCDMIPLL

R29 +1.5VS_DMIPLL_ICH

1
C895

4.7U_0603_6.3V6M

R903
100_0402_5%

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]

VCCA3GP

10/01 Danson

V5REF_SUS

+3VS

AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25

ICH_V5REF_SUS

2mA

1634mA

0.1U_0402_16V4Z

V5REF

CORE

2mA

C898
0.1U_0402_16V4Z

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C1169

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

0.1U_0402_16V4Z
C1168

+5VS

U9E

VCCRTC

0.1U_0402_16V4Z

C894
0.1U_0402_16V4Z

A6

VCCP_CORE

A23
ICH_V5REF_RUN

PCI

20 mils
+RTCVCC

Title

Compal Electronics, Inc.

ICH9M(4/4)-POWER&GND

Size
B
Date:

Document Number

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

1

20

of

41

+5VS

+5VS

+5VS

+5VS

+5VS

Pre MP ADD for ESD solution

+5VS

+5VS

Near D26
2
@
D2
BAT54S-7-F_SOT23-3

<10> DAC_GRN

<10> DAC_BLU

R90
150_0402_1%

R131
150_0402_1%

R153
150_0402_1%

CLOSE TO CONN

1
C158

C146

Near D21
1

2
@
D27
BAT54S-7-F_SOT23-3

C137
10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

C624
0.1U_0402_16V4Z

C627
0.1U_0402_16V4Z

+5VS

RED
GREEN

C658
0.1U_0402_16V4Z

1.1A_6V_SMD1812P110TF

R91 @

W=40mils

C145
2

C136
10P_0402_50V8J

10P_0402_50V8J10P_0402_50V8J

JCRT1

T10

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_DDC_DAT_CONN
GREEN
JVGA_HS
BLUE
JVGA_VS
CRT_DDC_CLK_CONN

+CRT_VCC
R575 2

CRT_HSYNC_1

L32
CRT_HSYNC_2
2
1
2
FCM1608CF-121T03 0603
39_0402_1%

1
R576

U26
TC7SET125FUF_SC70

R159
2.2K_0402_5%

CRT_VSYNC_1

U25
TC7SET125FUF_SC70

JVGA_VS

R158
2.2K_0402_5%

@
C178
2N7002DW-T/R7_SOT363-6 100P_0402_50V8J

Q13A

@ C625
10P_0402_50V8J

CRT_DDC_DAT_CONN

Q13B
2N7002DW-T/R7_SOT363-6

<10> CRT_DDC_CLK

R157
2.2K_0402_5%
2

2
L31
CRT_VSYNC_2
2
1
2
FCM1608CF-121T03 0603
39_0402_1%

1
R577

+CRT_VCC

<10> CRT_DDC_DATA

Follow KHLBx

1
OE#

P
G
3

R162
2.2K_0402_5%

R580 2

+3VS

@
C626
10P_0402_50V8J

10K_0402_5%

<10> CRT_VSYNC

+3VS

1
C620
0.1U_0402_16V4Z

JVGA_HS

+CRT_VCC

16
17

1
Y

G
G

Follow KHLBx

TYCO_1775763-1
ME@

C628
100P_0402_50V8J

<10> CRT_HSYNC

10K_0402_5%

OE#

C619
0.1U_0402_16V4Z

C629
0.1U_0402_16V4Z

0_0603_5%

RED

+CRTVCC_CONN
1

RB491D_SC59-3

F1
1

BLUE
1

CRT Connector

+CRT_VCC
D21

C157
2

@
D26
BAT54S-7-F_SOT23-3

+5VS

Near D3

JVGA_VS
1

FCM1608CF-121T03 0603
1
2
L11
FCM1608CF-121T03 0603
1
2
L10
FCM1608CF-121T03 0603
1
2
L9
1
1

<10> DAC_RED

JVGA_HS

BAT54S-7-F_SOT23-3
@
D3

@
D1
BAT54S-7-F_SOT23-3

RED

2
1

GREEN

BLUE

CRT_DDC_CLK_CONN
1
@
C177
68P_0402_50V8K
2

Change Q13 from SB00000EO10 to SB00000AR00.

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

CRT Connector

Size
B
Date:

Document Number

Rev
1.0

LA7012P
Friday, December 24, 2010

Sheet
E

21

of

41

INVPWM

C567

2
2

JLVDS1

+LCDVDD_CONN

(60 MIL)
1

2
@ R392
2.2K_0402_5%

R395@
2.2K_0402_5%
<27> DAC_BRIG
EDID_CLK
EDID_DATA

<10> EDID_CLK
<10> EDID_DATA

2
4
6
8
10
12
14
16
INVPWM
18
DISPOFF# 20
22
24
26
28
30
32

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

GNDGND

31

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

USB20_N2
USB20_P2
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
LVDS_ACLK#
LVDS_ACLK

CMOS

+3VS

LVDS_A0# <10>
LVDS_A0 <10>

+CMOS_PW

R596 CMOS@
0_0603_5%
1
2

(20 MIL)
USB20_N2 <19>
USB20_P2 <19>

Q24 CMOS@
AP2301GN-HF_SOT23-3
CAM_3 3

+5VS
R270 CMOS@
100K_0402_5%

LVDS_A1# <10>
LVDS_A1 <10>

CAM_1

R280 CMOS@
0_0603_5%
2

C275
0.1U_0402_16V4Z
2 CMOS@

C337
10U_0805_10V4Z
2 CMOS@

CMOS1

LVDS_A2# <10>
LVDS_A2 <10>

R435
150K_0402_5%

CMOS@
LVDS_ACLK# <10>
LVDS_ACLK <10>
2

<27> CMOS_OFF#

IN

ACES_87142-3041
ME@

C326
0.01U_0402_16V7K
CMOS@

Q21
DTC124EKAT146_SC59-3
CMOS@

+3VS
R261
0_0402_5%
1
2

R539
@
0_0603_5%
1
2

+5VS

+CMOS_PW

EMI demand
680P_0402_50V7K
@ C14

CMOS Camera

+3VS

+3VS

B+

2 0_0805_5%

1 @
C296

(40MIL)

4.7U_0805_25V6-K
1 R549
1
C566

680P_0402_50V7K

OUT

1 @
C13

+LEDVDD

DISPOFF#

GND

470P_0402_50V7K

C15
1 @

470P_0402_50V7K

470P_0402_50V7K

DAC_BRIG

R250
@

BKOFF#

BKOFF#

4.7K_0402_5%
@
2

DISPOFF#

LCD POWER CIRCUIT

RB751V_SOD323

<27>

D12

R751
10K_0402_5%

10/01
+LCDVDD

+5VALW

Change D12 from SC1H751H010 to SCS00000Z00 .

<10> GMCH_ENVDD

LCD_ENVDD 2

IN

+3VS

DTC124EK

U22

P
Y

3
1

AP2301GN-HF_SOT23-3

W=60mils
+LCDVDD

+LCDVDD_CONN

L2
1

Q5
DTC124EKAT146_SC59-3

FBMA-L11-201209-221LMA30T_0805
C33

R37
@
100K_0402_5%

INVPWM

4.7U_0805_10V4Z

C25
0.1U_0402_16V4Z

TC7SZ14FU_SSOP5

C539
4.7U_0603_6.3V6K

<10> GMCH_PWM

NC
A
G

1
2

Q4

C34
0.1U_0402_16V4Z

OUT

S
R35
0_0402_5%
2
1

R38
1
2
220K_0402_5%

2
G
1

R430 @
0_0402_5%
1
2

D
2N7002H_SOT23-3
Q3

W=60mils

R31
100K_0402_5%

R432
0_0402_5%
1
2

GND

<27> INVT_PWM

+3VS
R13
150_0603_1%

INVPWM

R431 @
2
1

+3VS

Issued Date

For GMCH DPST

5

Compal Secret Data

Security Classification

10K_0402_5%
2N7002H_SOT23-3
Q82 @

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Compal Electronics, Inc.

LVDS/CAMERA

Size
B
Date:

Document Number

Rev
1.0

LA7012P
Friday, December 24, 2010

Sheet
1

22

of

41

Mini-Express Card for WLAN(Half)

+3VS_WLAN
+3VS

+3VS_WLAN
J6

+1.5VS

@
2Watt
2

2
@ J4
@J4
JUMP_43X79

JUMP_43X79

C422
2

0.01U_0402_16V7K

C423
0.1U_0402_16V4Z

C424
@
4.7U_0603_6.3V6M

+3VS_WLAN

1
R334 1
R333

2 ICH_PCIE_WAKE#_R
2 0_0402_5%
0_0402_5%

<16> WLAN_CLKREQ1#
<16> CLK_PCIE_WLAN1#
<16> CLK_PCIE_WLAN1

<19> PCIE_RXN3
<19> PCIE_RXP3
<19> PCIE_TXN3
<19> PCIE_TXP3

+3VS_WLAN

1
1

2 R274
2 R273

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

53

GND

54

GND

+1.5VS_CONN
+1.5VS_CONN

C425
0.01U_0402_16V7K
R377 1

0_0402_5%

R376 1
R375 1

2 @ 0_0402_5%
0_0402_5%
2

R374 1
R373 1

2 @ 0_0402_5%
2 @ 0_0402_5%

WL_OFF# <27>
PLT_RST# <8,17,24>

C426
0.1U_0402_16V4Z

C433
@
4.7U_0603_6.3V6M

+3VALW
+3VS_WLAN
ICH_SMBCLK <16,19>
ICH_SMBDATA <16,19>

USB20_N5 <19>
USB20_P5 <19>
R372 2
R371 2

1 @ 300_0402_5%
0_0402_5%
1

WLAN_LED# <32>

R626
100K_0402_5%
1

<27> EC_TX_P80_DATA
<27> EC_RX_P80_CLK

100_0402_1%
100_0402_1%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

ICH_PCIE_WAKE#
BT_ACTIVE

JWLAN1
<19,24> ICH_PCIE_WAKE#
<30> BT_ACTIVE

+5VS

TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
R625
100K_0402_5%

For EC to detect
debug card insert.

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Mini-Card/DEBUG-PORT

Size

Document Number

Rev
1.0

LA7012P
Date:

Friday, December 24, 2010

Sheet
E

23

of

41

+1.7_VDDCT

+3V_LAN

+3VALW

+1.7_LX

Power On strapping

Close together

Pin
Layout Notice : Place as close
chip as possible.

GIGA@

Atheros request can't disable LAN power

LED0

Chip Default

Note: Place Close to LAN chip

L39 DCR< 0.15 ohm
Rate current > 1A

LED1

L:Over Clock Disable

H:SWR Switch mode regulator Select

--

AR8151 Pin23=LED2.

AR8152, Pin23 is CLKREQ

Close to
Pin40

Atheros request reserve

Place Close to LAN chip

+3V_LAN

PLT_RST#

R252 1

2 4.7K_0402_5%

PCIE_WAKE#_R

R253 1

2 4.7K_0402_5%

CLKREQ_LAN#

R1160

U29

R1161

R1162

R1163

8152@

0_0402_5%

0_0402_5%

NONSURGE@

0_0402_5%

NONSURGE@

R526

MDI0-

R527 1

MDI1+

R528 1

MDI1-

R529 1

MDI2+

R530 1
GIGA@
R531 1
GIGA@
R532 1
GIGA@
R533 1
GIGA@

MDI2-

0_0402_5%

NONSURGE@

MDI0+

NONSURGE@
MDI3+
MDI3-

S IC AR8152-AL1E QFN 40P E-LAN CTRL

32
33

REFCLK_N
REFCLK_P

R519 1
R521 1

<19,23> ICH_PCIE_WAKE#
<27> LAN_WAKE#

2 0_0402_5% PCIE_WAKE#_R
2 0_0402_5%

8152@
C559 1
2 0.1U_0402_16V4Z

LAN_XTALO
LAN_XTALI

PERST#

W AKE#

25
26

SMCLK
SMDATA

RBIAS

10

28
27

TEST_RST
TESTMODE

VDD33

7
8

CLKREQ_LAN#_R

C597

0.1U_0402_16V4Z

1U_0402_6.3V4Z
C600

C601

C568

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

C565

0.1U_0402_16V4Z

C564

0.1U_0402_16V4Z

GIGA@

+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL

4
13
19
31
34
6
41

+1.7_VDDCT

2
0.1U_0402_16V4Z

DVDDL
DVDDL_REG

24
37

1
C561
+1.1_DVDDL
+1.1_DVDDL

AVDDH
AVDDH
AVDDH_REG

16
22
9

+2.7_AVDDH_R
+2.7_AVDDH
+2.7_AVDDH

0_0402_5% 1

+1.7_LX

GND
AR8151-AL1A_QFN40_5X5
GIGA@
LAN_XTALI

LAN_XTALO

<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>

+1.7_VDDCT

Near
Pin6

25MHZ_20PF_7A25000012
1
1

C579

Near
Pin34

Near
Pin9

2 C577 1000P_0402_50V7K

2 C593 0.1U_0402_16V4Z

1@

2 C580 1000P_0402_50V7K

2 C591 0.1U_0402_16V4Z
GIGA@
2 C599 1000P_0402_50V7K

1@

2 C583 0.1U_0402_16V4Z
GIGA@

D24
MDI0+
MDI0-

1
2
3
4
5

1
2
3
4
5

10
9
8
7
6

TCLAMP3304N.TCT_SLP2626P10-10

2 R520

+2.7_AVDDH

Near
Pin16

Near
Pin22

Near
Pin37

10
9
8
7
6

MDI1MDI1+

SURGE@
B

Will used
Semtech
3304N

Customer Lan
surge
Suggesttion

GIGA@

Part Number = SC300001J00

Part Number = SC300001J00

D20
MDI2+
MDI2-

2
27P_0402_50V8J

Near
Pin31

C578

Near
Pin19

27P_0402_50V8J

Near
Pin13

2 C592 0.1U_0402_16V4Z

1@

9/27 Add it for avoid to be struck by lightning

Y6

2 C594 1000P_0402_50V7K

+3V_LAN

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG

MDI0-_R
MDI0+_R
MDI1-_R
MDI1+_R
MDI2MDI2+
MDI3MDI3+

C554 & C555 Close pin1 < 200mil

C557 & C558 Close pin < 400mil

+3V_LAN

CLKREQ#

MDI0-_R
MDI0+_R
MDI1-_R
MDI1+_R
MDI2MDI2+
MDI3MDI3+

3.9_0402_1%
3.9_0402_1%
3.9_0402_1%
3.9_0402_1%

1
2
R522 2.37K_0402_1%

+1.7_LX

XTLO
XTLI

2
2
2
2

Close Pin 10

LAN_RBIAS

C572

CLKREQ_LAN# 1 GIGA@ 2
R525
0_0402_5%

R1160
R1161
R1162
R1163

40

LX
VDDCT

<16> CLKREQ_LAN#

Pre MP Add it for EMI

1
1
1
1

1U_0402_6.3V4Z

PLT_RST#

<8,17,23> PLT_RST#

MDI0- SURGE@
MDI0+ SURGE@
MDI1- SURGE@
MDI1+ SURGE@

C563

1 0_0402_5% CLK_PCIE_LAN#_C
1 0_0402_5% CLK_PCIE_LAN_C

12
11
15
14
18
17
21
20

0.1U_0402_16V4Z
C562

2 R517
2 R518

<16> CLK_PCIE_LAN#
<16> CLK_PCIE_LAN

TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3

10U_0805_10V4Z

RX_P

C557

35

10U_0805_10V4Z
@ C558

<19> PCIE_ITX_C_PRX_P1

8151-AL1A

1@

Note 2 : C594, C577, C580, C599, reserved for EMI.

1U_0402_6.3V4Z

RX_N

1 8152@ 2
R516
0_0402_5%

2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%

Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+

resister and cap

ACTIVITY <25>
LAN_LINK# <25> CLKREQ_LAN#

C560

36

ACTIVITY
LAN_LINK#

0.1U_0402_16V4Z

TX_P

<19> PCIE_ITX_C_PRX_N1

38
39
23

C554

30

LED_0
LED_1
LED_2

0.1U_0402_16V4Z
C555

Atheros

C573

PCIE_PRX_LANTX_P1

1
2
R515 5.1K_0402_5%

TX_N

GIGA@

2 0.1U_0402_16V7K

29

0.1U_0402_16V4Z

C552 1

PCIE_PRX_LANTX_N1

C574

<19> PCIE_IRX_PTX_P1

2 0.1U_0402_16V7K

LED0,1,2 intel Pull UP

0.1U_0402_16V4Z

C553 1

1U_0402_6.3V4Z

<19> PCIE_IRX_PTX_N1

0.1U_0402_16V4Z
C571

Place Close to Chip

no overclocking
PD 5.1K

U29

GND

2 4.7K_0402_5%

11

Near
Pin24

1
2
3
4
5

1
2
3
4
5

10
9
8
7
6

GND

R251 1

TCLAMP3304N.TCT_SLP2626P10-10

11

10U_0805_10V4Z

JUMP_43X79

0.1U_0402_16V4Z
C547

C549

Description
H:Over Clock Enable

L39
1
2 +1.7_LX
4.7UH_SIA4012-4R7M_20%

+1.7_VDDCT
1000P_0402_50V7K
C548

J8

10
9
8
7
6

MDI3MDI3+

Configure
Pin4
AR8152

VDDCT_REG

AR8151

CLKREQn

R525

C559

*
*
5

Configure
Pin23
CLKREQn

R516

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/10

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LED[2]
4

Title

LAN-AR8151/8152
Size Document Number
Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

24

of

41

9/27 Add it for avoid to be struck by lightning

BS201N-LV
1

C602
2
@
BS201N-LV C603
1
2
@
BS201N-LV C604
1
2
@
BS201N-LV C609
1
2
@

MCT3
MCT2

Customer Lan
surge
Suggesttion
Will used BS-201N-LV

+1.7_VDDCT

1 0.1U_0402_16V4Z
GIGA@
1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z

MDI3+
MDI3-

<24>
<24>

MDI1+_R
MDI1-_R

<24>
<24>

MDI2+
MDI2-

<24>
<24>

MDI0+_R
MDI0-_R

MDI3+
MDI3MDI1+_R
MDI1-_R
MDI2+
MDI2MDI0+_R
MDI0-_R

1
2
3
4
5
6
7
8
9
10
11
12

GIGA@

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

MCT3
MDO3+
MDO3MCT2
MDO1+
MDO1MCT1
MDO2+
MDO2MCT0
MDO0+
MDO0-

2 R534
1 GIGA@
75_0402_5%
2 R535
1 GIGA@
75_0402_5%

LAN_GND

2 R537
1
75_0603_5%

GSL5009LF

D11
PESD5V0U2BT 3P
@

1
C585
1000P_1206_2KV7K

2
T7
MDI1+_R
MDI1-_R
+1.7_VDDCT_R

12/13 PreMP Add it for avoid to be struck by lightning

+1.7_VDDCT_R
MDI0+_R
MDI0-_R

Near to near JRJ45.

11

SURGE@

10
9
8
7
6

10
9
8
7
6

SURGE@

10
9
8
7
6

GND

1
2
3
4
5

10
9
8
7
6

MDO1+
MDO1MCT1
MCT0
MDO0+
MDO0-

JRJ45

<24> ACTIVITY

ACTIVITY

C387
470P_0402_50V7K

PVT Add EMI solution.

R538

1 220_0402_5%

R97
BLM18PG181SN1D_0603
2
1

ACTIVITY_R

12

Amber LED-

11

Amber LED+

SHLD4

16

MDO3-

PR4-

SHLD3

15

MDO3+

PR4+

MDO1-

PR2-

MDO2-

PR3-

MDO2+

PR3+

MDO1+

PR2+

MDO0-

PR1-

MDO0+

PR1+

MDO1+
C863
1

0.1U_0603_25V7K
2
<24> LAN_LINK#

11

1
2
3
4
5

16
15
14
13
12
11
10
9

D52
MDO1-

TX+
TXCT
NC
NC
CT
RX+
RX-

MDO0+

TCLAMP3302N.TCT_SLP2626P10-10

R884
1

TCLAMP3302N.TCT_SLP2626P10-10

0_0402_5%
2

LAN_LINK#
1
C386
470P_0402_50V7K

+3V_LAN
2

40 mil

LAN_GND

1
2
3
4
5

GND

1
2
3
4
5

D13
PESD5V0U2BT 3P
@

8152@

TD+
TDCT
NC
NC
CT
RD+
RD-

S X'FORM_ NS681680

D55
MDO0-

1
2
3
4
5
6
7
8

Place closely JRJ45

40 mil
2 R536
1
75_0603_5%

RJ45_GND

C440 2

SCV00001400

C438 2

+1.7_VDDCT_R
<24>
<24>

T8

C436 2

SCV00001400

1 0.1U_0402_16V4Z
GIGA@

C435 2

1 1U_0402_6.3V4Z

C427 2

MCT0

SCV00001400

R306
0_0603_5%

MCT1

SCV00001400

SHLD2

14

10 Green LEDSHLD1
220_0402_5%
2
1 +3V_LAN_R 9 Green LED+
R702
FOX_JM36113-P2221-7F
1
ME@
C395
470P_0402_50V7K
2

13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

LAN_Transformer
Size
B
Date:

Document Number

Rev
1.0

LA7012P
Friday, December 24, 2010

Sheet
1

25

of

41

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).

+3VS
1

HDA_RST_CODEC#

EMI

HDA_SYNC_CODEC
R363
4.7K_0402_5%

HDA_SDOUT_CODEC

1
33_0402_5%

HDA_BITCLK_CODEC

2
R331

HDA_RST_CODEC#

1
22P_0402_50V8J
C370

@
2

1
22P_0402_50V8J
C378

22P_0402_50V8J
C375

C584
100P_0402_50V8J

1
22P_0402_50V8J
C376

2
D

R309

0.1U_0402_16V4Z

C410

AVDD_3.3 pinis output of

internal LDO. NOT connect
to external supply.

2 R338
1
R343

38
37

SPK_L2+
SPK_L1-

C416
1
2
0.1U_0402_16V4Z

11
13

Internal SPEAKER
SPK_R2+
SPK_R1-

16
14

+CLASSD_5V_C

MIC_INR
MIC_INL

35
34
33

C_BIAS
PORTC_R
PORTC_L
GPIO0/EAPD#
GPIO1/SPK_MUTE#

DMIC_CLK
DMIC_1/2

R344

2 5.11K_0402_1%

R345
R346

1
1

2 10K_0402_1%
2 39.2K_0402_1%

C403
C415

R601
R602

1
1

2
2

15_0402_5%
15_0402_5%

2 3.3K_0402_5%
2 3.3K_0402_5%

EXT_MICR_C
EXT_MICL_C

2 2.2U_0603_10V7K
2 2.2U_0603_10V7K

1
1

+VAUX_3.3
MIC_JD <30>
PLUG_IN <30>

Port C
Port A

Sense resistors must be

connected same power
that is used for VAUX_3.3

Vender advise: Change R352 and R351 frorm 2.2K to 3.3K by Danson

R352 1
R351 1

+MICBIASC

HP_OUTR_R
HP_OUTL_R

23
22

HP_OUTR <30>
HP_OUTL <30>

+MICBIASC

R350

100_0402_1%

R356

100_0402_1%

EXT_MIC_R <30>
EXT_MIC_L <30>

External MIC

Headphone

Changed from 5.1ohm to 15ohm for "zi zi"noise.

NC
NC
NC

LEFT+
LEFTRIGHT+
RIGHT-

EXT_MICR
EXT_MICL

+5VS

<BOM Structure>

Internal MIC

+MICBIASB

32
31
30

0.1_1206_1%

Please bypass caps very close to device.

SENSE_A

36

1 R348

10U_0805_10V4Z

10U_0805_10V4Z
C399

PC_BEEP

41

2
0_0402_5%

0.1U_0402_16V4Z
C390

C391
C393

AVDD_3.3
AVDD_5V
AVDD_HP

PORTB_R
PORTB_L
B_BIAS

12
15
17

0.1U_0402_16V4Z
C392

0.1U_0402_16V4Z

10U_0805_10V4Z
C411

C413
27
28
26

29

3
7
2
18

AVEE
FLY_P
FLY_N

24
25
39

Vender advise: Change R349 frorm 4.7K to 2.2K and C347 from 2.2u to 4.7
21
19
20

+MICBIASB
1
C401

2
1U_0603_10V4Z

GND

C396
1
2
0.1U_0402_16V4Z

SENSE_A

PORTA_R
PORTA_L
40
1

+CLASSD_5V

CX20671-11Z_QFN40_6X6

10

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

LPWR_5.0
RPWR_5.0
CLASS-D_REF

+5VS

R349
2.2K_0402_5%

Add for ESD solution.

1

5
8
6
4

RESET#

1
0_0603_5%

10U_0805_10V4Z

1
2

C406

0_0402_5%
EC_MUTE#
0_0402_5%

0.1U_0402_16V4Z
C404

PC_BEEP

U17

FILT_1.65

HDA_RST_CODEC#

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

HDA_BITCLK_CODEC
HDA_SYNC_CODEC
33_0402_5% 1
R336 2 HDA_SDIN0_R
HDA_SDOUT_CODEC

EAPD active low

0=power down ex AMP
1=power up ex AMP
<27>
EAPD
<27> EC_MUTE#

0.1U_0402_16V4Z

2
<18> HDA_BITCLK_CODEC
<18> HDA_SYNC_CODEC
<18> HDA_SDIN0
<18> HDA_SDOUT_CODEC

10U_0805_10V4Z
C379

FILT_1_8

10K_0402_5%
C371

+AVDD_5V

10K only needed if supply to VAUX_3.3

is removed during system re-start.

0.1U_0402_16V4Z

1U_0603_10V4Z
C377

C369

R329

<18> HDA_RST_CODEC#

MIC1

2
0_0402_5%

1
2

2
0_0402_5%

WM-64PCY_2P
45@

C394
1

MIC_IN
GNDA

4.7U_0603_6.3V6K
2

MIC_INR

MIC_INL

@ R362
1

R311

@ R354
1

Layout Note:Path from +5VS to LPW R_5.0

RPW R_5.0 must be very low
resistance (<0.01 ohms)

R332

@ R355
1

10U_0805_10V4Z
C409

R328
@

2
0_0402_5%

+LDO_OUT_3_3V_R

0.1U_0402_16V4Z

FILT_1_65

C414

0.1U_0402_16V4Z

1U_0603_10V4Z
C412

+VDD_IO

0_0402_5%

0.1U_0402_16V4Z

C381

0.1U_0402_16V4Z

10U_0805_10V4Z
C380

2
1
+3VALW
0_0402_5%
R337
To support Wake-on-Jack or Wake-on-Ring, the CODEC
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed.
*DSH page42 has more detail.

+3VALW

R339
@

+3VS

C407

+VAUX_3.3

0_0402_5%

0.1U_0402_16V4Z
C408

+3VS

+DVDD_3_3

1
0_0603_5%

10U_0805_10V4Z
C400

+3VS

D4
PESD5V0U2BT 3P

GNDA
1

GND

Add for ESD solution.

wide 20MIL
JSPK1
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

<27>

BEEP#

D18

ICH Beep

SB_SPKR

1
RB751V_SOD323
R582
1
2
33_0402_5%

1
C645

5
6

D5
PESD5V0U2BT 3P
@

D6
PESD5V0U2BT 3P
@

GND1
GND2
ACES_88231-04001
ME@

PC_BEEP
2
0.1U_0402_16V4Z

D35

RB751V_SOD323
2
1PC_BEEP2
R599 @ 0_0402_5%

Add for ESD solution.

<19>

@
R585
10K_0402_5%
2

1 PC_BEEP1
0_0402_5%

1
2
3
4

EC Beep

C632

@
2
R598

1
2
3
4

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

1000P_0402_50V7K

2
2
2
2

1000P_0402_50V7K
C635

1
1
1
1

1000P_0402_50V7K
C634

L19
L20
L22
L23

1000P_0402_50V7K
C633

SPK_R1SPK_R2+
SPK_L1SPK_L2+

PC Beep

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

CX20671 Codec
Size
C

Document Number

Rev
1.0

LA7012P

Date: Friday, December 24, 2010

Sheet
1

26

of

41

+3VALW
+EC_AVCC

+3VALW

C859
0.1U_0402_16V4Z

09/16 Add C859 For ESD

R932
47K_0402_5%

KSO[0..17]
<32>

KSO[0..17]

<32>

KSI[0..7]

KSI[0..7]

KSO1

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

2
1

0_0402_5% 1
0_0402_5% 1

<19> SLP_S3#
<19> SLP_S5#

1
1
R71

2
@ 0_0402_5%
3

PCI_PME#

R95 2
S3#
R96 2
S5#
EC_SMI#
LID_SW#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

EC_PME#
<32>

KILL_SW#

FAN_SPEED1

PS2 Interface

+3VALW

<19,32> ODD_DA#
<23> EC_TX_P80_DATA
<23> EC_RX_P80_CLK
<30>
ON/OFF#
<30,32> PWR_LED#
<30> NUM_LED#

@ Q19
2N7002H_SOT23-3

EC_TX_P80_DATA
EC_RX_P80_CLK

NUM_LED#

XCLKI
XCLKO

1
R99

FRD#SPI_SO
2
@ 100K_0402_1%

1
R86

FSEL#SPICS#
2
@ 100K_0402_1%

122
123

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

1
R85 @

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0

V18R

+3VALW
KB926QFE0_LQFP128
U46

2 LID_SW#
100K_0402_1%

DAC_BRIG

TSATN#_EC

R59

E0 version
SA00001J5A0

100
101
102
103
104
105
106
107
108

2 @ 10K_0402_5%

R67

KB926 SPI STRAP PIN

BATT_SEL_EC <36>
CMOS_OFF# <22>
FRD#SPI_SO

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

<28>

R818 2
R817 1
R421 1

CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
SYSON

EC_RSMRST#
EC_LID_OUT#
EC_ON

SPI_SI <28>
SPI_CLK_R <28>
SPI_CS# <28>

1
1

R235
2.2K_0402_5%

@
C533
100P_0402_50V8J

EC_SMB_CK2
EC_SMB_DA2
@
C534
100P_0402_50V8J

2
1

R234
2.2K_0402_5%

NC

2 4.7K_0402_5%

ACIN

S4#

PBTN# 1

2
100P_0402_50V8J
2
100P_0402_50V8J

R36
10K_0402_5%

EC_RSMRST#

BKOFF# <22>
WL_OFF# <23>
DDR3_SM_PWROK

R93

1
C527
1
C528

+3VALW

0_0402_5%
1
2ICH_POK
R76

ICH_POK_EC

1
R77

<8>

+3VALW
ICH_POK

<8,19>

2
+3VS
4.7K_0402_5%
@

R66

USB_ON#

2 0_0402_5%
ENBKL
EAPD
EC_THERM#
SUSP#
R94 2 0_0402_5%
BT_OFF#

SLP_S4# <19>
ENBKL
<10>
EAPD
<26>
EC_THERM# <19>
SUSP#
<31,38>
PBTN_OUT# <19>

2 10K_0402_5%

1
1
R104

2
@ 10K_0402_5%

change to 'L' active

<30>

124
1

C529
4.7U_0603_6.3V6K

1
@
C927
1U_0603_10V4Z

FAN1 Conn

+5VS
@
C530
1000P_0402_50V7K

R68
10K_0402_5%

R227
0_0402_5%

C531
10P_0402_50V8J

C490
10U_0805_10V4Z

JFAN1

Add C388 for noise

FAN_SPEED1
EC_FAN_PWM

1 R619
1
R620

TACH_R
2 0_0402_5%
FAN_PWM_R
2
0_0402_5%

VR_ON

1
C388
1000P_0402_50V7K

X1

NC

<31,39>
<40>
<19,36>

OSC

R62

BATT_TEMP

1 0_0402_5%
2 33_0402_5%
2 0_0402_5%

OSC

TP_DATA

EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON
<30,37>

BKOFF#

15P_0402_50V8J

2 4.7K_0402_5%

SUSP#

C532

+3VS

XCLKO

R237
20M_0603_5%
@

R61

FSTCHG <36>
CHARGE_LED0# <32>
CAPS_LED# <30>
CHARGE_LED1# <32>
SYSON
VR_ON
ACIN

ACIN

TP_CLK

EN_WOL#

110
112
114
115
116
117
118

C656 closely U46.65

+5VS

2 @ 4.7K_0402_5%

EN_WOL#

Change D46 from SJ100001U00 to SJ132P7KW10

+3VS

C655 closely PU3.3

TP_CLK
<32>
TP_DATA <32>

EC_SMB_DA1
2
4.7K_0402_5%

2
R65

@
C656

EC_MUTE# <26>
USB_ON# <29>
NOVO#
<30>

TP_CLK
TP_DATA

119
120
126
128
73
74
89
90
91
92
93
95
121
127

+3VALW

1
R236

C655

IREF
<36>
CHGVADJ <36>

USB_ON#

97
98
99
109

<8>

IREF

83
84
85
86
87
88

TSATN#

<22>

SPI_CLK_R
EC_SMB_CK1
2
4.7K_0402_5%

ADP_I

2 @ 0_0603_5%

+5VALW

1
R84

FSTCHG

<36>

DAC_BRIG

SPI Device Interface

GND
GND
GND
GND
GND

+3VALW

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

11
24
35
94
113

<17>

<19> EC_SMI#
<32> LID_SW#

2
0_0402_5%

R70

77
78
79
80

68
70
71
72

10/01 Add for reduce noise

BATT_TEMP <35>
ADP_I

ECAGND

<24> LAN_WAKE#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<35> EC_SMB_CK1
<35> EC_SMB_DA1
<4> EC_SMB_CK2
<4> EC_SMB_DA2

R69
10K_0402_5%

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

EC_FAN_PWM

<34,36>

EC_MUTE#

+3VALW
KSO2

AVCC

67

9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

ACOFF

R105
10K_0402_5%

PCI_RST#

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

63
64
65
66
75
76

BATT_TEMP

INVT_PWM <22>
BEEP#
<26>

ACOFF

PWM Output

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

INVT_PWM
BEEP#

21
23
26
27

100P_0402_50V8J

<19>
EC_SCI#
<35> BATT_LEN#

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PVT
Add BATT_LEN# on Pin38

Place closely pin13

R931
47K_0402_5%

12
13
37
20
38

EC_RST#
EC_SCI#
BATT_LEN#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

100P_0402_50V8J

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<16> CLK_PCI_LPC
<17> PCI_RST#

1
2
3
4
5
7
8
10

KB_RST#_EC

NUM_LED#
2
@ 10K_0402_5%
CAPS_LED#
2
@ 10K_0402_5%

1
R102
1
R103

+3VS

1
@
10_0402_5%
R100

2
47K_0402_5%
C524
0.1U_0402_16V4Z

AGND

1
R63

GATEA20

<19>
SERIRQ
<18> LPC_FRAME#
<18>
LPC_AD3
<18>
LPC_AD2
<18>
LPC_AD1
<18>
LPC_AD0

Change D46 from SC1H751H010 to SCS00000Z00 .

+3VALW

<18>

10/01 Danson

2
1
2
@ C525 22P_0402_50V8J

69

D46
2 @
RB751V_SOD323

KB_RST#

+3VS

2
0_0402_5%

R60
<18>

C523
1000P_0402_50V7K

C520
1000P_0402_50V7K

C522
1000P_0402_50V7K
2 1 ECAGND 2
FBM-11-160808-601-T_0603

1
L24

C519
0.1U_0402_16V4Z

C518
0.1U_0402_16V4Z

+EC_AVCC

C517
0.1U_0402_16V4Z

C516
0.1U_0402_16V4Z

L21 1
2
FBM-11-160808-601-T_06032
C521
0.1U_0402_16V4Z

+3VALW

1
2
3
4
5
6

1
2
3
4
G5
G6
ACES_85205-04001
ME@

For SED Team

32.768KHZ_12.5PF_Q13MC14610002

Close PR131.1

C535
XCLKI
15P_0402_50V8J

Compal Secret Data

Security Classification
Issued Date

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

EC / FAN Conn

Size
Document Number
Custom
Date:

Friday, December 24, 2010

Rev
1.0

LA7012P
Sheet

27

of

41

FOR EC 16M SPI ROM

SPI Flash (16Mb*1)

FOR EC 256K SPI ROM (NONShare ROM)

Change U31 P/N from SA00000XT00 to SA000041N00 0915

+3VALW

20mils
1
C1170
0.1U_0402_16V4Z

<27>

U31
8

2
R921
2
R922
SPI_CS#

1 SPI_W# 3
0_0402_5%
1SPI_HOLD# 7
0_0402_5%
SPI_CS#
1

<27>

VSS

+3VALW

U23
SPI_CS# 1
SPI_W# 3
SPI_HOLD# 7
4

HOLD
S

SPI_SI

SPI_SI

Add U23 for NONShare SPI ROM.

LPC@

VCC

SPI_CLK_R
<27> SPI_CLK_R

2010/09/24

Change U31 footprint from WIESO_G6179-100000_8P to

MX25L1606EM2I-12G_SO8 0920

SPI_SO

VDD
SCK
SI
SO

8
6
5
2

SPI_CLK_R
SPI_SI
SPI_SO

W25X20BVSNIG SOIC 8P

FRD#SPI_SO <27>

FRD#SPI_SO
1
0_0402_5%

2
R816

SPI@

CE#
WP#
HOLD#
VSS

SA00003GM10

MX25L1606EM2I-12G_SO8

256kB(NAU00 2nd)

+5VALW

SATA HDD Conn.

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

C130
0.1U_0402_16V4Z

Near H7

Near H3

C131
0.1U_0402_16V4Z

+3VALW

C132
0.1U_0402_16V4Z

Near H2

Near H6

Near H22

Near H4

Near H16

+3VS

+3VS

H9
HOLEA

C150
0.1U_0402_16V4Z

H15
HOLEA

Near H6

Near H6

H11
HOLEA

H12
HOLEA

3P2 X1
H19
HOLEA

H20
HOLEA

BOTTOM SIDE
FAN

FD1

Issued Date

FD2

2010/09/10

Near C147

FD3
1

FD4

H10
HOLEA

H23
HOLEA

H_3P0X4P0N
BOTTOM SIDE
WLAN

Deciphered Date

H16
HOLEA

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_4P5X3P0N

H24
HOLEA

Compal Secret Data

Security Classification

J:H_2P8 X1 I:H_3P0N X1

BOTTOM SIDE
VGA

H_4P2

C148
0.1U_0402_16V4Z

Title

H_6P0N

H21
HOLEA

H17
HOLEA

C149
0.1U_0402_16V4Z

SUYIN_127043FB022G208ZR_RV
ME@

H18
HOLEA

2
2
C126
0.1U_0402_16V4Z

D:H_3P8

H_4P2

C123
10U_0805_10V4Z

+5VS_HDD

H6
HOLEA

1
2
0_0805_5%

H8
HOLEA

H5
HOLEA

H4
HOLEA

C125
1000P_0402_50V7K

H7
HOLEA

H3
HOLEA

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

H2
HOLEA

R749

H1
HOLEA

2
+5VS

C147
0.1U_0402_16V4Z

+5VS

+3VS

A:H_2P8

C121 @
0.1U_0402_16V4Z

C133
0.1U_0402_16V4Z

+3VS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

C444 1
C445 1

Near H1

GND
A+
AGND
BB+
GND

C128
0.1U_0402_16V4Z

+5VS

H22
HOLEA

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

+5VS

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

C124
0.1U_0402_16V4Z

+5VS

<18> SATA_DTX_C_IRX_N0
<18> SATA_DTX_C_IRX_P0

C441 1
C442 1

1
2
3
4
5
6
7

JHDD1

10/11 Change JHDD1 P/N from SP01000QT00 to SP01000FX00

<18> SATA_ITX_C_DRX_P0
<18> SATA_ITX_C_DRX_N0

C122
0.1U_0402_16V4Z

+5VALW

Compal Electronics, Inc.

HDD / SPI ROM / Hold

Size
B
Date:

Document Number

Rev
1.0

LA7012P
Friday, December 24, 2010

Sheet

28

of

41

+USB_VCCA
JUSB1 ME@

W=80mils

+5VALW

D25
@

USB20_N0

USB20_P0

1
L66

U19
C421 0.1U_0402_16V4Z
2
1
<27>
USB_ON#

1
2
3
4

USB_ON#

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

RIGHT USB PORT X1

8
7
6
5

USB_OC#0 <19>

USB20_N0_R

USB20_P0_R

1
2
3
4
5
6

1
2
3
4
G5
G6

Right USB Conn.

ACES_85205-04001

PJDLC05_SOT23-3

WCM-2012-900T_4P
+USB_VCCA

USB20_N0_R
USB20_P0_R

1 0_0402_5%
1 0_0402_5%

C615
220U_6.3V_M

2 R914
2 R912

+USB_VCCA
1
<19> USB20_N0
1
<19> USB20_P0
+
C715
470P_0402_50V7K
2
2

PVT Change U19 and U27 part number from SA000039E00 to SA00002XX00

RT9715BGS_SO8
C429
@ 1000P_0402_50V7K

+USB_VCCB

C430
220U_6.3V_M

2 R918
2 R913

<19> USB20_N1
<19> USB20_P1

USB20_N1_R
USB20_P1_R

1 0_0402_5%
1 0_0402_5%

C432
470P_0402_50V7K

USB20_N1

USB20_P1

+5VALW
+USB_VCCB

USB_ON#
1
C621
0.1U_0402_16V4Z
3

8
7
6
5

RT9715BGS_SO8

USB20_N1_R

USB20_P1_R

C610
@ 1000P_0402_50V7K

SUYIN_020173MR004S558ZL
ME@

Left2 USB Conn.

Change JUSB3 connector from ESATA to USB

+USB_VCCB

JUSB3

W=80mils

C623
220U_6.3V_M

+USB_VCCB
1
<19> USB20_N7
1
<19> USB20_P7
+
C622
470P_0402_50V7K
2

2 R924
2 R923

1 0_0402_5%
1 0_0402_5%

USB20_N7_R
USB20_P7_R

+USB_VCCB
L64

Near C622
1

USB20_N7

USB20_P7

1
C660
0.1U_0402_16V4Z

USB20_N7_R

USB20_P7_R

1
2
3
4
GND
GND
GND
GND
SUYIN_020173MR004S558ZL
ME@

WCM-2012-900T_4P

1
2
3
4
5
6
7
8

D10
@

+5VALW

PJDLC05_SOT23-3

Pre MP ADD for ESD solution

C661
0.1U_0402_16V4Z

Left USB Conn.

USB_OC#1_7 <19>
1

Near D10

1
2
3
4
GND
GND
GND
GND

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

WCM-2012-900T_4P

LEFT USB PORT x2

U27
1
2
3
4

PJDLC05_SOT23-3

D47
@
L63

1
2
3
4
5
6
7
8

JUSB2

W=80mils

+USB_VCCB
1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

USB ports/BT
Size
B
Date:

Document Number

Rev
1.0

LA7012P
Friday, December 24, 2010

Sheet
E

29

of

41

Power Bottom Board Conn. 8pin

ON/OFF switch

NOVO_BTN#

CAPS_LED#
D19
PJSOT24C 3P C/A SOT-23

J5
2
2

SHORT PADS

R272
100K_0402_5%
1

D14

ON/OFF#

+5VALW
PWR_LED#

NUM_LED#
CAPS_LED#

+5VALW
NOVO_BTN#
ON/OFFBTN#
+5VS

+5VS

2
BT@
C353
2

MIC_JD
EXT_MIC_L
EXT_MIC_R

CardReader
<19>
<19>

2 R926
2 R925

USB20_P4
USB20_N4

USB20_N4

USB20_P4

USB20_P4_R
USB20_N4_R

1 0_0402_5%
1 0_0402_5%

USB20_P6
USB20_N6

<23>

BT_ACTIVE

JCR1
1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

3USB20_N4_R

ACES_85201-1205N

2USB20_P4_R

ME@

D7
PESD5V0U2BT 3P

ACES_87213-0600G

EXT_MIC_L

EXT_MIC_R

HP_OUTL

JBT1 ME@
1 1
2 2
3 3
4 4
5 5 G1 7
6 6 G2 8

HP_OUTR

C354
BT@
0.1U_0402_16V4Z

WCM-2012-900T_4P

USB20_P6
USB20_N6
BTON_LED
BT_ACTIVE

MIC_JD

C366

D8
PESD5V0U2BT 3P
@

D9
PESD5V0U2BT 3P
@
1

<19>
<19>
2

Q32
BT@
AP2301GN-HF_SOT23-3

30mils

C365

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GND

<26> MIC_JD
<26> EXT_MIC_L
<26> EXT_MIC_R

R583
0_0603_5%
1+3VS_BT_R 1
2

BT@
Q29
DTC124EKAT146_SC59-3

C364

+3VS_BT

BT@

IN

+3VS

PLUG_IN
HP_OUTR
HP_OUTL

L65

BT@
Q31
DTC124EKAT146_SC59-3

OUT

BT_LED#

NOVO_BTN#

3
DAN202UT106_SC70-3

+3VS

<32>

1
51_ON#

<26> PLUG_IN
<26> HP_OUTR
<26> HP_OUTL

PLUG_IN

GND

IN

51_ON#

0.1U_0402_16V4Z

NOVO#

<34>

OUT

1 R616
2
100K_0402_5%
BT@

<27>

D44

1
2

BT@
R304
100K_0402_5%

NOVO#

C360

Card Reader/Audio Jack SB CONN

R296
100K_0402_5%

BT MODULE CONN

0.1U_0402_16V4Z

D51
AZ5125-02S.R7G_SOT23-3

D50
AZ5125-02S.R7G_SOT23-3

0.1U_0402_16V4Z

D49
AZ5125-02S.R7G_SOT23-3

Q28
2N7002H_SOT23-3

+3VALW

BT_OFF#

PVT ESD solution.

D15
@
RLZ20A_LL34

R302
10K_0402_5%

<27>

C359

1
S

C356
@
1000P_0402_50V7K

2
G

+5VALW

EC_ON
2

EC_ON

C358

51_ON#

2
DAN202UT106_SC70-3

<27,37>

C357

ACES_85201-08051
ME@

ON/OFF# <27>

EMI REQUEST 1ST = SCA00000E00

2ST = SCA00000R00

ON/OFFBTN#

NOVO_BTN#
ON/OFFBTN#
PWR_LED#

@1

Bottom Side

<27,32> PWR_LED#

6
5

+3VALW

TOP Side

0.1U_0402_16V4Z

<27> NUM_LED#
<27> CAPS_LED#

SMT1-05_4P

PWR_LED#

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
9
10

0.1U_0402_16V4Z

JPWRB2

0.1U_0402_16V4Z

SW1

Power Button

NUM_LED#

ON/OFFBTN#
+5VALW +5VS

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

2010/09/10

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Audio Jack & SW & BT Conn.

Size
B

Document Number

Date: Friday, December 24, 2010

Rev
1.0

LA7012P
Sheet

30

of

41

+VSB
+VSB

+3VALW TO +3VS
1

+5VALW TO +5VS
R229
10K_0402_5%

Change U10 from

SB548000320 to SB000009510

Change U14 from

5VS_GATE_R

2
C278
0.1U_0603_25V7K

SUSP

Q46
2N7002H_SOT23-3

C144
0.1U_0603_25V7K

+5VS

5
6
7
C279
8
10U_0805_10V4Z

3
2
1
U10
AO4468L_SO8

C276
1U_0603_10V4Z
1 2

1
C277
10U_0805_10V4Z

+3VALW
5
6
1
7
C127
8
10U_0805_10V4Z
2

R202
470_0603_5%
@

3
2
1

U4
AO4468L_SO8

2 SUSP
G
Q16
2N7002H_SOT23-3
@

+3VS

1
C134
10U_0805_10V4Z

3VS_GATE_R
1
0_0402_5%

2
R88

2
G
3

S
+5VALW

3VS_GATE

Q20
2N7002H_SOT23-3

2
G

C135
1U_0603_10V4Z
1 2

5VS_GATE 2
R228 1
10K_0402_5%

SUSP

1
1

SB548000320 to SB000009510

R89
47K_0402_5%

R87
470_0603_5%
@

2 SUSP
G
Q6
2N7002H_SOT23-3
@

+VSB

2 SUSP
G
Q40
2N7002H_SOT23-3
@

+1.5V to +1.5VS

2 SUSP
G
Q11
2N7002H_SOT23-3
@

Change U16 from

Q33

1.5VS_GATE
D

1.5VS_GATE_R
1
0_0402_5%
1

2
R313

SUSP

SYSON

SYSON

IN

1
C362
10U_0805_10V4Z

C363
1U_0603_10V4Z

R314
470_0603_5%
@

<27,39>

3
2
1

OUT
IN

GND

SUSP#

+1.5VS

U16
AO4468L_SO8

OUT

Q2
DTC124EKAT146_SC59-3
@

<27,38>

5
6
1
7
C389
8
10U_0805_10V4Z
2

GND

SYSON#
Q45
DTC124EKAT146_SC59-3

+1.5V

@
R6
100K_0402_5%

SUSP

+5VALW
1

SUSP

@
R5
10K_0402_5%

<39>

R4
100K_0402_5%

C361
0.1U_0603_25V7K

PVT Change R5 from 100K to 10K.

+5VALW

+3VLP

2
2
0.1U_0603_25V7K

Change SUSP pull high from +5VALW to +3VLP.

1
C373
@

2
G
2N7002H_SOT23-3
S

Pre MP

SB548000320 to SB000009510

100K_0402_5%
R312
2

R568
470_0603_5%
@

1 2

R143
470_0603_5%
@

1
1 2

1 2

+0.75VS

D
2 SYSON#
G
Q35
2N7002H_SOT23-3
@

R342
470_0603_5%
@

D
2 SUSP
G
Q10
2N7002H_SOT23-3
@

1 2

R142
470_0603_5%
@

+1.05VS

+1.5V

+1.8VS

2 SUSP
G
Q34
2N7002H_SOT23-3
@

2010/09/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/08/19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom
Date:

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

E

31

of

41

INT_KBD Conn.
Lid Switch

Kill Switch

+3VALW

+VCC_LID

STATUS
1,2(LOW)
2,3(HI)

R615
100K_0402_5%
1
2

R614

0_0402_5%

1
C694
0.1U_0402_16V4Z

+3VALW
R617
100K_0402_5%
2
1

VDD

OUTPUT

GND

U32

OFF
ON

SW2

LID_SW# <27>
<27>

C695
10P_0402_50V8J

KILL_SW#

S-5711ACDL-M3T1S_SOT23-3
LSSM12-P-V-T-R_3P

<27>

KSI[0..7]

<27>

KSO[0..17]

KSI[0..7]

JKB1

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

C721
C722
C723
C724
C725
C726
C727
C728
C729
C730
C731
C732
C733
C734
C735
C736
C747
C746

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

C737
C738
C739
C740
C741
C742
C743
C744

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

PVT Change U32 part number from SA032120010 to SA000031C00

LED
LED1

White

<27,30> PWR_LED#

LED1_5V
2
300_0402_5%

1
R622

+5VALW

LED2_3V
2
300_0402_5%

1
R623

+3VALW

LED2_5V
2
470_0402_5%

1
R624

+5VALW

19-213A-T1D-CP2Q2HY-3T_WHITE
LED2

Orange

BATT_LOW_LED#

BATT_CHG_LED#

White

G1
G2

31
32

ACES_85201-3005N
ME@

Reserve for ESD.

check connector & pin define.

LED3

D22

White

LED3_5V
2
300_0402_5%

1
R627

+5VS

RB751V_SOD323

CONN PIN define need double check

19-213A-T1D-CP2Q2HY-3T_WHITE

D23
<30> BT_LED#

18-225A-S2T3D-C01-3T_ORG-WHITE

<23> WLAN_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

<27> CHARGE_LED1#
<27> CHARGE_LED0#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

KSO[0..17]

To TP/B Conn.

+5VS

Add for ESD solution.

RB751V_SOD323
C701

TP_CLK
TP_DATA

LED4

1
R628

JTP1

+5VS
<27>
<27>

19-213A-T1D-CP2Q2HY-3T_WHITE

4
3
2
1

TP_CLK
TP_DATA

TP_CLK
TP_DATA

ODD Power Control

@
C699
100P_0402_50V8J

@
C700
100P_0402_50V8J

LED4_5V
2
300_0402_5%

4
3
2
1

D48
PESD5V2S2UT_SOT23-3

E&T_6905-E04N-00R
ME@

<18> HDD_LED#

0.1U_0402_16V4Z

White

11/05 Add this function.

J9

+5VS_ODD

2
R677

@
2

AP2301GN-HF_SOT23-3
@
1

C613

IN

0.01U_0402_16V7K

<18> SATA_ITX_C_DRX_P1
<18> SATA_ITX_C_DRX_N1

C612
0.1U_0402_16V4Z

<18> SATA_DTX_C_IRX_N1
<18> SATA_DTX_C_IRX_P1

100K_0402_5%

OUT
<19> ODD_EN

GND

Q99
R552
10K_0402_5%

C428 1
C431 1

2 0.01U_0402_16V7K SATA_ITX_DRX_P1
2 0.01U_0402_16V7K SATA_ITX_DRX_N1

C437 1
C439 1

2 0.01U_0402_16V7K SATA_DTX_IRX_N1
2 0.01U_0402_16V7K SATA_DTX_IRX_P1
+5VS_ODD

C611
10U_0805_10V4Z

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

@R717
@
R717

2 0_0402_5% ODD_DETECT#

R554
ODD_DA#

<19,27> ODD_DA#

@
Q100
DTC124EKAT146_SC59-3

+3VS

R555
1

@
2 0_0402_5%

@
2
10K_0402_5%

GND
GND

17
16
A

OCTEK_SLS-13SB1G_RV
ME@

Compal Secret Data

Security Classification

Issued Date

2010/09/10

Deciphered Date

2010/08/19

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

JODD1

SATA ODD Conn.

1
@

JUMP_43X79

+5VS

Compal Electronics, Inc.

KB/TP/LID/KLL/ODD/LED FOR 14

Size Document Number

Custom
Date:

Rev
1.0

LA7012P

Friday, December 24, 2010

Sheet
1

32

of

41

9HUVLRQFKDQJHOLVW3,5/LVW
,WHP

)L[HG,VVXH

3DJHRIIRU+:
5HDVRQIRUFKDQJH

5HY

3*

0RGLI\/LVW

'DWH

3KDVH



D









C













B










A



2010/09/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HW PIR
Size Document Number
Custom
Date:

Rev
1.0

LA7012P
Sheet

Friday, December 24, 2010

1

33

of

41

VIN

DC030006J00

PF1
7A_24VDC_429007.WRML
APDIN
1
2 APDIN1

Precharge detector
15.97V/14.84V FOR
ADAPTOR

PL1
SMB3025500YA_2P
1
2

PreCHG
PR1
1K_1206_5%
1
2

PD1
2

PR6
1K_1206_5%
1
2

2
1

PD2
LL4148_LL34-2
1

PQ2
PDTC115EU_SOT323-3

VS

1 2

PQ3
PDTC115EU_SOT323-3

PC6
0.1U_0603_25V7K

B+

PR12
2.2M_0402_5%
2
1

0.01U_0402_25V7K

PC7
1

PC8
0.1U_0603_25V7K

ML1220T13RE
45@
1

PD6
RB751V-40_SOD323-2

2N7002W-T/R7_SOT323-3

PR19
34K_0402_1%
2
1

+3VLP

PC10
0.01U_0402_25V7K

@ RB715F_SOT323-3

2
1
PR16
499K_0402_1%

ACON

6251VREF

PQ5
2
G

PR20
<36>
47K_0402_1%
2
1

PACIN

<36>
+CHGRTC

1
PR15
205K_0402_1%

PR18
560_0603_5%
1
2

3
2

PRG++ 2

PR17
560_0603_5%
1
2

+RTCBATT

JRTC1
2

1
3
+RTCBATT

PU1A
LM393DG_SO8
1 O

PD5

<35,37> MAINPWON

PR14
100K_0402_1%

2
1
PR13
499K_0402_1%

VS

VL

PC9
1000P_0402_50V7K

51_ON#

RB715F_SOT323-3

1
<30>

PR11
22K_0402_1%
1
2

PR10
100K_0402_1%

PC5
0.22U_0603_25V7K
2
1

N1

1
3

+5VALW

PQ4
TP0610K-T1-E3_SOT23-3

<20,22,27,28,29,30,31,32,37,38,39>

PR9
68_1206_5%

PR8
68_1206_5%

<27,36> ACOFF

BATT+

PD4
1

PD3
LL4148_LL34-2
2
1

PR7
100K_0402_1%

PR3
1K_1206_5%
1
2

VIN

LL4148_LL34-2
@

PR2
1K_1206_5%
1
2

PR5
100K_0402_1%
2
1

VIN

PQ1
TP0610K-T1-E3_SOT23-3

PR4
100K_0402_1%
2
1

1
2

PC4
1000P_0402_50V7K

PC3
100P_0402_50V8J

PC123
1000P_0402_50V7K
2
1

1
2

@ 4602-Q04C-09R 4P P2.5
JDCIN1

PC2
100P_0402_50V8J

1
2

PC1
1000P_0402_50V7K

PC122
1000P_0402_50V7K
2
1

3
D

S
2

PQ6
PDTC115EU_SOT323-3
PR21
2

66.5K_0402_1%

+5VALW

ACIN
Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V

Compal Secret Data

Security Classification
2010/09/10

Issued Date

BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

DCIN / Vin Detector /Pre-charge

Size Document Number

Custom
Date:

Rev
1.0
Sheet

Friday, December 24, 2010

1

34

of

41

VMB2

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

PL2
SMB3025500YA_2P
1
2

BATT+

EC_SMCA
EC_SMDA
1

PC11
1000P_0402_50V7K

PC12
0.01U_0402_25V7K

VL
VL
2
PR24
10K_0402_1%

1
PC13
0.1U_0603_25V7K

TYCO_1775789-1
@
PR25
21.5K_0402_1%

100_0402_1%
1
2

PU2
1

VCC TMSNS1

GND RHYST1

8
7

OT1 TMSNS2

OT2 RHYST2

EC_SMB_CK1 <27>

PR26
@ 100K_0402_1%

PR23

1
2
3
4
5
6
7
8
9

VMB
PF2
12A_65V_451012MRL
1
2

JBATT1
1
2
3
4
5
6
7
GND
GND

G718TM1U_SOT23-8

A/D

BATT_TEMP <27>

PR27
9.76K_0402_1%

+3VALW

1
2
PR30
10K_0402_1%

PH1
100K_0402_1%_TSM0B104F4251RZ

MAINPWON <34,37>

EC_SMB_DA1 <27>

PR22
100_0402_1%

1
2
PR28
6.49K_0402_1%

1
2
PR29
@ 47K_0402_1%

PD15

PD16

PH2
@ 100K_0402_1%_TSM0B104F4251RZ

@ PJSOT24C

@ PJSOT24C

6251VREF

<27> BATT_LEN#

2
G

PR39
22K_0402_1%
1
2

PC16
0.1U_0603_25V7K

VL

+VSBP

PQ44
2N7002W-T/R7_SOT323-3

B+
PC15
0.22U_0603_25V7K

PR38
10K_0402_1%

PQ8
TP0610K-T1-E3_SOT23-3

2
1
PR37
100K_0402_1%

2
G

PU1B
LM393DG_SO8

BATT_OUT <36>

O
-

1
+

PQ7
2N7002W-T/R7_SOT323-3

PR32
10K_0402_1%

8
5

PR36
232K_0402_1%

+3VS

PR35
10K_0402_1%
1
2

+3VALW

PR31
100K_0402_1%
PR34
5.1M_0402_5%
1

1
PR33
649K_0402_1%

VMB2

PC14
0.01U_0402_25V7K

VS

PR41
1K_0402_1%
2

D
PQ9
2N7002W-T/R7_SOT323-3

2
G
3

SPOK

<19,37>

PC17
1U_0402_6.3V6K

PR40
100K_0402_1%
PJ1
@ JUMP_43X39
1 1
2 2

+VSBP

+VSB

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

BATTERY CONN/OTP

Size Document Number

Custom
Date:

Rev
1.0
Sheet

Friday, December 24, 2010

1

35

of

41

B+

P3
P2
PQ11
AO4409_SO8

ICOMP

CSIN

20

VCOMP

CSIP

12

LGATE

GND

PGND

DL_CHG

14
13

PC20
2200P_0402_50V7K

1DISCHG_G-1
1

2 ACOFF-1

PC19
4.7U_0805_25V6-K
1
2

PQ19
AO4466L_SO8

5
6
7
8
3
2
1

RB751V-40_SOD323-2
1
2 6251_VDD

PR72
4.7_0402_5%
PC39
4.7U_0805_10V6K

VADJ

6251_VDDP

15

VDDP

PC36
10U_0805_25V6K
2
1

ACLIM

16

PR74
15.4K_0402_1%
1
2

<27> CHGVADJ

3
PC35
10U_0805_25V6K
2
1

BOOT

PR67
4.7_1206_5%

CHLIM

PR69
PC33
0_0603_5%
0.1U_0603_25V7K
BST_CHG 1
2 BST_CHGA 2
1
PD10

1 6251_SN
2

UGATE

PC130
10U_0805_25V6K

6251_VADJ
11

PR73
2.2K_0402_1%

VREF

ISL6251AHAZ-T_QSOP24

Connect to EC A/D Pin.

B

5
6
7
8

1
2
6251VREF
PC32
6251_CHLIM 9
0.1U_0402_16V7K
PR70
21K_0402_1%
1
2 6251_ACLIM 10
6251VREF

PQ23
2N7002W-T/R7_SOT323-3

BATT+

PR64
0.02_1206_1%

CHG
1

PC34
10U_0805_25V6K
2
1

PR71
100K_0402_1%

DH_CHG

17

2
G

18

PACIN

PC38
680P_0603_50V7K

1
1
BATT_OUT

BATT_OUT

PHASE

PL3
10U_LF919AS-100M-P3_4.5A_20%

PQ22
AO4466L_SO8

PR68
154K_0402_1%
2
1

ICM

2
G

2
G
S

3
2
1

IREF

7
8

<27>

1
PR63
100_0402_1%

ADP_I

<27>
PR66
0_0402_5%

<35>

19

PR65
10K_0402_1%

6251_VCOMP 6

ACPRN

CSOP

CSON
CSOP

PQ18
2N7002W-T/R7_SOT323-3

CELLS

21

PC27
0.1U_0603_25V7K
2
1

PR57
20_0402_5%
6251_CSON
1
2
PC28
0.047U_0402_16V7K
6251_CSOP 1
2
PR58
20_0402_5%
6251_CSIN
2
1
PC31
PR60
0.1U_0402_16V7K
20_0402_5%
6251_CSIP
1
2
PR62
2_0402_5%
LX_CHG

PQ20
2N7002W-T/R7_SOT323-3

CELLS

PD9
1SS355_SOD323-2
1
2

2200P_0402_50V7K

22

CSON

EN

PC26
1

6251_EN

PR55
100K_0402_1%
1
2

ACPRN

ACOFF-12

PC37
0.01U_0402_25V7K
2
1

23

PR49
200K_0402_1%

1SS355_SOD323-2

ACSET ACPRN

2 6251_ICM

<27,34> ACOFF

0.01U_0402_25V7K

PQ21
PDTC115EU_SOT323-3

ACSETIN

PC23
1000P_0402_50V7K

PC25
0.1U_0603_25V7K
6251_DCIN
2
1

ACON
1

<34>

10K_0402_1%
2

24

6800P_0402_25V7K
6251_ICOMP
2

PC30
PR61
1
2 6251_VCOMP-1
1

DCIN

PD8

VIN

PC29
1

VDD

PR48
10K_0402_1%

PQ15
PDTC115EU_SOT323-3

2
2

PU3

3
PACIN

PQ16B
2N7002KDW-2N_SOT363-6

2
1

<34>

PR59
47K_0402_1%
PACIN 1
2

PR52
14.3K_0402_1%

P2-2

PQ17
2N7002W-T/R7_SOT323-3

ACSETIN

PR51
10_1206_5%

PR45
47K_0402_1%
1
2

PR47
191K_0402_1%
@

PR56

BATT_OUT

100K_0402_1%

2
G

PC24
2.2U_0603_10V7K
2
1

PR53
10K_0402_1%
12

1
2

6251_VDD

8
7
6
5

DISCHG_G

BATT_ON

PR54
150K_0402_1%

6
PQ16A
2N7002KDW-2N_SOT363-6

1 1

PR50
0_0402_5%
2
1

<27> FSTCHG

1
2
3

PD7
RB751V-40_SOD323-2

P2-1

PR46

PreCHG

PC22
4.7U_0805_25V6-K
1
2

VIN

PQ12
AO4407A_SO8

PC18
4.7U_0805_25V6-K
1
2

1
2

CSIN
CSIP

PC131
5600p_0402_25V7K

PQ14
PDTC115EU_SOT323-3
BATT_ON

PC137
0.1U_0402_25Y5V

PC128
10U_0805_25V6K
2
1

CHG_B+

PL11
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
1
2

191K_0402_1%

PC21
0.1U_0603_25V7K
2
1
PR44
200K_0402_1%

1
PR43
47K_0402_1%

PQ13
PDTA144EU

PR42
0.02_1206_1%

8
7
6
5

PC127
10U_0805_25V6K
2
1

1
2
3

1
2
3

8
7
6
5

VIN

PC126
10U_0805_25V6K
2
1

PQ10
AO4407A_SO8

PR75
31.6K_0402_1%

CHGVADJ=(Vcell-4)/0.10627
CHGVADJ

VCHLIM need over 95mV

<37> ACPRN

ACPRN

PR81
0_0402_5%

PQ25
PDTC115EU_SOT323-3
PR83

PR42=20mohm

CELLS

PACIN

2
1

<19,27>

IREF=0.254V~3.048V

PR73=2.2K

1
PR82
@ 0_0402_5%

<27> BATT_SEL_EC

2
2

IREF=1.016*Icharge

ACIN

PR76
PR77
@ 100K_0402_1% @ 100K_0402_1%

CC=0.25A~3A

PR79
10K_0402_1%

PR78
47K_0402_1%

PR70=21K

PR80
10K_0402_1%
1
2

3.2935V

6251_VDD

4.35V

DIS CP mode (65W*85%)

Vaclim=2.39*((2.2K//152K)/(2.2K//152K+21K//152K))=0.25136V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.25136V, Iinput=2.76293A

1.882V

1 2

0V

4.2V

4cell : VDD
3cell : GND

6251_VDD

4V

6251_VDD

Vcell

14.3K_0402_1%
PQ24B
@ 2N7002KDW-2N_SOT363-6

PQ24A
@ 2N7002KDW-2N_SOT363-6

2010/09/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

CHARGER
Size
Date:

Document Number

Rev
1.0
Sheet

Friday, December 24, 2010

1

36

of

41

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ3
2

+3VALWP
PC40
1U_0603_10V6K

19

LG_5V

3
2
1

RT8205EGQW_WQFN24_4X4

1
2
3
2
1

PC57
4.7U_0805_10V6K

1
2
2
1
PC58
0.1U_0603_25V7K

PC56
1U_0603_10V6K
2
1

RT8205_B+

+5VALWP

1
+

VL

PC49
0.1U_0603_25V7K
2
1

PC47
4.7U_0805_25V6-K
2
1

PC48
2200P_0402_50V7K
2
1

PL5
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
1

LX_5V

PR94
4.7_1206_5%

UG_5V

21
20

Typ: 175mA

PC55
680P_0603_50V7K

NC

EN

VREG5

LGATE1

VIN

LGATE2

13

PC46
4.7U_0805_25V6-K
2
1

ENTRIP1
1

2
FB1

REF

4
TONSEL

ENTRIP1

22

PQ27
SIS412DN-T1-GE3_PAK1212-8

PC54
150U_B2_6.3VM_R45M

PQ29
SI7716ADN-T1-GE3_PAK1212-8

TONSEL=VREF (1)SMPS1=300KHZ(+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

PC59
2.2U_0603_10V7K

PR100
100K_0402_1%

PQ33
PDTC115EU_SOT323-3

23

PHASE1

2VREF_8205

<19,35>

PQ31
PDTC115EU_SOT323-3
1

VS

SPOK

BOOT1

PHASE2

17

12

24

PGOOD

UGATE1

GND

LG_3V

+5VALW

UGATE2

16

11

PR89
121K_0402_1%
2

PR91
PC51
0_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

VFB=2.0V

15

LX_3V

PR98
100K_0402_1%
2
1

2
1
PR101
40.2K_0402_1%

EC_ON

2
G

PQ32
2N7002W-T/R7_SOT323-3

PR99
200K_0402_1%
2
1

1
<27,30>

10

PR97
0_0402_5%
2
1

ACPRN

ENTRIP2

VL

<36>

UG_3V

PQ30B
2N7002KDW-2N_SOT363-6

PQ30A
2N7002KDW-2N_SOT363-6

<34,35> MAINPWON

BOOT2

RT8205_B+

B+
PQ28
SI7716ADN-T1-GE3_PAK1212-8

ENTRIP1

VREG3

PR95
499K_0402_1%
1
2

1
2
3

PC53
680P_0603_50V7K
2
1

+
PC52
150U_B2_6.3VM_R45M

BST_3V

VO1

PR93 @
0_0402_5%
MAINPWON 2
1

PR96
100K_0402_1%

+3VALWP

PC50
0.1U_0603_25V7K

PR92
4.7_1206_5%
2
1

PL4
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2

PR90
2 1
2
0_0603_5%

JUMP_43X118

PC120
@ 2200P_0402_50V7K
1
2

VO2

SKIPSEL

P PAD

1
2
3

14

25

PQ26
4 SIS412DN-T1-GE3_PAK1212-8

ENTRIP2

PU4

FB2

PR88
110K_0402_1%
1
2

+3VALW

PR87
20K_0402_1%
1
2

PC45
4.7U_0805_10V6K

PC44
2200P_0402_50V7K
2
1

PC42
4.7U_0805_25V6-K
2
1

1
2

PR86
20K_0402_1%
1
2
PC119
@ 2200P_0402_50V7K
1
2

+3VLP

1
PC43
4.7U_0805_25V6-K
2
1

@ JUMP_43X118

PR85
30K_0402_1%
1
2

ENTRIP2

PC129
1U_0603_25V6

PC41
0.1U_0603_25V7K
2
1

B+

PR84
13K_0402_1%
1
2

18

Typ: 175mA

PJ5

PJ4
2

+5VALWP

RT8205_B+

@ JUMP_43X118

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

3VALWP/5VALWP

Size Document Number

Custom
Date:

Rev
1.0
Sheet

Friday, December 24, 2010

1

37

of

41

11

VDDP

10

NC

LGATE

2
PR107
11K_0402_1%

+5VALW

PQ35
AO4726L_SO8

DL_VCCP

4
1

PGND
8

GND

PGOOD

6
PC65
4.7U_0603_6.3V6K

RT8209BGQW_WQFN14_3P5X3P5

PC67
4.7U_0805_10V6K

PR108
4.12K_0402_1%
1
2

B+
PC124
1U_0603_25V6

1
2

PC135
0.1U_0402_25Y5V

1
2

PC61
4.7U_0805_25V6-K

PC60
4.7U_0805_25V6-K

+VCCPP

+1.05VS

@ JUMP_43X118

+VCCPP

1
+
2

PC64
220U_6.3V_M

CS

0.1U_0603_25V7K

LX_VCCP

PR105
4.7_1206_5%

15

14

DH_VCCP

12

FB

13

PHASE

UGATE

VDD

PJ7
PL6
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2

PC63

PC66
680P_0603_50V7K

BST_VCCP

5
6
7
8

VOUT

+5VALW

3
2
1

TON

@ 1SS355_SOD323-2

+5VALW

PR106
100_0603_5%
1
2

PU5

EN/DEM

PC62
.1U_0402_16V7K

@ JUMP_43X118

PD13

PR104
1
2
2.2_0603_5%

BOOT

SUSP#

3
2
1

PR103
150k_0402_1%
1
2
1

<27,31>

PQ34
AO4406AL_SO8

PC134
680P_0402_50V7K
2
1

PR102
255K_0402_1%
1
2

PC133
680P_0402_50V7K
2
1

5
6
7
8

PC132
680P_0402_50V7K

PJ6
1.1VALW_B+

PR109
10K_0402_1%

Compal Secret Data

Security Classification
2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

VCCP

Size
Date:

Document Number

Rev
1.0
Sheet

Friday, December 24, 2010

1

38

of

41

PJ8

B+

JUMP_43X118

PC125
1U_0603_25V6

+5VALW

PC139
1U_0603_25V6

PC74
680P_0603_50V7K

PC76
4.7U_0603_6.3V6K

3
2
1

RT8209BGQW_WQFN14_3P5X3P5

+
2

4
PC73
4.7U_0805_10V6K

2
DL_1.5V

+1.5VP

PC72
220U_6.3V_M

5
6
7
8

PR114
4.7_1206_5%

PQ37
AO4726L_SO8

10

LGATE

PGND

PL7
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2

+5VALW

PGOOD

LX_1.5V

11

CS
VDDP

GND

6
PR115
100_0603_5%
1
2

DH_1.5V

FB

13
12

PR116
11K_0402_1%

PHASE

VFB=0.75V

VDD

PC71
0.1U_0603_25V7K
1
2

14
UGATE

VOUT

PD14
@ 1SS355_SOD323-2
BST_1.5V-1

BOOT

TON

NC

EN/DEM

15

PU6
PC70 @
.1U_0402_16V7K

+5VALW

PR113
0_0603_5%

PR112
47K_0402_1%

3
2
1

<27,31> SYSON

PQ36
AO4406AL_SO8

2
PC69
4.7U_0805_25V6-K
2
1

PR110
255K_0402_1%
1
2

PR111
0_0402_5%
1
2

PC68
4.7U_0805_25V6-K
2
1

5
6
7
8

1.5_51117_B+

PR117
10.2K_0402_1%
1
2
2

+1.5VP

2
@

PC121
@0.1U_0402_16V7K

+1.5V
1

JUMP_43X118

+1.5V

PJ10
JUMP_43X79
@

PJ9

1.5V_PGOOD <8>

PR165
100K_0402_1%

+1.5VP
PR118
10K_0402_1%

PU7

NC

3
PR119
1K_0402_1%

TP

PJ11
PC78
1U_0603_6.3V6M

+0.75VSP

2
@

+0.75VS

JUMP_43X118

+0.75VSP

10U_0603_6.3V6M

PC82
1

PC81
1

10U_0603_6.3V6M

PR121

S
PC80
.1U_0402_16V7K

PC79
0.1U_0402_16V7K
2
1

2
G

1K_0402_1%

NC

G2992F1U_SO8

PR120
0_0402_5%
1
2

VOUT

PQ38
2N7002W-T/R7_SOT323-3

<31> SUSP

VREF

PC77
4.7U_0603_6.3V6K

+3VALW

6
1

NC

VCNTL

GND

VIN

PC138
.1U_0402_16V7K

PJ12
JUMP_43X79

+3VS

VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

PC83
4.7U_0603_6.3V6K

+5VS

TP

PC84
1U_0603_6.3V6M

8
PJ13

9
+1.8VSP

+1.8VS

1
2

1
2

PC88
10U_0603_6.3V6M

Compal Secret Data

2010/09/10

Issued Date

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

JUMP_43X118

+1.8VSP

Security Classification

2
@

PC87
0.1U_0402_16V7K
2
1

PR124
1.24K_0402_1%
2
1

1
3

2
G

G2992F1U_SO8

PC86
10U_0603_6.3V6M

PQ39
2N7002W-T/R7_SOT323-3

PC85
0.1U_0402_16V7K

<31> SUSP

2
4

PR122
1K_0402_1%

LDO_1.8V_REF
PR123
31.6K_0402_1%
1
2

PU8
LDO_1.8V_IN

Title

Compal Electronics, Inc.

1.5VP/1.8VSP/0.75VSP

Size
Date:

Document Number

Rev
1.0
Sheet

Friday, December 24, 2010

1

39

of

41

<8,19>
PHASE_CPU2

22

BOOT_CPU2

21

UGATE_CPU2

1 CPU2_SNB
2

1
2

PC136
0.1U_0402_25Y5V

PC96
100U_25V_M

PC95
100U_25V_M

PC94
2200P_0402_50V7K

2
1

PC117
680P_0603_50V7K
CPU_CSP2

+CPU_CORE
C

CPU_CSN1

PR139
69.8K_0402_1%
2
PH3
100K_0603_1% TSM1A104F4361RZ

PL10
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

PR152
69.8K_0402_1%
2

1
2 CPU_SN-2
1
2
PR155
28.7K_0402_1%
1
2
PC118
0.033U_0402_16V7K

PH4
100K_0603_1% TSM1A104F4361RZ

<6>

<6>

+
2

1
2 CPU_SN-1
1
2
PR141
28.7K_0402_1%
1
2
PC104
0.033U_0402_16V7K

CPU_CSP2-1
2
PR149
4.7_1206_5%

3
2
1

PQ43
TPCA8028-H_SOP-ADVANCE8-5

<6>

PC93
0.1U_0603_25V7K
2
1

PC92
1000P_0402_50V7K
2
1

PC91
10U_0805_25V6K
2
1

PQ42
CSD17308Q3 1N SON

+5VS

PD12
1SS355_SOD323-2
PR167
1
2
2.2_0603_5%

<6>

VID1

VID0
<6>
CPU_VID0

<6>
CPU_VID1

<6>
CPU_VID2

<5>
CPU_VID3

<5,8,18>
CPU_VID4

CPU_VID5

PR137
17.8K_0402_1%
2
1

1 CPU1_SNB
2
2

4
PR146
1
2
1
2
3.3_0603_5% PC116
0.22U_0603_10V7K
1

+
2

B+
1

CPU_CSN2

LGATE_CPU2

23

24

5
3
2
1

+5VS

+CPU_B+

PC112
0.1U_0603_25V7K
1
2

PC106 10U_0603_6.3V6M

PC110
10U_0805_25V6K
2
1

25

PC109
10U_0805_25V6K
2
1

LGATE_CPU1

26

1
2 BOOT_CPU1-1
1
2
PC100
3.3_0603_5%
0.22U_0603_10V7K

27

20

19

VID2
18

VID4

VID3
17

16

VID5
15

VID6

PSI#

CPU_VID6

<6>

H_DPRSTP#

H_PSI#

1CPU_DPRSTP#
0_0402_5%
PSI#
1
0_0402_5%
VID6
2
0_0402_5%
VID5
2
0_0402_5%
VID4
2
0_0402_5%
VID3
2
0_0402_5%
VID2
2
0_0402_5%
VID1
2
0_0402_5%
VID0
2
0_0402_5%
2
PR156
2
PR157
1
PR158
1
PR159
1
PR160
1
PR161
1
PR162
1
PR163
1
PR164

11

PR154
100_0402_1%

PHASE_CPU1

PC115
2200P_0402_50V7K CPU_CSP1

VBST2
DRVH2

28

PR151
17.8K_0402_1%
2
1

VSNS

29 BOOT_CPU1

PC101
680P_0603_50V7K

PC111
1000P_0402_50V7K
2
1

LL2

PR142

CPU_CSP1-1
2
PR136
4.7_1206_5%

GNDSNS

UGATE_CPU1

PC108
10U_0805_25V6K
2
1

DRVL2

PQ41
TPCA8028-H_SOP-ADVANCE8-5
PD11
1SS355_SOD323-2
4

3
2
1

PGND

CSP2

30

PL9
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

3
2
1
2

PU9
TPS51620RHAR_QFN40_6X6

CSN2

PQ40
CSD17308Q3 1N SON

32

31
PGOOD

DPRSLPVR

34

35

33
CLK_EN#

VR_ON

PWRMON

37

36
TRIPSEL

38

TONSEL

OSRSEL

40

39
ISLEW

V5FILT

V5IN

PR150
20K_0402_1%

1
2
+CPU_CORE

VCCSENSE

DRVL1

CSN1

<6>

1
2
VSSSENSE

CSP1

CPU_THERM
10 THERM

PR153
100_0402_1%

LL1

14

VBST

13

DRVH1

PL8
HCB4532KF-800T90_1812
1
2

+5VS

GND

DPRSTP#

PC90
10U_0805_25V6K
2
1

5
1
PR132
CPU_DPRSLPVR

PR166
1
2
2.2_0603_5%

VREF

VR_TT#

CPU_VSNS

DROOP

12

GND

41
1
2

2 CPU_CSP1-2
33P_0402_50V8K
2 CPU_CSN1-1
33P_0402_50V8K
2 CPU_CSN2-1
33P_0402_50V8K
2 CPU_CSP2-2
33P_0402_50V8K
CPU_GNDSNS

PR147
0_0402_5%
2
1

CPU_CSP2 2
PR145

PC113
100P_0402_50V8J
1
470_0402_1%

1
PC103
1
PC105
1
PC107
1
PC114

CPU_CSN1 2
PR143
CPU_CSN2 2
PR144

PC102
100P_0402_50V8J
1
470_0402_1%
1
470_0402_1%

PR148
0_0402_5%
1

1
470_0402_1%

CPU_CSP1 2
PR140

CPU_VREF
1
2
PR138
4.75K_0402_1%
1
2 CPU_DROOP 1
PC98
68P_0402_50V8J
1
2 CPU_VREF
2
PC99
0.22U_0603_10V7K
3

PC89
10U_0805_25V6K
2
1

2
0_0402_5%

1
0_0402_5%
2
PR131
CPU_VR_ON

CPU_V5FILT

+CPU_B+

CPU_TONSEL
2
1 CPU_VREF
PR134
0_0402_5%
CPU_TRIPSEL
2
1
PR135
0_0402_5%

1
124K_0402_1%
1

CPU_ISLEW
2
PR133
CPU_OSRSEL

2
PC97
1U_0603_10V6K

<27>

VR_ON

+5VS

PR129
@ 0_0402_5%
2
1
PR130
0_0402_5%
2
1

+3VS

DPRSLPVR

1
2
PR128
@ 0_0402_5%

CPU_CLK_EN#

VGATE

<19> CLK_ENABLE#

2
1
PR127
10K_0402_1%

2
1
PR126
1.91K_0402_1% @

<8,19>
D

+3VS

VR_ON
2
1
PR125
1.91K_0402_1%

<27>

2010/09/10

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/19

Deciphered Date

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Size Document Number

Custom
Date:

Rev
1.0

Friday, December 24, 2010

Sheet
1

40

of

41

V ersion Change L ist ( P. I. R . L ist ) for Pow er Circuit

P age#

Title

D ate

R equest
O w ner

Issue D escription

Solution D escription

3

$GGFDSDFLWLHVIRU(0,UHTXHVW



(0,

(0,WHVWIDLO

$GG3&3&3&3&3&3&

3

&KDQJHUHVLVWDQFHIRU(0,UHTXHVW



(0,

(0,WHVWIDLO

&KDQJH35IURPRKPWRRKP

3

$GGRQHFDSDFLWRUIRUSUHYHQW
LQUXVKFXUUHQWWRRODUJH



3:5

,IWKHUHLVQ
WDGGFDSDFLW\
WKH026RI34KDYHGDPJHGULVN

$GG3&ZKLFKYDOXHLV3)

3

$GGRQHWUDQVLVWRUIRULPSURYH
GHVLJQPDUJLQ



3:5

,IWKHUHLVQ
WDGGWUDQVLWRU
WKHGHVLJQPDUJLQRI34LVQRWHQRXJK

$GG34

3

&KDQJHUHVLVWDQFHIRU&38ORDGOLQH
ILQHWXQLQJ



3:5

)RUPHHWWKHORDGOLQHRILQWHOVSHF

&KDQJH35IURPNWRN

3

$GGRQHFDSDFLWRUIRULPSURYH
ULSSOHFXUUHQW



3:5

)RUPHHWWKHULSSOHFXUUHQWVSHFRI&RPSDO

$GG3&

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/09/10

2010/08/19

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Power PIR
Size Document Number
Custom
Date:

Rev
1.0

LA7011P

Friday, December 24, 2010

Sheet
1

41

of

41