ASCEND Semiconductor 4Mx4 EDO Data sheet

Rev.1

Page 1

AD 40 4M 4 2 V S A 5
Ascend Semiconductor

EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM

: : : : : :

40 41 42 43 46 48

Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 4: x4 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K 8 : 8K 2 : 2K 6 :16K 4 : 4K

Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) EDO : -5 (50 ns) -6 (60 ns)

Revision A : 1st B : 2nd C : 3rd D :4th

Interface V: 3.3V R: 2.5V

Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP S: SOJ

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Description

The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features

Single 3.3V( 10 %) only power supply High speed tRAC acess time: 50/60ns Low power dissipation - Active mode : 432/396 mW (Mas)

- Standby mode: 0.54 mW (Mas) Extended - data - out(EDO) page mode access I/O level: CMOS level (Vcc = 3.3V) 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version) 4 refresh modesh: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version)

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Pin Configuration 26/24-PIN 300mil Plastic SOJ

26/24-PIN 300mil Plastic TSOP (ll)

VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC

1 2 3 4 5 6 8 9 10 11 12 13

26 25 24 23 22 21 19 18 17 16 15 14

VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS

VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC

1 2 3 4 5 6 8 9 10 11 12 13

26 25 24 23 22 21 19 18 17 16 15 14

VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS

AD404M42VT

AD404M42VS

Pin Description Pin Name A0-A10 Function Address inputs - Row address - Column address - Refresh address Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+ 3.3V) Ground A0-A10 A0-A10 A0-A10

DQ1~DQ4 RAS CAS WE OE Vcc Vss

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Block Diagram

WE

CAS

CONTROL LOGIC

DATA-IN BUFFER DQ1 . . DQ4

NO. 2 CLOCK GENERATOR

DATA-OUT BUFFER OE

COLUMN ADDRESS BUFFERS (11) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

ROW DECODER

COLUMN DECODER

REFRESH CONTROLLER

2048

SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 2048x4

A10

ROW ADDRESS BUFFERS (11)

2048x2048x4 MEMORY ARRAY

2048

RAS

NO. 1 CLOCK GENERATOR

Vcc Vss

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TRUTH TABLE
ADDRESSES FUNCTION RAS STANDBY READ WRITE: (EARLY WRITE ) READ WRITE EDO-PAGEMODE READ 1st Cycle 2nd Cycle EDO-PAGE 1st Cycle MODE WRITE 2nd Cycle EDOPAGE-MODE READ-WRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE RAS-ONLY REFRESH CBR REFRESH H L L L L L L L L L LHL LHL L HL CAS HX L L L HL HL HL HL HL HL L L H L WE X H L HL H H L L HL HL H L X H OE X L X LH L L X X ROW X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X COL X COL COL COL COL COL COL COL COL COL COL COL n/a X High-Z Data-Out Data-ln Data-Out,Data-ln Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z 1 DQS Notes

LH LH
L X X X

Notes: 1. EARLY WRITE only.

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Absolute Maximum Ratings

Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature

Symbol VT VCC IOUT PD TOPT TSTG

Value -0.5 to + 4.6 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125

Unit V V mA W
C C

Recommended DC Operating Conditions

Parameter/Condition

Symbol Min

3.3 Volt Version Typ 3.3 Max 3.6

Unit

Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs

VCC VIH VIL

3.0 2.0 -0.3

V V V

- VCC + 0.3 0.8

Capacitance Ta = 25C, VCC = 3.3V 10 %, f = 1MHz

Parameter Input capacitance (Address) Input capacitance (RAS, CAS, OE, WE) Output capacitance (Data-in, Data-out)

Symbol CI1 CI2 CI/O

Typ -

Max 5 7 7

Unit pF pF pF

Note 1 1 1, 2

Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout.

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DC Characteristics : (Ta = 0 to 70C , VCC = + 3.3V 10 %, VSS = 0V)

Parameter

Symbol

Test Conditions -5 Min

AD404M42V -6 Max 120 Min Max 110

Unit

Notes

Operating current

ICC1

RAS cycling CAS, cycling tRC = min LVTTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V C C -0.2V Dout = High-Z

mA

1, 2

Low power S-version

ICC2

0.5

0.5

mA

0.15

0.15

mA

Standby Current

Standard power version

LVTTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V C C -0.2V Dout = High-Z

mA

0.5

0.5

mA

RAS- only refresh current EDO page mode current CAS- before- RAS refresh current Self- refresh current (S-Version)

ICC3 ICC4 ICC5 ICC8

RAS cycling, CAS = VIH tRC = min tPC = min tRC = min RAS, CAS cycling t RASS 100 s

120 90 120 550

110 80 110 550

mA mA mA A

1, 2 1, 3 1, 2

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DC Characteristics : (Ta = 0 to 70C, VCC= +3.3V 10 %, VSS= 0V) AD404M42V -5 Parameter Input leakage current Output leakage current Symbol ILI ILO VOH VOL Test Conditions 0V Vin V C C + 0.3V 0V Vout V CC + 0.3V Dout = Disable Output high Voltage Output low voltage IOH = -2mA IOL = +2mA 2.4 0.4 2.4 0.4 V V Min -5 -5 Max 5 5 Min -5 -5 -6 Max 5 5 A A Unit Notes

Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For I CC4, address can be changed once or less within one EDO page mode cycle time.

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AC Characteristics (T a = 0 to + 70C, Vcc = 3.3V 10 %, Vss = 0V) *1, *2, *3, *4

Test conditions Output load: one TTL Load and 100pF (VCC = 3.3V 10 %) Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VCC = 3.3V 10 %) Output timing reference levels: VOH = 2.0V, VOL = 0.8V

Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) AD404M42V -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time in normal mode RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period Refresh period (S- Version) CAS to output in Low- Z CAS delay time from Din OE delay time from Din Symbol tRC tRP tCPN tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tREF tCLZ tDZC tDZO Min 84 30 10 50 8 0 8 0 8 12 10 25 8 38 5 12 1 0 0 0 Max 10000 10000 37 25 50 32 128 Min 104 40 10 60 10 0 10 0 10 14 12 30 10 40 5 15 1 0 0 0 -6 Max 10000 10000 45 30 50 32 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns 11 10 8 9 7 5 6 Unit Notes

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Read Cycle AD404M42V -5 Parameter Access time from RAS Access time from CAS Access time from column address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ Min 0 0 0 0 0 Max 50 14 25 12 12 12 Min 0 0 0 0 0 -6 Max 60 15 30 15 15 15 ns ns ns ns ns ns ns ns ns 7 10, 16 16 17 17 12 13, 14 14, 15 Unit Notes

Write Cycle AD404M42V -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time WE to Data-in delay Symbol tWCS tWCH tWP tRWL tCWL tDS tDH tWED Min 0 8 8 13 8 0 8 10 Max Min 0 10 10 15 10 0 10 10 -6 Max ns ns ns ns ns ns ns ns 19 19 7, 18 Unit Notes

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Read- Modify- Write Cycle AD404M42V -5 Parameter Read-modify- write cycle time RAS to WE delay time CAS to WE dealy time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 108 64 26 39 8 Max Min 133 77 32 47 10 -6 Max ns ns ns ns ns 18 18 18 Unit Notes

Refresh Cycle

AD404M42V -5 Parameter CAS setup time (CBR refresh) CAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (CBR self refresh) WE setup time WE hold time Symbol tCSR tCHR tRPC tRASS tRPS tCHS tWSR tWHR Min 5 8 5 100 90 -50 0 10 Max Min 5 10 5 100 110 -50 0 10 -6 Max Unit ns ns ns s ns ns ns ns 10 7 Notes

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EDO Page Mode Cycle AD404M42V -5 Parameter EDO page mode cycle time EDO page mode CAS precharge time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge OE high hold time from CAS high OE high pulse width Data output hold time after CAS low Output disable delay from WE WE pulse width for output disable when CAS high Symbol tPC tCP tRASP tCPA tCPRH tOEHC tOEP tCOH tWHZ tWPZ Min 20 10 50 30 5 10 5 3 7 Max 105 30 10 Min 25 10 60 35 5 10 5 3 7 -6 Max 105 35 10 Unit ns ns ns ns ns ns ns ns ns ns 20 10, 14 Notes

EDO Page Mode Read Modify Write Cycle AD404M42V -5 Parameter EDO page mode read- modify- write cycle CAS precharge to WE delay time EDO page mode read- modify- write cycle time Symbol tCPW tPRWC Min 45 56 Max Min 55 68 -6 Max Unit ns ns Notes 10

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Notes : 1. AC measurements assume t T = 2ns. 2. An initial pause of 100 s is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+t RWL(min)+tT in read-modify-write cycle. 6. tCAS (min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 7. tASC(min), tRCS (min), tWCS(min), and tRPC are determined by the falling edge of CAS . 8. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 11. V IH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 12. Assumes that t RCD

tRCD(max) and tRAD

tRAD(max). If t RCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that tRCD

t RCD (max) and tRAD t RAD (max). tRAD (max).

14. Access time is determined by the maximum of tAA , tCAC, tCPA. 15. Assumes that t RCD tRCD (max) and t RAD

16. Either tRCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). t OFF is determined by the later rising edge of RAS or CAS. 18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tCWD

tRWD (min),

t CWD (min),

t AWD

t AWD (min) and

tCPW

tCPW (min), the cycle is a read-modify-write and

the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in EDO page mode cycles.

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Timing Waveforms Read Cycle

t RC t RAS t RP

RAS
t CRP t CSH t RCD t T t RSH t CAS t CPN

CAS

t RAD

t RAL

t ASR

t RAH Row

t ASC

t CAH Column t RRH

ADDRESS

t RCS

t RCH

WE

OE
t OEA t CAC t AA t RAC t OEZ t OFF t OFF

DQ1~DQ4
t CLZ Note : = dont care = Invalid Dout

D OUT

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Early Write Cycle

t RC t RAS t RP

RAS

t CSH t RCD t T t RSH

t CRP

t CPN t CAS

CAS

t RAD t ASR t RAH Row t ASC t CAH

t RAL

ADDRESS

Column

t RAL

t WCS

t WCH

WE

t DS

t DH

DQ1~DQ4

DIN

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 Delayed Write Cycle

t RC t RAS t RP

RAS

t CSH t RCD t T t RSH t CAS

t CRP

t CPN

CAS

t ASR

t RAH

t ASC

t CAH

ADDRESS

Row

Column

t CWL t RCS t RWL t WP

WE

t OED

t OEH

OE

t DS

t DS

t DH

DQ1~DQ4

OPEN

DIN

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 Read - Modify - Write Cycle

t RWC t RAS t RP

RAS

t T t RCD t CAS t CRP t CPN

CAS

t RAD t ASR t RAH t ASC t CAH

ADDRESS

Row

Column t RCS t CWD t AWD t RWD t CWL t RWL t WP

WE

t DZC t DS

t DH

DQ1~DQ4

OPEN

DIN

t DZO

t OED

t OEH

OE
t OEA t CAC t AA t OEZ

t RAC

DQ1~DQ4

DOUT

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 EDO Page Mode Read Cycle

t RASP t CPRH t RP

RAS
t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN

CAS

t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC

t RAL t CAH

ADDRESS

Row

Column 1

Column 2

Column N

Row

t RCS

t RRH t RCH

WE

WE
t OEHC t OEA t OEP t OEA

OE

OE
t RAC t AA t CPA t AA t CPA t AA t OEZ t CAC t CAC t COH t CAC t OFF t OEZ

t OFF

DQ1~DQ4

DOUT 1 DOUT 2

DOUT N

OPEN

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 EDO Page Mode Early Write Cycle

RASP

t RP

RAS

tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS

t CRP t CPN

CAS

t ASR

t RAH

t ASC

t CAH

t ASC

t CAH

t ASC

t CAH

ADDRESS

Row

Column 1

Column 2

Column N

t WCS

t WCH

t WCS

t WCH

t WCS

t WCH

WE

WE

t DS

t DH

t DS

t DH

t DS

t DH

DQ1~DQ4

DIN 1

DIN 2

DIN N

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 EDO Page Mode Read-Early-Write Cycle

t RASP t CPRH t RP

RAS
t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN

CAS
t CSH t RAD t ASR t RAH t ASC t RAH t ASC t CAH t ASC t CAL t RAL t CAH

ADDRESS

Row

Column 1

Column 2

Column N

Row

t RCS

t RCH

t WCS t WCH

WE

WE

t OEA t WED

OE

OE
t RAC t AA t CPA t AA t WHZ t CAC t COH t CAC t DS
Data Doutput 2 Data Input N

t DH

DQ1~DQ4

OPEN

Data Doutput 1

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 EDO Page Mode Read-Modify-Write Cycle

t RASP tCPRH t RP

RAS
t T t RCD t CAS t CP

t PRWC t CAS t CP t CAS

t CRP

CAS

t RAD t ASR t RAH t ASC t CAH t ASC t CAH

t RAL t ASC t CAH

ADDRESS

Row

Column 1 Column 1 t RWD t AWD t CWD t CWL

Column 2 t CPW t AWD t CWD t CWL

Column N t CWL t CPW t AWD t CWD

t RWL

t RCS

t RCS

WE

WE
t RCS t WP t DS t DZC t DH t DZC t WP t DZC t DS t DH t WP t DS t DH OPEN

DQ1~DQ4

OPEN

DIN 1

OPEN

DIN 2

DIN N

t DZO t DZO t OED t OEH t OED t OEH

t DZO

t OED

t OEH

OE
t OEA t CAC t RAC t AA t OEZ t OEA t CAC t AA t CPA t OEZ t CAC t AA t CPA t OEZ t OEA

DQ1~DQ4
DOUT 1 DOUT

DOUT

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 Read Cycle with WE Controlled Disable

RAS

t CSH t RCD t T t CAS

CAS

t RAD t ASR t RAH t ASC t CAH

ADDRESS

Row

Column

t RCS

t RCH

t WPZ

WE
t WHZ

OE

t DS tOEA tCAC t AA t RAC tOEZ

DQ1~DQ4
tCLZ

DOUT

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RAS-Only Refresh Cycle

t RC t RAS t RP

RAS

tT t CRP tRPC tCRP

CAS

tASR

tRAH

ADDRESS

ROW

tOFF OPEN

DQ1~DQ4

CAS-Before-RAS Refresh Cycle

tRC tRP tRAS tRP t RAS

tRC t RP

RAS
tRPC

tT t CSR t CHR

tRPC tCSR t CHR

tCRP

CAS
tWSR tWHR tWSR tWHR

WE

tOFF OPEN

DQ1~DQ4

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CBR Self-Refesh Cycle

t RASS

t RPS

RAS

t RPC t CSR tCHS

CAS

tOFF

High lmpedance

DQ1~DQ4

tWSR

tWHR

WE

OPEN

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 Hidden Refresh Cycle

t RC tRAS
(READ)

t RC t RP tRAS
(REFRESH)

t RC t RP tRAS
(REFRESH)

t RP

RAS

tT

t CHR t RSH t RCD tCAS

tCRP

CAS

t RAD t ASR t RAH tASC

t RAL tCAH

ADDRESS

ROW

COlumn

tRRH t RCS tRCH

WE

OE
t OEA t CAC t AA t RAC t OEZ t OFF t OFF

DQ1~DQ4

D OUT

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Ordering information Part Number AD404M42VSA-5 AD404M42VSA-6 AD404M42VTA-5 AD404M42VTA-6 AD404M42VSA-5 AD

40 4M4 2 V

Access time 50 ns 60 ns 50 ns 60 ns

Package

300mil 26/24-Pin Plastic SOJ TSOP II

Ascend Memory Product Device Type Density and Organization Refresh Rate, 2: 2K Refresh T: 5V, V: 3.3V Package Type (S : SOJ, T : TSOP II) Version
Speed (5: 50 ns, 6: 60 ns)

S A
5

Packaging information
300 mil, 26/24-Pin Plastic SOJ

D DIM A A1 A2 b b1 b2 c c1 D E E1 E2 e R1 MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. 3.25 3.51 3.76 0.128 0.138 0.148 2.08 ----0.082 ----2.54 REF. 0.100 REF. 0.41 0.41 0.66 0.18 0.18 17.02 --0.46 --0.51 0.48 0.81 0.016 0.016 0.026 0.007 0.007 0.670 --0.018 --0.020 0.019 0.032 1 6 8 13 b 26 21 19 14 b1

c1 c E1 E BASE METAL WITH PLATING

--0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02

--0.012 0.011 --0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040

SECTION B-B

C L

A2

0.025" MIN. A A1

B B E2

NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.

e b2 b 0.007"M 4-e 0.004"

RAD R1 SEATING PLANE

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 300 mil, 26/24-Pin TSOP II

DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1

MILLIMETERS MIN. --0.05 0.95 0.30 0.30 0.12 0.12 17.01 NOM. ----1.00 --0.40 --0.15 17.14 0.95 REF. 1.27 BASIC 9.02 7.49 0.40 0.12 0.12 9.22 7.62 0.50 ----9.42 7.75 0.60 0.25 --0.355 0.295 0.016 0.005 0.005 MAX. 1.20 0.15 1.05 0.52 0.45 0.21 0.16 17.27 MIN. --0.002 0.037 0.012 0.012 0.005 0.005 0.670

INCHES NOM. ----0.039 --0.016 --0.006 0.675 0.050 BASIC 0.363 0.300 0.020 ----0.371 0.305 0.024 0.010 --(ZD) A MAX. 0.047 0.006 0.041 0.020 0.018 0.008 (0.006) 0.680 1 6 D 8 13 b b1 E1 E A1 26 21 19 14 A2

RAD R1 RAD R B B c

DETAIL A

0 ~5

0.0374 BASIC

SECTION B-B
c

c1

BASE METAL WITH PLATING DETAIL A

NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.

4-1.27 REF. b 0.200(0.008")

M

e SEATING PLANE 0.100(0.004")

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