Compal Confidential: P1VE6 LA7071P Schematics Document

A
ZZZ0
ZZZ1
ZZZ2
ZZZ3
ZZZ4
ZZZ5
PCB
LA-7071P
LS-7071P
LS-7074P
LS-7075P
LA-7076P
M/B
DAZ@
M/B
DA@
USB IO/B
DA@
HDD/B
DA@
LED/B
DA@
TP/B
DA@
PCB
DAZ0I200101
MB
USB IO/B
HDD/B
LED/B
TP/B
DA60000KP10
DA60000KQ10
DA400011R10
DA400011T10
DA400013910
Compal Confidential
P1VE6 LA7071P Schematics Document
AMD Ontario Processor with DDRIII + Hudson M1

11.6" M/B
2011-03-17
Rev : 1.0
2010/11/09
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/11/09
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Cover Page
Size Document Number
Custom
Rev
1.0
P1VE6 Schematics
Date:
Thursday, March 17, 2011
Sheet
E
of
37
Compal Confidential
Brazos Platform
Model Name : P1VE6

File Name : LA-7071P
HDMI
RGB
LVDS
AMD
Ontario FT1
Memory Bus (DDRIII)
Dual Channel
APU
204 Pin DDRIII SO-DIMM x2
1.5V DDRIII 800/1066
BANK 0, 1, 2, 3
6.4G/8.5G
BGA 413-Ball
19mm X 19mm
Page 7 , 8
100M/133M
Page 4,5,6
HDMI Conn.
D-Sub Conn.
Page 10
Page 11
LVDS Conn.
UMI x4
Gen.1
Page 9
USB Conn.x2
(Left Side)
Port 0 , 1
2.5GT/s
per Lane
(Right Side)
Port 2
IO/B
Fan Circuit
PWM
Page 25
Camera
Bluetooth
Port 5
Port 7
Page 9
Card Reader
RTS 5138
Port 6
Page 20
Page 19
2
Page 27
PCI-Express X3
100MHz
Port 1
PCIE Gen1 2.5GT/S

Port 3
WWAN
WLAN
JMINI1
JMINI2
Media processor
Port 1
USB Conn.x1
Wireless Card
Port 3
Page 20
Page 21
USB
AMD
Hudson M1
HD Audio
FCH
Port 2
LAN(10/100)
3.3V 48MHz
SATA
3.3V 24MHz
Gen1 1.5GT/S ,Gen2 3GT/S
3G Card
100MHz
BGA 605-Ball
23mm X 23mm
Port 3, 9
Page 20
Page 12 ~ 16
AR8158
SIM Card
HDD
Port 2
Page 18
(2.5")
Port 0
LPC
Port 4
Page 20
Page 22
33MHz
3
RJ-45
WLAN
Page 18
Port 8
ENE KB930
Page 21
Small Board
Page 26
IO/B
HDD/B
LS-7071P
HDA Codec+AMP
LS-7074P
CX20584
Page 17
RTC Ckt.
LED/B
Page 12
TP BTN/B
LS-7072P
BIOS ROM
LS-7073P
HP Jack x1
MIC Jack x1
2MB
Power Button
Page 27
IO/B
Page 23
Page 28
2010/11/09
Issued Date
Compal Secret Data
DC/DC Interface Ckt.
2012/11/09
Deciphered Date
B
Title
Block Diagrams
Size
B
Date:
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
E
of
37
Voltage Rails
Power Plane
Description
S1
VIN
Adapter power supply (19V)
N/A
B+
AC or battery power rail for power circuit.
N/A
S5
FCH Hudson-M1
USB Port List
N/A
N/A
USB1.1
N/A
N/A
S3
+APU_CORE
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
+APU_CORE_NB
1.0V switched power rail
ON
OFF
OFF
+1.5V
1.5V power rail for CPU VDDIO and DDRIII
ON
ON
OFF
+0.75VS
0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS
1.05V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+1.1VS
1.1VS switched power rail
ON
OFF
OFF
+1.8VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+1.1VALW
1.1V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+1.5VS
1.5VS switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCBATT
RTC power
ON
ON
ON
EC SM Bus1 address
Address
HEX
Device
Address
HEX
Smart Battery
0001-011xb
16H
SB-TSI
1001-100xb
98H
SM Bus Controller 0
Device
SM Bus Controller 1
Device
NC
(FCH_SMB0)
Address
HEX
1001-000xb
90
PCIE1
PCIE2
NC
HDD
SATA1
NC
SATA2
PCIE3
NC
SATA3
NC
Port0
Left conn
PCIE0
NC
SATA4
NC
Port1
Left conn
PCIE1
WWAN
SATA5
NC
Port2
Right conn
PCIE2
LAN
Port3
WWAN
PCIE3
WLAN
Port4
SIM
Port5
USB Camera
Port6
CardReader
Port7
BT
Port8
WiMax
Port9
WWAN
Port10
NC
Port11
NC
Port12
NC
Port13
NC
Board ID
H_THERMTRIP# (FCH_ALERT#)
DDR DIMM1 (FCH_SMB0)
NC
Port1
Vcc
Ra
HEX
APU SIC/SID (FCH_SMB3)
Port0
SATA0
Board ID / SKU ID Table for AD channel
(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
Address
PCIE0
FCH Hudson-M1
SATA Port List
EC SM Bus2 address
Device
Brazos
PCIE Port List
USB2.0
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
APU
FCH
0
1
2
3
4
5
6
7
+3VALW
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
PCB Revision
0.1
0.2
SMBUS Control Table

Source
BATT
EC_SMB_CK1
EC_SMB_DA1
KB930
EC_SMB_CK2
EC_SMB_DA2
KB930
HDMI_DATA
HDMI_CLK
APU FT1
EDID_DATA
EDID_CLK
APU FT1
FCH_SMDAT0
FCH_SMCLK0
FCH M1
BOM Structure
HDMI@ :
BT@
:
CONN@ :
45@
:
3G@
:
N3G@ :
CMBS@ :
NCMBS@:
HDMI function
BT function
Connetors
45 Level
3G function
None 3G function
Combo Jack POPO noise Solution
None Combo Jack POPO noise Solution
DIMM
MINI Card LCD DDC ROM
APU
V
V
V
4
2010/11/09
Issued Date
V
Compal Secret Data
2012/11/09
Deciphered Date
A
HDMI DDC ROM
Title
Notes List
Size
B
Date:
Document Number
P1VE6 Schematics
Sheet
E
of
37
Rev
1.0
APU C50 P/N change to SA00004KD50

Tock 2010/12/30
R9
SA00004KD50
mount
1
1
1
1
2
2
2
2
HDMI_DATA
HDMI_CLK
APU_PROCHOT#
APU_ALERT#_R
APU_SIC
APU_SID
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
C435
100P_0402_50V8J
Power Circuit
<26> EC_PROCHOT#
2 0_0402_5% APU_PROCHOT#
Power Circuit
2 0_0402_5%
Power Circuit
TDP1_TXP2
TDP1_TXN2
C4
C5
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_CLKP_C
HDMI_CLKN_C
A10
B10
TDP1_TXP3
TDP1_TXN3
<9> LVDS_A2
<9> LVDS_A2#
B5
A5
LTDP0_TXP0
LTDP0_TXN0
<9> LVDS_A1
<9> LVDS_A1#
D6
C6
LTDP0_TXP1
LTDP0_TXN1
<9> LVDS_A0
<9> LVDS_A0#
A6
B6
<9> LVDS_ACLK
<9> LVDS_ACLK#
D8
C8
D2
D1
<36> APU_SVC
<36> APU_SVD
APU_SIC
APU_SID
CLKIN_H
CLKIN_L
DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD
P3
P4
SIC
SID
APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R T2
R24 1
@
2 0_0402_5%
R26 1
@
2 0_0402_5%
APU_TDI
N2
APU_TDO
need to pull-down
N1
APU_TCK
P1
APU_TMS
P2
APU_TRST#
M4
APU_DBRDY
M3
Close to APU
APU_DBREQ#
M1
F4
G1
F3
<36> APU_VDDNB_RUN_FB_H
<36> APU_VDD0_RUN_FB_H
LTDP0_TXP3
LTDP0_TXN3
J1
J2
T3
T4
<12> LDT_RST#
<12> APU_PWRGD
LTDP0_TXP2
LTDP0_TXN2
<36> APU_VDD0_RUN_FB_L
R379 1
2 0_0402_5%
F1
<36> APU_VDDNB_RUN_FB_L
R380 1
2 0_0402_5%
B4
W11
V5
DP MISC
D10
C10
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
R1
H3
DP_BLON
DP_DIGON
DP_VARY_BL
G2
H2
H1
TDP1_AUXP
TDP1_AUXN
B2
C2
TDP1_HPD
C1
LTDP0_AUXP
LTDP0_AUXN
A3
B3
EDID_CLK
EDID_DATA
LTDP0_HPD
D3
LTDP0_HPD
DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA
DAC_ZVSS
RESET_L
PWROK
DP_ZVSS
DP_ZVSS
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37
VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE
C12
D13
A12
B12
A13
B13
APU_ENBKL <26>
APU_ENVDD <9>
APU_BLPWM <9>
HDMI_CLK
HDMI_DATA
8/25 Pull-up 100k(@ R352) to +3VS

on LTDP0_HPD for eDP
HDMI_DET <10>
R12
EDID_CLK <9>
EDID_DATA <9>
R9
R18
CRT_DDC_CLK <11>
CRT_DDC_DATA <11>
D12 DAC_ZVSS
R19
2 499_0402_1%
TEST15
R20
2 1K_0402_5%
TEST18
TEST19
TEST25_H
TEST_25_L
R21
R22
R25
1
1
1
2 1K_0402_5%
2 1K_0402_5%
2 510_0402_1%
10/01 Remove T1,T3~T7,T11,T12,T31,T32
TEST31
TEST33_H
TEST33_L
TEST35
TEST36
TEST37
PAD T8
C9 1
C10 1
R30
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
1
PAD T13 R386 1
R28
R29
2 51_0402_1%
2 51_0402_1%
1
1
2 1K_0402_5%
2 1K_0402_5%
+1.8VS
9/9 Add R386 (1k@) to +1.8VS on TEST35
VSS_SENSE
TEST38
DMAACTIVE_L
RSVD_1
RSVD_2
RSVD_3
9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)
K3
T1
ALLOW_STOP# <12>
R31
2 1K_0402_5%
+1.8VS
ALLOW_STOP#
@
8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P
2
1
DMIC_CLK <9,17>
CRT_HSYNC <11>
CRT_VSYNC <11>
F2
D4
C438
100P_0402_50V8J
Reserve C438 for ALLOW_STOP#

Michael 2010/11/18
Q1
1
H_THERMTRIP# <13>
2 0_0402_5% DMIC_CLK
Reserve R389 for eDP function

Tock 2010/12/30
APU_THERMTRIP#
+3VS
2 100K_0402_5%
R389 1
DAC_BLU <11>
2 150_0402_1%
2 100K_0402_5%
DAC_GRN <11>
2 150_0402_1%
1
eDP@
DAC_RED <11>
2 150_0402_1%
R15
R352 1
1K_0402_5%
B
HDMI_CLK <10>
HDMI_DATA <10>
E1
E2
R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5
eDP
2 150_0402_1%
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L
R32
10K_0402_5%
<BOM Structure>
HDMI_TX0P_C
HDMI_TX0N_C
T14PAD
+3VS
R33
.1U_0402_16V7K
.1U_0402_16V7K
DISP_CLK
DISP_CLK#
Add C429 for APU_PROCHOT#

Michael 2010/11/18
2
2
<12>
<12>
<14> APU_ALERT#_FCH
<26> APU_ALERT#_EC
R27
1
1
V2
V1
Connection to EC, FCH input
R23
C7
C8
APU_CLK
APU_CLK#
C434
100P_0402_50V8J
C429
100P_0402_50V8J
<12> FCH_PROCHOT#
TDP1_TXP1
TDP1_TXN1
<12>
<12>
9/15 Change R24 from mount to @
B9
A9
9/9 Change R24 from @ to mount R26 from mount to @
APU_PROCHOT#
HDMI_TX1P_C
HDMI_TX1N_C
LDT_RST#
APU_SIC
@
.1U_0402_16V7K
.1U_0402_16V7K
C432
100P_0402_50V8J
10/05 Add 100p(C405) on LDT_RST#
2
2
APU_SID
2 100P_0402_50V8J
1
1
Reserve C432, C433, C434, C435

Michael 2010/11/18
Change R10, R11 to RP1

Michael 2010/12/23
C405 1
C2
C3
TDP1_TXP0
TDP1_TXN0
VGA DAC
2 10K_0402_5%
2 10K_0402_5%
A8
B8
TEST
R13
R14
R16
R17
1
1
HDMI_TX2P_C
HDMI_TX2N_C
DISPLAYPORT 0
R10
R11
<10> HDMI_CLKP
<10> HDMI_CLKN
.1U_0402_16V7K
.1U_0402_16V7K
CLK
APU_SVC
@
+3VS
<10> HDMI_TX1P
<10> HDMI_TX1N
<10> HDMI_TX0P
<10> HDMI_TX0N
TEST_25_L
TEST36
2 510_0402_1%
2 1K_0402_5%
1
1
C433
100P_0402_50V8J
2
2
SER
R8
R6
APU_SVC
APU_SVD
2 1K_0402_5%
2 1K_0402_5%
1
1
1
1
CTRL
R3
R4
C1
C6
JTAG
<10> HDMI_TX2P
<10> HDMI_TX2N
DISPLAYPORT 1
APU_SVD
@
LVDS
mount
U1B
+1.8VS
Display
R352
MMBT3904_NL_SOT23-3
1
R34
+1.8VS
2
0_0402_5%
9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32
If FCH internal pull-up disabled, level-shifter could be deleted.

Need BIOS to disable internal pull-up!!
+3VS
9/20 Delete R41~R43
AMD Debug
2N7002DW-T/R7
Vgs(th): min 1.0V
Typ 1.6V
Max 2.0V
R39
10K_0402_5%
@
R37
1 1K_0402_5%
APU_TDI
R38
1 1K_0402_5%
APU_TMS
R36
1 1K_0402_5%
APU_TCK
R35
1 1K_0402_5%
APU_PWRGD
R5
1 300_0402_5%
LDT_RST#
R7
1 300_0402_5%
R2
1 300_0402_5%
APU_PWRGD
1
If Q8 or R429, R432 implemented,

EC side pull-up need to be mounted
C421
100P_0402_50V8J
@
T29PAD
APU_TRST#
APU_TDO
DMN66D0LDW-7_SOT363-6
APU_SID
6
D
EC_SMB_DA
Q2A
1
R49
1
R47
1
R48
2
0_0402_5%
2
0_0402_5%
FCH_SID
EC_SMB_DA2
FCH_SID <13>
EC_SMB_DA2 <26>
T30PAD
Reserve C421 for APU_PWRGD

Michael 2010/11/18
T0 FCH
TO EC
APU_DBRDY
APU_DBREQ#
2
0_0402_5%
8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
4
APU_SIC
Q2B
1
R52
5
EC_SMB_CK
1
R50
1
R51
FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%
FCH_SIC <13>
EC_SMB_CK2 <26>
T0 FCH
TO EC
Compal Secret Data
2010/11/09
Issued Date
2012/11/09
Deciphered Date

FT1 CTRL/DP/CRT
2
0_0402_5%
Title

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
of
37
DDR_A_D[0..63]
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DM[0..7]
U1E
R18
T18
F16
<7,8> DDR_A_BS0
<7,8> DDR_A_BS1
<7,8> DDR_A_BS2
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
<7,8>
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
<7>
<7>
<7>
<7>
<8>
<8>
<8>
<8>
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3
<7>
<7>
<8>
<8>
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3
M17
M16
M19
M18
N18
N19
L18
L17
DDR_CKE0
DDR_CKE1
<7,8> DDR_CKE0
<7,8> DDR_CKE1
D15
B19
D21
H22
P23
V23
AB20
AA16
DDR_RST#
DDR_EVENT#
<7,8> DDR_RST#
<7,8> DDR_EVENT#
<7>
<7>
<8>
<8>
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
F15
E15
DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1
W19
V15
U19
W15
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
T17
W16
U17
V16
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
<7,8> DDR_A_RAS#
<7,8> DDR_A_CAS#
<7,8> DDR_A_WE#
L23
N17
U18
V19
V17
M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
DDR SYSTEM MEMORY
R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1
B14
A15
A17
D18
A14
C14
C16
D16
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
C18
A19
B21
D20
A18
B18
A21
C20
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
C23
D23
F23
F22
C22
D22
F20
F21
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
H21
H23
K22
K21
G23
H20
K20
K23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
N23
P21
T20
T23
M20
P20
R23
T22
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
V20
V21
Y23
Y22
T21
U23
W23
Y21
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
M23
+MEM_VREF
M22
+M_ZVDDIO
<7,8>
<7,8>
<7,8>
8/22 Delete C11~C18 (No VGA)

9/6 Change PCI-E from FCH to APU
9/6 Update PCI-E port List
9/15 Change PCI-E from APU to FCH
U1A
AA6
Y6
AB4
AC4
AA1
AA2
Y4
Y3
+1.05VS
R53
2
2K_0402_1%
P_ZVDD_10
Y14
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_GPP_TXP0
P_GPP_TXN0
PCIE I/F
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
P_ZVDD_10
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_ZVSS
AB6
AC6
AB3
AC3
Y1
Y2
V3
V4
AA14 P_ZVSS
R54
1.27K_0402_1%
Less than 1"

Less than 1"
AA12
Y12
<12> UMI_RX0P
<12> UMI_RX0N
<12> UMI_RX1P
<12> UMI_RX1N
AA10
Y10
<12> UMI_RX2P
<12> UMI_RX2N
AB10
AC10
<12> UMI_RX3P
<12> UMI_RX3N
AC7
AB7
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_UMI_TXP0
P_UMI_TXN0
UMI I/F
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
AB12
AC12
UMI_TX0P_C
UMI_TX0N_C
C19
C20
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
AC11
AB11
UMI_TX1P_C
UMI_TX1N_C
C21
C22
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
AA8
Y8
UMI_TX2P_C
UMI_TX2N_C
C23
C24
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
AB8
AC8
UMI_TX3P_C
UMI_TX3N_C
C25
C26
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
UMI_TX0P <12>
UMI_TX0N <12>
UMI_TX1P <12>
UMI_TX1N <12>
UMI_TX2P <12>
UMI_TX2N <12>
UMI_TX3P <12>
UMI_TX3N <12>
M_VREF
M_RAS_L
M_CAS_L
M_WE_L
R55
M_ZVDDIO_MEM_S
+1.5V
39.2_0402_1%
9/11 Delete DDR Signal link to JDIMM2
Reserve C439 for DDR_EVENT#

Michael 2010/11/18
2
1K_0402_5%
R56
1K_0402_1%
DDR_EVENT#
+MEM_VREF
R57
C439
100P_0402_50V8J
R58
1K_0402_1%
C27
C28
1
1
+1.5V
+1.5V
1000P_0402_50V7K
0.1U_0402_16V4Z
Place within 1000 mils to APU

20100526
Compal Secret Data
Issued Date
2010/11/09
2012/11/09
Deciphered Date
A
Title

FT1 DDRIII/UMI/PCIE
Size
Document Number
Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
E
of
37
+APU_CORE
+1.8VS
4500 mA
10U_0603_6.3V6M
1U_0402_6.3V6K
C40
1U_0402_6.3V6K
C39
1U_0402_6.3V6K
C38
1U_0402_6.3V6K
C37
180P_0402_50V8J
C35
.1U_0402_16V7K
C36
10U_0603_6.3V6M
1U_0402_6.3V6K
C51
1
FBMA-L11-201209-221LMA30T_0805
8/25 Change +1.0VS to +1.05VS

+1.05VS
L3
10U_0603_6.3V6M
1U_0402_6.3V6K
C60
.1U_0402_16V7K
C59
L4
+VDD_10
1
FBMA-L11-201209-221LMA30T_0805
+3VS
500 mA
A4
VDD_33
10U_0603_6.3V6M
C67
1U_0402_6.3V6K
C66
1U_0402_6.3V6K
C65
2
1
.1U_0402_16V7K
C64
U13
W13
V12
T12
VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4
FBMA-L11-201209-221LMA30T_0805
10U_0603_6.3V6M
C57
2
1
5500 mA
+VDD_33
1
1
R333
2
0_0603_5%
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC
N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11
8/22 Reserve R333 ( 0 ohm 0603 )
C91
1U_0402_6.3V6K
C90
C83
10U_0603_6.3V6M
C98
C97
180P_0402_50V8J
C96
180P_0402_50V8J
9/15 Change C99,C100 to 470U(SGA00003K00)
POWER
+APU_CORE
SGA00003K00
8/22 Change C111~C113 from E-Cap to Poly-Cap (SGA20331E10)

8/25 Change C111 from poly-cap to E-cap (SF000002Z00)
By case (Along split)
9/11 Change C111 to SGA20331E10
+1.5V
+
2
C114
330U_D2_2V_Y
C117
SGA20331E10
Near CPU Socket
SGA20331E10
10U_0603_6.3V6M
Near CPU Socket
Compal Secret Data
Issued Date
2010/11/09
Deciphered Date
2012/11/09
Title
C110

P07-FT1 PWR/VSS
Size
C
Date:
SGA20331E10
Near CPU Socket
change C99,C100 from 470U to 330U , 2011/01/28 Tock

change C99,C100 footprint from C_D2 to C_X for placement
5
C109
C108
C107
180P_0402_50V8J
C112
330U_D2_2V_Y
C116
180P_0402_50V8J
C115
C111
330U_D2_2V_Y
22U_0805_6.3V6M
1
1
180P_0402_50V8J
180P_0402_50V8J
+1.8VS
Near CPU Socket
+APU_CORE_NB
C106
+1.5V
POWER
C105
POWER
.1U_0402_16V7K
C104
330U_D2_2V_Y
C102 @
10U_0603_6.3V6M
.1U_0402_16V7K
C100
C103
330U_D2_2V_Y
.1U_0402_16V7K
C99
.1U_0402_16V7K
10U_0603_6.3V6M
.1U_0402_16V7K
C95
SGA00004L00
.1U_0402_16V7K
L2
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
C93
220U_D2_2VY_R15M
C94
U1D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11
9/20 Change C93 to SGA00004L00
.1U_0402_16V7K
C92
@
10U_0603_6.3V6M
+1.05VS
1U_0402_6.3V6K
C89
1U_0402_6.3V6K
+1.5V
POWER
+VDDL_10
C82
10U_0603_6.3V6M
C81
180P_0402_50V8J
180P_0402_50V8J
C80
C79
C88
1U_0402_6.3V6K
1U_0402_6.3V6K
C78
C87
1U_0402_6.3V6K
.1U_0402_16V7K
1U_0402_6.3V6K
C77
C86
.1U_0402_16V7K
1U_0402_6.3V6K
C76
C85
.1U_0402_16V7K
1U_0402_6.3V6K
C75
C84
.1U_0402_16V7K
C34
C49
U11
VDDPL_10

1
180P_0402_50V8J
C50
.1U_0402_16V7K
C63
VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
W = 15 mil / Spcae = 20 mil
DP Phy/IO
G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16
1U_0402_6.3V6K
C72
C71
10U_0603_6.3V6M
10U_0603_6.3V6M
C70
10U_0603_6.3V6M
C69
10U_0603_6.3V6M
C68
DDR3
10U_0603_6.3V6M
+VDD_18_DAC
POWER
+1.5V
VDD_18_DAC
PCIE/IO/DDR3 Phy
2000 mA
+1.8VS
W9
180P_0402_50V8J
C58
+APU_CORE_NB
VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22
W = 20 mil / Spcae = 20 mil
+APU_CORE_NB
E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13
C61
8000 mA
180P_0402_50V8J
C62
10U_0603_6.3V6M
C33
C48
180P_0402_50V8J
U8
W8
U6
U9
W6
T7
V7
VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7
C73
VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
.1U_0402_16V7K
C74
10U_0603_6.3V6M
C30
C47
C56
180P_0402_50V8J
C42
10U_0603_6.3V6M
10U_0603_6.3V6M
C41
E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8
.1U_0402_16V7K
1U_0402_6.3V6K
C46
C55
.1U_0402_16V7K
C32
10U_0603_6.3V6M
1U_0402_6.3V6K
C45
C54
.1U_0402_16V7K
C29
10U_0603_6.3V6M
1U_0402_6.3V6K
C44
C53
DIS PLL
.1U_0402_16V7K
10U_0603_6.3V6M
C31
C43
C52
GPU AND NB CORE
DAC
L1
2
1
FBMA-L11-201209-221LMA30T_0805
GND
CPU CORE
1U_0402_6.3V6K
.1U_0402_16V7K
+VDD_18
TSense/PLL/DP/PCIE/IO
2000 mA
U1C
+APU_CORE
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
1
of
37
DDR_A_D16
DDR_A_D17
<5,8> DDR_A_DQS#2
<5,8> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
R396
1
<5,8> DDR_CKE0
100_0402_1%
<5,8> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5> DDR_A_CLK0
<5> DDR_A_CLK#0
DDR_A_MA10
<5,8> DDR_A_BS0
<5,8> DDR_A_WE#
<5,8> DDR_A_CAS#
DDR_A_MA13
<5> DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
<5,8> DDR_A_DQS#4
<5,8> DDR_A_DQS4
B
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<5,8> DDR_A_DQS#6
<5,8> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
R63
10K_0402_5%
1
2
R64
10K_0402_5%
2
0.1U_0402_16V4Z
C139
C138
+3VS
2.2U_0603_6.3V6K
DDR_A_DM7
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
BOSS1
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
GND2
BOSS2
206
208
R60
1K_0402_1%
DDR_A_D6
DDR_A_D7
+VREF_CA
DDR_A_DM1
DDR_RST# <5,8>
R61
1K_0402_1%
C413
100P_0402_50V8J
R62
1K_0402_1%
1
Reserve C413 for DDR_RST#

Michael 2010/11/18
+VREF_DQ
DDR_RST#
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
9/23 Reserve R396,R397 on CKE0 & CKE1(S3 hang Issue)

DDR_A_DQS#3 <5,8>
DDR_A_DQS3 <5,8>
DDR_A_D30
DDR_A_D31
+1.5V
R397
2
100_0402_1%
DDR_A_MA15
DDR_A_MA14
DDR_CKE1 <5,8>
1
0.1U_0402_16V4Z
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
0.1U_0402_16V4Z
2
C120
C121
1
0.1U_0402_16V4Z
2
C122
C123
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C124
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C125
C126
@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C127
@
C128
@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C129
@
C130
@
1
0.1U_0402_16V4Z
C131
@
10/11 Change R396 R397 from @ to mount (For A1 APU,B0 APU no Need)
DDR_A_MA2
DDR_A_MA0
9/11 Change C137 to SGA00004L00

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
CRB 0.1u X1
DDR_A_BS1 <5,8>
DDR_A_RAS# <5,8>
+VREF_CA
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
W=20mil
@
1
CRB
100U
X2
+0.75VS
DDR_A_ODT1 <5>
DDR_A_D36
DDR_A_D37
4.7u X1
+1.5V
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
1
+
@
C137
220U_6.3V_M
Place near JDIMM1
SGA00004L00
DDR_A_DQS#5 <5,8>
DDR_A_DQS5 <5,8>
change C137 to SF000002Y00

2010/12/14 Tock
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
8/25 Change C137 from poly-cap to E-cap (SF000002Y00)

8/25 Reserve C381 E-cap (SF000002Y00) on +1.5V
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <5,8>
DDR_A_DQS7 <5,8>
DDR_A_D62
DDR_A_D63
9/11 Remove C381

+0.75VS
DDR_EVENT# <5,8>
FCH_SMDAT0 <8,13,20,21>
FCH_SMCLK0 <8,13,20,21>
A
100 mA
FOX_AS0A621-U4RG-7H
Compal Secret Data
2010/11/09
Issued Date
2012/11/09
Deciphered Date
5
2
R59
1K_0402_1%
<5,8>
DDR_A_DQS#0 <5,8>
DDR_A_DQS0 <5,8>
1
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_A_DM[0..7]
+1.5V
4.7U_0603_6.3V6K
DDR_A_D10
DDR_A_D11
DDR_A_DM[0..7]
+1.5V
<5,8> DDR_A_DQS#1
<5,8> DDR_A_DQS1
<5,8>
C136
DDR_A_D8
DDR_A_D9
DDR_A_D[0..63]
DDR_A_MA[0..15] <5,8>
0.1U_0402_16V4Z
DDR_A_D2
DDR_A_D3
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_D4
DDR_A_D5
C135
DDR_A_DM0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
0.1U_0402_16V4Z
DDR_A_D0
DDR_A_D1
CONN@
C134
C119
1000P_0402_50V7K
2
D
0.1U_0402_16V4Z
C118
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
0.1U_0402_16V4Z
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Change JDIMM1 socket to SP07000NN00

2010/12/06 Tock
Change JDIMM1 socket to SP07000NZ00
2010/12/14 Tock
C133
W=20mil
+VREF_DQ
3500 mA
+1.5V
1000P_0402_50V7K
+1.5V
C132
Title

DDR3 SODIMM-I Socket

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
of
37
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<5,7> DDR_A_DQS#2
<5,7> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
@ R421
1
<5,7> DDR_CKE0
<5,7> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5> DDR_B_CLK2
<5> DDR_B_CLK#2
DDR_A_MA10
<5,7> DDR_A_BS0
<5,7> DDR_A_WE#
<5,7> DDR_A_CAS#
DDR_A_MA13
<5> DDR_CS1_DIMMB#
DDR_A_D32
DDR_A_D33
<5,7> DDR_A_DQS#4
<5,7> DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<5,7> DDR_A_DQS#6
<5,7> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
1
R131
0.1U_0402_16V4Z
C159
C158
2.2U_0603_6.3V6K
+3VS
A
10K_0402_5%
DDR_A_D58
DDR_A_D59
@ R130
10K_0402_5%
1
2
+3VS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
<5,7>
DDR_A_DM[0..7]
DDR_A_DM[0..7]
<5,7>
DDR_A_DQS#0 <5,7>
DDR_A_DQS0 <5,7>
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_RST# <5,7>
DDR_A_D14
DDR_A_D15
DDR_RST#
DDR_A_D20
DDR_A_D21
Reserve C414 for DDR_RST#

Michael 2010/11/18
DDR_A_DM2
C414
100P_0402_50V8J
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 <5,7>
DDR_A_DQS3 <5,7>
DDR_A_D30
DDR_A_D31
+1.5V
@ R401
1
100_0402_1%
DDR_A_D[0..63]
DDR_A_MA[0..15] <5,7>
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
0.1U_0402_16V4Z
2
2
DDR_CKE1 <5,7>
100_0402_1%
DDR_A_MA15
DDR_A_MA14
C167
@
1
0.1U_0402_16V4Z
C145
@
0.1U_0402_16V4Z
2
C141
@
1
0.1U_0402_16V4Z
C144
@
0.1U_0402_16V4Z
2
C143
@
1
0.1U_0402_16V4Z
C150
@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C154
@
C151
@
1
0.1U_0402_16V4Z
C149
@
0.1U_0402_16V4Z
2
C157
@
1
0.1U_0402_16V4Z
C155
@
9/23 Reserve R421,R401 on CKE0 & CKE1(S3 hang Issue)

10/11 Change R421 R401 from @ to mount (For A1 APU,B0 APU no Need)
DDR_A_MA2
DDR_A_MA0
DDR_B_CLK3 <5>
DDR_B_CLK#3 <5>
CRB 0.1u X1
4.7u X1
DDR_A_BS1 <5,7>
DDR_A_RAS# <5,7>
+0.75VS
DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_B_ODT1 <5>
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
@
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
W=20mil
Place near JDIMM2
DDR_A_DQS#5 <5,7>
DDR_A_DQS5 <5,7>
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <5,7>
DDR_A_DQS7 <5,7>
DDR_A_D62
DDR_A_D63
+0.75VS
DDR_EVENT# <5,7>
FCH_SMDAT0 <7,13,20,21>
FCH_SMCLK0 <7,13,20,21>
206
G2
100 mA
FOX_AS0A621-U4SG-7H
Compal Secret Data
2010/11/09
Issued Date
2012/11/09
Deciphered Date
5
0.1U_0402_16V4Z
2
C140
@
C152
<5,7> DDR_A_DQS#1
<5,7> DDR_A_DQS1
DDR_A_D4
DDR_A_D5
4.7U_0603_6.3V6K
DDR_A_D8
DDR_A_D9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
0.1U_0402_16V4Z
DDR_A_D2
DDR_A_D3
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C153
DDR_A_DM0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
0.1U_0402_16V4Z
DDR_A_D0
DDR_A_D1
Change JDIMM2 socket to SP07000NZ00 for reverse

2010/12/06 Tock
DDR_A_D[0..63]
Change JDIMM2 socket to SP07000NN00
DDR_A_MA[0..15]
2010/12/14 Tock
C148
@
D
1000P_0402_50V7K
C160
C166
0.1U_0402_16V4Z
+VREF_DQ
CONN@
0.1U_0402_16V4Z
JDIMM2
3500 mA
C147
+1.5V
1000P_0402_50V7K
+1.5V
W=20mil
C146
Title

DDR3 SODIMM-II Socket

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
of
37
Camera
11/02 Change Q3 PN to SB934130020
LCD POWER CIRCUIT
J1
+LCDVDD
Q3
+LCDVDD
+3VS
+3VS
AO3413L_SOT23-3
2
6 +LCDVDD_R
C165
100K_0402_5%
1
W=40mils
R68
2
R69
USB20_N5_1
USB20_P5_1
USB20_N5 <13>
USB20_P5
USB20_P5 <13>
1
R72
0_0402_5%
Change C163 BOM Struture to @

Michael 2010/11/18
USB20_N5
WCM2012F2S-900T04_0805
Remove C164 4.7U

Michael 2010/11/18
C163
C161
0.1U_0402_16V4Z
2
1
2 0.047U_0402_16V4Z
D
Q32A
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
C162 1
470_0402_5%
+CAM_VCC
JUMP_43X39
@
W=40mils
L5
W=40mils
+3VALW
R67
1
R71
0_0402_5%
2011/02/11 Change Q3 PN to SB000006R10
9/15 Remove D1 L5 R71 R72 C166 C167 for layout spacing
9/23 Remove D1 C166 C167
9/23 Add D1 L5 R71 R72 C166 C167 for ESD
9/24 Swap L5
1
4.7K_0402_5%
8/31 Change R68.2 link to +3VALW
8/26 Change Q4 Q5 to Q32A Q32B (SB00000DH00) Standard Part

D
Q32B
<4> APU_ENVDD
R70
100K_0402_5%
8/26 Change Q3 to SB934130020 Standard Part
9/9 Reserve 100k PD to GND on INVTPWM
9/17 Change R387 from @ to mount

10/04 Add 100p(C401) on INVT_PWM
100K_0402_5%
CMOS & LCD/PANEL BD. Conn.
R387 1
2 INVTPWM
DMIC
8/25 JLVDS1.5 change to INT_MIC0 JLVDS1.6 change to GNDA
ohm for +3VS_MIC
Add R344 0
Michael 2010/11/18
0_0402_5%
0_0402_5%
1 R310
INVT_PWM <26>
EC
1 R311
APU_BLPWM <4>
APU
8/31 Update JLVDS1 Pin definition Delete R74 R76
GND1
GND2
GND3
GND4
GND5
GND6
8/22 Reserve R327~R332( 0 ohm) for eDP

+3VS
8/31 Reserve R353 R354 on LVDS_ACLK
camera
+CAM_VCC W=20mil
DMIC_CLK <4,17>
DMIC_DATA <17,26>DMIC
LVDS_ACLK <4>
LVDS_ACLK# <4>
0_0402_5%
0_0402_5%
2 LVDS@ 1 R327
2 LVDS@ 1 R328
LVDS_A2 <4>
LVDS_A2# <4>
2 LVDS@ 1 R329
2 LVDS@ 1 R330
2 LVDS@ 1 R331
2 LVDS@ 1 R332
0_0402_5%
0_0402_5%
2 LVDS@ 1 R381
2 LVDS@ 1 R382
9/7 Reserve R381,R382( 0 ohm)R383(100k@) for eDP
0_0402_5%
1 R334
+LCDVDD
L6
FBMA-L11-201209-221LMA30T_0805
L7 2
LVDS_A0 <4>
LVDS_A0# <4>
STARC_107K30-000001-G2
1
W=20mil
C168
220P_0402_50V7K
3G@
EDID_DATA <4>
EDID_CLK <4>
R381
DA2
PJDLC05C_SOT23-3
R382
eDP@
eDP@
SE070104Z80
5
eDP@
0 ohm
0.1uF
R381
0 ohm
0.1uF
R382
0 ohm
@
0.1uF
100k ohm
R73
2.2k ohm
R75
2.2k ohm 100k ohm
1
CA55
2 22P_0402_50V8J
CA56
2 22P_0402_50V8J
9/3 Pull-Down 10k(R377) to GND on BKOFF#

R377 1
2 10K_0402_5%
2010/11/09
Issued Date
Compal Secret Data
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
eDP@
R328
R328
0.1uF
DMIC_DATA
@
C171
100P_0402_50V8J
3G@
BKOFF#
R327
0 ohm
DMIC_CLK
change JLVDS1 to SP010011S00

2010/12/14 Tock
R327
R383
For RF
W=20mil
FBMA-L11-201209-221LMA30T_0805
1
C169
1000P_0402_50V7K
3G@
8/22 Reserve R334(0402 0 ohm)

B+
C170
330P_0402_50V7K
3G@
SD028100380
BKOFF#
1
+3VS
eDP
INVT_PWM
BKOFF# <26>
1
LVDS
eDP@
LVDS_A1 <4>
LVDS_A1# <4>
EDID_DATA
EDID_CLK
Display
eDP@
100K_0402_5%
2 LVDS@ 1 R353
2 LVDS@ 1 R354
0_0402_5%
0_0402_5%
R75
100K_0402_5%
R383 1
2
EDID_DATA_R
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
EDID_CLK_R
LVDS@
1 R344
0_0402_5%
CONN@
+3VS_MIC
1 1
USB20_P5_1
2 2
USB20_N5_1
3 3
4
4
DMIC_CLK
5 5
DMIC_DATA
6 6
7 7
LVDS_ACLK_R
8 8
LVDS_ACLK#_R
9
9
10 10
LVDS_A2_R
11
11
LVDS_A2#_R
12
12
13 13
LVDS_A1_R
14 14
LVDS_A1#_R
15
15
16 16
LVDS_A0_R
17
17
LVDS_A0#_R
18
18
19 19
EDID_DATA_R
20 20
EDID_CLK_R
21 21
BKOFF#
22 22
INVTPWM
23 23
+3VS_LVDS
24
24
+LCDVDD_L
25
25
26
26
27 27
+LEDVDD
28 28
29
29
30 30
JLVDS1
LVDS@
R73
2.2K_0402_5%
10/04 Change C401 on INVTPWM
10/01 Remove R74,R76
R75
2.2K_0402_5%
1
2
9/13 Add Net Name +3VS_DMIC
1
100P_0402_50V8J
+3VS
9/13 Update LVDS Pin definition, Add R74,R76
Connect DMIC_CLK,
DMIC_DATA
to JLVDS1 pin 5 and 6
Michael 2010/11/18
31
32
33
34
35
36
C401
INVTPWM
2012/11/09
Deciphered Date
3
Title
LVDS / Camera / DMIC

Size
B
Date:
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
1
of
37
HDMI@
R107 1 HDMI@ 2
R112 1
2
<4> HDMI_CLKN
<4> HDMI_CLKP
+5VS
0_0402_5%
0_0402_5%
HDMI_CLK-_CONN
HDMI_CLK+_CONN
Change RP13 to R107 , R112

Tock 2010/12/30
+5VS
<4> HDMI_TX0N
<4> HDMI_TX0P
HDMI@
R141 1 HDMI@ 2
R142 1
2
0_0402_5%
0_0402_5%
HDMI_TX0-_CONN
HDMI_TX0+_CONN

Tock 2010/12/30
<4> HDMI_TX1N
<4> HDMI_TX1P
HDMI@
R143 1 HDMI@ 2
R187 1
2
0_0402_5%
0_0402_5%
HDMI_TX1-_CONN
HDMI_TX1+_CONN

Tock 2010/12/30
+5VS
3
1
HDMIDAT_R
@
D2
BAT54S-7-F_SOT23-3
HDMICLK_R
@
D3
BAT54S-7-F_SOT23-3
HDMI_HPD
@
D4
BAT54S-7-F_SOT23-3
EMI/ESD
D
+3VS
HDMI@
R188 1 HDMI@ 2
R192 1
2
<4> HDMI_TX2N
<4> HDMI_TX2P
0_0402_5%
0_0402_5%
HDMI_TX2-_CONN
HDMI_TX2+_CONN

Tock 2010/12/30
Swap HDMI Net of RP13~RP16 for layout

Tock 2010/12/24
@ L8
2
HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_CLK-_CONN
1
R86
HDMI_TX0+_CONN
WCM-2012-900T_4P
1
R87
HDMI_TX0N
HDMI_TX0+_CONN
HDMI_TX0-_CONN
1
R88
HDMI_TX1+_CONN
1
R89
HDMI_TX1-_CONN
1
R90
HDMI_TX2+_CONN
WCM-2012-900T_4P
1
R91
HDMI_TX2-_CONN
HDMI_TX1P
HDMI_TX1N
1
4
HDMI_TX1+_CONN
HDMI_TX1-_CONN
1
R93
2
3
499_0402_1%
499_0402_1%
@
R95
100K_0402_5%
HDMI_TX2+_CONN
HDMI_TX2-_CONN
NEAR CONNECT
Q7
SSM3K7002FU_SC70-3
2
G
S
8/19 Change Q9A Q9B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
HDMI@
10/29 Add C409~C412(0.1U) on +5VS_HDMI
10/29 Add C415~C416(0.1U) on +5VS_HDMI_F
HDMI_TX2N
HDMIDAT_R
Q9B
HDMI@
499_0402_1%
@ L11
HDMI_TX2P
<4> HDMI_DATA
499_0402_1%
+5VS
WCM-2012-900T_4P
499_0402_1%
@ L10
Q9A
HDMI@
499_0402_1%
499_0402_1%
HDMICLK_R
499_0402_1%
HDMI_TX0-_CONN
@ L9
HDMI_TX0P
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
2
HDMI@
R85
HDMI_CLKN
<4> HDMI_CLK
HDMI_CLK+_CONN
HDMI_CLKP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
HDMI@
2
1 C410
0.1U_0402_16V4Z
HDMI@
1 C411
0.1U_0402_16V4Z
HDMI@
1 C412
+5VS_HDMI
1 C409
0.1U_0402_16V4Z
0.1U_0402_16V4Z
HDMI@
2
1 C416
+5VS_HDMI_F
1 C415
WCM-2012-900T_4P
HDMI@
+5VS
W=60mil
9/20 Add F2 on HDMI

@
R96
0_0805_5%
HDMI@
D5
RB491D_SC59-3
1
10/27 Change D5 P/N from SC1B491D000 to SCS00003H00
HDMI@
10/27 Change F2 P/N from SP04301P120 to SP040001B00
+3VS
HDMI_DET
HDMIDAT_R
HDMICLK_R
HDMI_HPD
HDMI_CLK+_CONN
HDMI_TX0-_CONN
@
R102
100K_0402_5%
HDMI_TX0+_CONN
HDMI_TX1-_CONN
@
R101
200K_0402_5%
R103
100K_0402_5%
HDMI@
HDMI_CLK-_CONN
1
3
R100
1
2
150K_0402_5%
HDMI@
<4>
2
B
JHDMI1
HDMI_HPD
+5VS_HDMI_F
10/28 Change JHDMI1 footprint from

ACON_HMR2E-AK120D_19P-T to ACON_HMR2E-AK120D_19P-S
F2 HDMI@
1.1A_6V_SMD1812P110TF
0_0402_5%
@
C
HDMI@ Q8
MMBT3904_NL_SOT23-3
C172
0.1U_0402_16V4Z
HDMI@
B
HDMI@
R98
2.2K_0402_5%
2
9/20 Change Q8,R100 from @ to HDMI@

R99
2
HDMI@
R97
2.2K_0402_5%
+5VS_HDMI
W=60mil
9/20 Change R99 from HDMI@ to @
10/07 Update JHDMI1 footprint from ACON_HMR2E-AK120D_19P

to ACON_HMR2E-AK120D_19P-T
HDMI_TX1+_CONN
HDMI_TX2-_CONN
HDMI_TX2+_CONN
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
ACON_HMR2E-AK120D
CONN@
11/16 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)

A
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8/23 Update JHDMI1 Symbol (SUYIN_100042GR019S268ZR_19P-T)

9/7 Update JHDMI1 Symbol (ACON_HMR2E-AK120D_19P)
2010/11/09
Issued Date
Compal Secret Data
2012/11/09
Deciphered Date
5
Title
HDMI Connector
Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
10
of
37
D6
Close to CRT CONN for ESD.
D7
@
1
L12
1
<4> DAC_RED
L13
<4> DAC_GRN
<4> DAC_BLU
+5VS
1
C177
CHENG-HANN MBK1005470YZF 0402

2
RED

2
GREEN

2
BLUE
1
1
C178
10P_0402_50V8J
C176
10P_0402_50V8J
R106
10P_0402_50V8J
R105
150_0402_1%
2
1
R104
150_0402_1%
2
1
150_0402_1%
2
1
L14
Change L12. L14, L15 to SM01000C600 2010/04/06
PJDLC05C_SOT23-3
0615
PJDLC05C_SOT23-3
Modify C31- C308 C303 C307 C306 C304 BOM Structure
C173
10P_0402_50V8J
2
C174
10P_0402_50V8J
2
C175
10P_0402_50V8J
JVGA_HS
1
C179
2
0.1U_0402_16V4Z
JVGA_VS
U2
<4> CRT_HSYNC
IN A
GND
Vcc
OUT Y
CRT_HSYNC_R
R375 1
2 39_0402_5%
Delete Q10 , R107

for CRT Hot Plug detect Circuit
2010/12/15 Tock
TC7SET125FUF_SC70-5
R325 1
0_0402_5%
8/31 Delete Net Name: CRT_HSYNC_1, CRT_VSYNC_1
+5VS
8/21 Change U2 U3 to SA00000RZ00 (TC7SET125FUF_SC70-5)
1
C180
8/21 Reserve R325 R326 for CRT buffer cost down
9/3 Add R375 R376 for CRT
2
0.1U_0402_16V4Z
U3
1
<4> CRT_VSYNC
Vcc
CRT PORT
IN A
GND
CRT_VSYNC_R
OUT Y
R376 1
2 39_0402_5%

8/22 Update JCRT1 Symbol from database (SUYIN_070546FR015M21TZR_15P)
+CRT_VCC
+5VS
TC7SET125FUF_SC70-5
0.1U_0402_16V4Z
D8
2
R326 1
W=40mils
1
RB491D_SC59-3
+CRT_VCC_F
2.2K_0402_5%
2.2K_0402_5%
T27PAD
VGA_DDC_CLK
JCRT_5
G
G
16
17
SUYIN_070546FR015M21TZR
CONN@
VGA_DDC_DAT
S
2
JVGA_VS
JCRT_4
2.2K_0402_5%
2
Add JCRT_4 , JCRT_5 , JCRT_11

2011/01/28 Tock
Delete R112 and net CRT_DET#

for CRT Hot Plug detect Circuit
2010/12/15 Tock
VGA_DDC_CLK
<4> CRT_DDC_CLK
T26PAD
R111
Q11B
R110
5
R108
remove CRT11, CRT4

Tock 2010/11/26
JCRT1
JVGA_HS
BLUE
10/4 Change from +CRT_VCC to +CRT_VCC_F
11/01 Add Net CRT4, CRT11 on JCRT.4 , JCRT.11
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
JCRT_11
RED
VGA_DDC_DAT
GREEN
8/26 Update D8 P/N to SCS00003H00

8/26 Update F1 P/N to SP040001B00
+3VS
<4> CRT_DDC_DATA
+CRT_VCC_F 1
1.1A_6VDC_FUSE
T15PAD
R109
C181
2
0_0402_5%
+3VS
2.2K_0402_5%
F1
1
Q11A
8/19 Change Q11A Q11B to SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
2010/11/09
Issued Date
Compal Secret Data
2012/11/09
Deciphered Date
A
Title
CRT PORT
Size
B
Date:
Document Number
P1VE6 Schematics
Sheet
E
11
of
37
Rev
1.0
1
1
1
1
1
1
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
<20>
<20>
<18>
<18>
<21>
<21>
PCIE_CALRP
PCIE_CALRN
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1
PCIE_FTX_DRX_P2
PCIE_FTX_DRX_N2
PCIE_FTX_DRX_P3
PCIE_FTX_DRX_N3
AD29
AD28
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
AA22
Y21
AA25
AA24
W23
V24
W24
W25
PCIE_FRX_DTX_P1
PCIE_FRX_DTX_N1
PCIE_FRX_DTX_P2
PCIE_FRX_DTX_N2
PCIE_FRX_DTX_P3
PCIE_FRX_DTX_N3
UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
PCIE_CALRP
PCIE_CALRN
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
9/15 Change PCI-E from APU to FCH

close to FCH within 1"
<4>
<4>
+RTCBATT1
R125 1
R126 1
DISP_CLK
DISP_CLK#
2 0_0402_5%
2 0_0402_5%
M23
P23
DISP_CLK_R
DISP_CLK#_R
T26
T27
CONN@
JBATT1
<4>
<4>
R127 1
R128 1
APU_CLK
APU_CLK#
2 0_0402_5%
2 0_0402_5%
APU_CLK_R
APU_CLK#_R
WLAN
<21> CLK_PCIE_WLAN
<21> CLK_PCIE_WLAN#
R134 1
R135 1
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R
WWAN
<20> CLK_PCIE_WWAN
<20> CLK_PCIE_WWAN#
R348 1
R349 1
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_WWAN_R M29
CLK_PCIE_WWAN#_R M28
LOTES_AAA-BAT-019-K01
8/23 Add R348 R349 for WWAN PCIE
9/13 Add NONCHARGE@ for D10 R244

12/07 Remove BOM structure NONCHARGE@ for D10 R244
+CHGRTC
Tock
+RTCBATT1_R 1
R244
9/1 Add R372 on CLK_48M_CR
2
1K_0402_5%
9/7 Change R372 to 22 ohm
W=20mil
2 22_0402_5%CLK_48M_CR_R
R372 1
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
L24
L23
GPP_CLK4P
GPP_CLK4N
P25
M25
GPP_CLK5P
GPP_CLK5N
P29
P28
GPP_CLK6P
GPP_CLK6N
N26
N27
GPP_CLK7P
GPP_CLK7N
T29
T28
L25
INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48
GPP_CLK8P
GPP_CLK8N
ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L
1
C361
10P_0402_50V8J
2
3G@
25M_CLK_X1
L26
1M_0603_5%
25M_CLK_X2
R139
L27
C198
22P_0402_50V8J
C199
22P_0402_50V8J
1
2
Y2
25MHZ_20PF_7A25000012
9/13 Add Net Name +RTCBATT1_RR
25M_X1
G21
H21
K19
G22
J24
2 100K_0402_5%
10/11 Change Y1 from SJ100006600 to SJ132P7KW10

PE_GPIO0
Close to FCH
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
<16>
<16>
<16>
<16>
<16>
@ R123 20M_0402_5%
@R123
1
2
C196
1
2
RTC_32KHO
2
22P_0402_50V8J
Y1
4
R124
20M_0603_5%
C197
1
2
OSC
NC
OSC
NC
3
2
32.768KHZ_12.5PF_Q13MC14610002
RTC_32KHI
22P_0402_50V8J
10/05 PD 10k(R405) on CLKRUN

+1.8VS
PAD T18
+3VS
R129
10K_0402_5%
PE_GPIO1
R405
PAD T19
APU_PWRGD
FDV301N-NL_SOT23-3
Q12
R136 1
2 0_0402_5%
LPCCLK0 <16>
R137 1
R138 1
2 22_0402_5%
2 0_0402_5%
LPC_CLK0_EC <26>
CLK_PCI_DB <16>
LPC_AD0 <26>
LPC_AD1 <26>
LPC_AD2 <26>
LPC_AD3 <26>
LPC_FRAME# <26>
H_PWRGD_L <36>
10K_0402_5%
C396
100P_0402_50V8J
C396 near to PR12

Michael 2010/11/18
10/04 Add 100p(C396) on H_PWRGD_L

LPC_CLK0_EC 1
SERIRQ <26>
ALLOW_STOP# <4>
FCH_PROCHOT# <4>
APU_PWRGD <4>
U5_G22
LDT_RST# <4>
25M_X2
32K_X1
C1
RTC_32KHI
32K_X2
C2
RTC_32KHO
C359
10P_0402_50V8J
reserve C359 for RF

Tock 2010/12/28
T31
PAD
RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G
D2
B2
B1
10/07 Change R140 from 560 to 1k ohm

11/01 Add Net U5_G22 on U5.G22
SUSCLK <26>
+RTCBATT_R
S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA
SA000046HA0
1
R140
+RTCBATT
2
1K_0402_5%
1
C200
2
B
PE_GPIO0, PE_GPIO1 are for DIS only

It's no function for UMA
P1VE6 follow P5WE6 Tock 2010/11/26
11/04 Change U5 PN to SA000046HA0 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 0FA)

reserve R388 , C361 for RF
9/13 Add C392,R392,D23(CHARGE@) for RTC Charge Circuit Tock 2010/12/29
10/07 Change R392 from 1k to 0 ohm
Compal Secret Data
change R388,C361 BS from @ to 3G@ for RF solution
2010/11/09
2012/11/09
10/08 Change R392 from 0 ohm to 1k ohm
Issued Date
Deciphered Date
Tock 2011/03/16
11/01 Change R392 from 1k to 0 ohm
+5VALW
2 100K_0402_5%
PE_GPIO0 R122 1
8/25 Change FCH(U5) PN to SA000046H30
Tock
10K_0402_5%
R113
PE_GPIO1 R117 1
9/13 Change Net Name +RTCBATT1 to +RTCBATT2
12/07 Remove R392 , C392 , D23
9/9 Change R117 R122 from mount to @

9/15 PU PE_GPIO1 100k to +5VALW
AJ6
AG6
AG4
AJ4
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
14M_25M_48M_OSC
RTC
R388
22_0402_5%
3G@
PAD T17
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
<19> CLK_48M_CR
CPU_HT_CLKP
CPU_HT_CLKN
CPU
BAV70W_SOT323-3
NB_HT_CLKP
NB_HT_CLKN
T25
V25
+RTCBATT1
3
1
N29
N28
NB_DISP_CLKP
NB_DISP_CLKN
LPC
9/6 Change D10 to SC600000B00 Standard Part
D10
L29
L28
PCI_CLK3 <16>
PCI_CLK4 <16>
V2
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
PCI_CLK1 <16>
<18> CLK_PCIE_LAN
<18> CLK_PCIE_LAN#
LAN
2 0_0402_5%
2 0_0402_5%
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
CLOCK GENERATOR
R132 1
R133 1
V21
T21
V23
T23
8/21 Delete R130,R131(No VGA)
U29
U28
PAD T16
PCI_CLK2
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L
9/6 Change PCI-E from FCH to APU
8/25 Update JBATT1 Symbol (LOTES_AAA-BAT-019-K01_2P)
PCIRST_L
PCI I/F
WWAN FCH RX
LAN FCH RX
WLAN FCH RX
590_0402_1%
2K_0402_1%
UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N
W2
W1
W3
W4
Y1
C192
C193
C194
C195
C379
C380
PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1
PCIE_FTX_C_DRX_P2
PCIE_FTX_C_DRX_N2
PCIE_FTX_C_DRX_P3
PCIE_FTX_C_DRX_N3
1
1
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
2
2
PCIE_RST_L
A_RST_L
R121
R118
+PCIE_VDDAN
WWAN FCH TX
LAN FCH TX
WLAN FCH TX
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
<20>
<20>
<18>
<18>
<21>
<21>
UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C
UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
2
2
2
2
2
2
2
2
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
1
1
1
1
1
1
1
1
2 0_0402_5% P1
2 0_0402_5% L1
9/16 Change U4,C182 from @ to mount,

R120, R115 from mount to @
UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N
C184
C185
C188
C186
C187
C189
C190
C191
PCI EXPRESS I/F
9/2 Change R120 from 0603 to 0402
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
U5E
R384 1
R385 1
1 33_0402_5%
W=20mil
2 0_0402_5%
R119
Watchdog timer on NB_PWRGD

enable for pull-up
disable for pull-down
20100527
2
@
A_RST#
R116
R115
100K_0402_5%
PCI CLKS
150P_0402_50V8J
2
1 C183
PLT_RST# <18,20,21,26>
NC7SZ08P5X_NL_SC70-5
+RTCBATT
+3VS
10/08 Update U5 to SA000046H70 S IC 218-0792006 A13 HUDSON-M1 605P ABO!
1U_0402_6.3V6K
PLT_RST#
R120 1
10K_0402_5%
5
Y
R114
8.2K_0402_5%
@
9/20 C183.2 link to R119.2 Follow CRB
U4
A_RST#
9/9 Add R384(@ 0 ohm) R385(0 ohm) on PCI-E RST
0.1U_0402_16V4Z
2
+3VALW
C182
CLRP1 @
SHORT PADS
For Clear CMOS, near to RAM door
Title

FCH PCIE/PCI/ACPI/LPC/RTC

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
E
12
of
37
+3VS
KB_RST#
C418
100P_0402_50V8J
@
2 10K_0402_5%
<18,20,21> FCH_PCIE_WAKE#
<4> H_THERMTRIP#
1 0_0402_5%
C417
100P_0402_50V8J
@
<18> LAN_CLKREQ#
1 0_0402_5%
8/31 Delete Net : SATA_DET#

<17> FCH_SPKR
<7,8,20,21> FCH_SMCLK0
<7,8,20,21> FCH_SMDAT0
<20> WWAN_CLKREQ#
<21> WLAN_CLKREQ#
5
C397
100P_0402_50V8J
C202
1 .1U_0402_16V7K
ICH_POK <26>
VGATE
U6 @
1
2
+3VALW
<26,36>
Reserve C422 for ICH_POK

Michael 2010/11/18
8/22 Delete Net : R161
C422
100P_0402_50V8J
@
<26> EC_LID_OUT#
2
2
2
2
EC_RSMRST#
HDA_SDIN0
HDA_SDOUT
Reserve C358 for RF

Tock 2010/12/28
EC_SCI#
GATEA20
+3VALW
+3VALW
+3VALW
@
R414
P0@
R406
@
R409
1
R408
C441
100P_0402_50V8J
@
FCH_PCIE_WAKE#
R181
2 10K_0402_5%
1
C445
100P_0402_50V8J
@
T23
T24
C442
100P_0402_50V8J
PAD
PAD
Reserve C427 , C440, C441, C442, C445

for SCI, SMI, PCIE_WAKE#, GATE20, PCI_PME#
Michael 2010/11/18
GPIO187 E23
GPIO188 E24
F21
G29
GPIO189
GPIO190
GPIO191
GPIO192
D27
F28
F29
E27
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160
2
11.8K_0402_1%
USB_FSD0P/GPIO185
USB_FSD0N
H9
J8
USB_HSD13P
USB_HSD13N
B12
A12
USB_HSD12P
USB_HSD12N
F11
E11
USB_HSD11P
USB_HSD11N
E14
E12
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
G12
G14
G16
G18
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_HSD2P
USB_HSD2N
J16
J18
USB_HSD1P
USB_HSD1N
B17
A17
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
8/23 USB port8 link to SIM
D13
C13
USB_HSD4P
USB_HSD4N
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
9/1 Update USB Port List
A13
B13
D16
C16
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
9/15 Update USB Port List
J12
J14
USB_HSD5P
USB_HSD5N
USB_HSD0P
USB_HSD0N
A16
B16
D25
F23
B26
E26
F25
E22
F22
E21
GPIO193
GPIO194
R167 2
R169 2
change R407,R408,R410,R413 from 10K to 1K

11/26 Tock
change R406 BOM to P0@ , R407 BOM to P1@
2011/01/04 Tock
mount
EC_PWM2
EC_PWM3
mount
B
Card Reader
USB20_P5 <9>
USB20_N5 <9>
Camera
USB20_P4 <20>
USB20_N4 <20>
SIM
USB20_P3 <20>
USB20_N3 <20>
WWAN
USB20_P2 <25>
USB20_N2 <25>
USB Conn.(RS) JUSB1
USB20_P1 <24>
USB20_N1 <24>
USB Conn.(LS) IO
USB20_P0 <24>
USB20_N0 <24>
USB Conn.(LS) IO
Internal Pull-Up available
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
+3VALW
3

Change R183 from @ to mount
EC_PWM3
EC_PWM2
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
EC_PWM3 EC_PWM2
ROM TYPE
NC
SPI ROM
NC
NC
Reserved
Reserved
LPC ROM
2010/11/09
2012/11/09
Deciphered Date
C
Compal Secret Data
Issued Date
P1VS6
Bluetooth
USB20_P6 <19>
USB20_N6 <19>
G24
G25
E28
E29
D29
D28
C29
C28
Board ID
P1VE6
WiMax
USB20_P7 <20>
USB20_N7 <20>
FCH_SIC <4>
FCH_SID <4>
10/28 Add R413 R414 on GPIO192 for project ID
R407
WWAN
USB20_P8 <21>
USB20_N8 <21>
1 10K_0402_5%
1 10K_0402_5%
10/27 Change R408 R410 from @ to mount
R406
USB20_P9 <20>
USB20_N9 <20>
2 10K_0402_5%
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
USB_RCOMP 1
R410
1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5%

2
GPIO189
GPIO190
GPIO191
GPIO192
P1@
R407
C427
100P_0402_50V8J
@
10K_0402_5%
R180
PCI_PME#
@
R411
10K_0402_5% 10K_0402_5% 10K_0402_5%
R413
EC_SMI#
+3VALW
2 10K_0402_5%
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
J10
H11
USB_HSD8P
USB_HSD8N
BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L
R146
G19
USB_FSD1P/GPIO186
USB_FSD1N
USB_HSD9P
USB_HSD9N
EMBEDDED CTRL
22P_0402_50V8J
Pull-down for enable

high performance mode
20100527 (required for M1)
2 10K_0402_5%
2 10K_0402_5%
M3
N1
L2
M2
M1
M4
N2
P2
CLK_REQ4_L/SATA_IS0_L/GPIO64
SMARTVOLT1/SATA_IS2_L/GPIO50
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN
A10
10mils and <1"
USB_HSD10P
USB_HSD10N
GBE LAN
R177
+3VALW
C440
100P_0402_50V8J
@
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
2 33_0402_5% HDA_SYNC
2 33_0402_5% HDA_RST#
R175 1
R176 1
co-lay 22P on C358 for 3G @

for RF solution
Tock 2011/03/16
2 33_0402_5%
2 33_0402_5%
R173 1
R174 1
<17> HDA_SYNC_AUDIO
<17> HDA_RST_AUDIO#
HDA_BITCLK_AUDIO
C358 3G@
R166 1
R168 1
<17> HDA_BITCLK_AUDIO
<17> HDA_SDOUT_AUDIO
<17> HDA_SDIN0
HDA_BITCLK
<25> USB_OC1#
<24> USB_OC0#
USB_RCOMP
RSMRST_L
HD AUDIO
2
2.2K_0402_5%
2
10K_0402_5%
@
2
10K_0402_5%
2
10K_0402_5%
1
2
C358
10P_0402_50V8J
N3G@
@
C474
100P_0402_50V8J
Reserve C474 for USB_OC1#

Tock 2011/01/07
change RP5 to R162 , R163 , R164 , R186

Tock 2010/12/30
1
R165
1
R170
1
R171
1
R172
USB_OC5#
USB_OC4#
USB_OC3#
USB_OC2#
H3
D1
E4
D4
E8
F7
E7
F8
USBCLK/14M_25M_48M_OSC
USB OC
1
1
1
1
USB_OC7#
10K_0402_5% USB_OC1#
10K_0402_5% FCH_SMCLK1
10K_0402_5% FCH_SMDAT1
10K_0402_5%
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
FCH_SMCLK1
F5
FCH_SMDAT1
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
R162
K3
AA20
USB_OC7#
USB_OC1#
R162
R186
R164
R163
G1
<26> EC_RSMRST#
+3VS @
C201 .1U_0402_16V7K
1
2
<36> FCH_PWRGD
NB_PWRGD
EC_RSMRST#
PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD
USB 2.0
R148 1
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19
GPIO
C431
100P_0402_50V8J
<26>
<26>
<26>
<26>
C426
100P_0402_50V8J
@
Reserve C417 for EC_RSMRST#

Michael 2010/11/18
R160 2
+3VALW
Reserve C431 for H_THERMTRIP# Michael 2010/11/18

H_THERMTRIP#
FCH_PWRGD
T20PAD
T21PAD
T22PAD
8/31 Pull up 10k(R359) to +3VS on WWAN_CLKREQ#

R159 2
<26> SLP_S3#
<26> SLP_S5#
<26> PBTN_OUT#
PBTN_OUT#
WWAN_CLKREQ#
2
10K_0402_5%
LAN_CLKREQ#
2
10K_0402_5%
WLAN_CLKREQ#
2
10K_0402_5%
NB_PWRGD
2
4.7K_0402_5%
FCH_SMCLK0
2
2.2K_0402_5%
FCH_SMDAT0
2
2.2K_0402_5%
1
R359
1
R155
1
R156
1
R157
1
R149
1
R158
PCI_PME#
USB 1.1
Reserve C418 for KB_RST#, C426

for PBTN_OUT Michael 2010/11/18
<26>
U5A
10K_0402_5%
1
2
R179
EC_LID_OUT#
2
10K_0402_5%
2.2K_0402_5%
2
1
R183
FCH_SIC
2
2 10K_0402_5% FCH_SID
2 10K_0402_5% USB_OC5#
2 10K_0402_5% USB_OC4#
10K_0402_5%
1
R145 1
R147 1
R151 1
R152
Swap net of RP3 & RP5 for layout

Tock 2010/12/27
Change RP4 to R145, R147, R151, R152 for layout

Tock 2010/12/27
+3VALW
USB MISC
1
R144
ACPI/WAKE UP EVENTS
USB_OC0#
2
2 10K_0402_5% USB_OC3#
2 10K_0402_5% USB_OC2#
2 10K_0402_5% FCH_PCIE_WAKE#
10K_0402_5%
1
R150 1
R153 1
R154 1
R161
Change R145, R147, R151, R152 to RP4

Michael 2010/12/23
10K_0402_5%
1
2
R178
Change to RP3 to R150 , R153 , R154 , R161

Tock 2010/12/30
2.2K_0402_5%
2
1
R182
+3VALW
Title
FCH HDA/USB/ACPI
Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
E
13
of
37
U5B
AJ8
AH8
<22> SATA_DTX_C_IRX_N0
<22> SATA_DTX_C_IRX_P0
AH10
AJ10
SATA_TX1P
SATA_TX1N
AG10
AF10
SATA_RX1N
SATA_RX1P
AG12
AF12
SATA_TX2P
SATA_TX2N
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
AJ17
AH17
AJ18
AH18
AH19
AJ19
10 mils and < 1"

+AVDD_SATA
R184
R185
2 1K_0402_1%
2 931_0402_1%
1
1
SATA_CALRP
SATA_CALRN
AD11
<22> HDD_LED#
R190 1
25M_SATA_X1 AD16
@ C209
22P_0402_50V8J
@ C210
22P_0402_50V8J
1
2
SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
SATA_CALRP
SATA_CALRN
SATA_ACT_L/GPIO67
25M_SATA_X2 AC16
SATA_X1
SATA_X2
GPIO161
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161
SPI ROM
T25 PAD
J5
E2
K4
K9
G2
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
1M_0603_5%
R195
25MHZ_20PF_7A25000012
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM
@
Y3
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
SATA_RX4N
SATA_RX4P
2 10K_0402_5%
+3VS
AB14
AA14
SATA_TX4P
SATA_TX4N
FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
HW MONITOR
9/7 Change SATA_CALRN from +1.1VS to +AVDD_SATA
SATA_RX0N
SATA_RX0P
SERIAL ATA
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
GPIOD
8/21 Delete C205~C208 (No ODD ESATA function)
SATA_TX0P
SATA_TX0N
NC1
NC2
AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
11/01 Add Net U5_AE29 on U5.AE29

2011/0103 delete Net U5_AE29 on U5.AE29
T28
2011/01/28 Add Net U5_AE29 on U5.AE29 for Layout test point
U5_AE29
PAD
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
+3VS
2
SATA_ITX_C_DRX_P0 AH9
SATA_ITX_C_DRX_N0 AJ9
@
GPIO56
W5
W6
Y9
W7
V9
W8
8/21 Delete Net : ODD_EN

8/22 Delete Net : BT_OFF#, WL_OFF#
TEMPIN0
TEMPIN1
TEMPIN2
A3
B4
A4
C5
A7
B7
B8
A8
GPIO175
GPIO176
GPIO177
GPIO178
GPIO179
GPIO180
GPIO181
GPIO182

R189 2
1 10K_0402_5%
R191 2
1 10K_0402_5%
R194 2
1 10K_0402_5%
APU_ALERT#_FCH <4>
R198 2
1 10K_0402_5%
VIN6/GBE_STAT3/GPIO181
Enable integrated pull-down/up and leave unconnected
@
GPIO177
TEMPIN2
TEMPIN0
GPIO180
R196
R197
R199
R236
2
2
2
2
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
GPIO182
GPIO179
TEMPIN1
GPIO176
R237
R239
R240
R245
2
2
2
2
C406 1
2 100P_0402_50V8J
APU_ALERT#_FCH
10/05 Add 100p(C406) on APU_ALERT#_FCH

Change R193, R188, R197, R198 to RP7
Michael 2010/12/23
Change RP7 to R196 , R197 , R199 , R236
Tock 2010/12/30
8/31 remove FCH SPI ROM
R416
10K_0402_5%
10/29 Add R415(@), R416(@) on GPIO56
GPIO56
B6
A6
A5
B5
C7
G27
Y2
R415
10K_0402_5%
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
1
1
C203
C204
<22> SATA_ITX_DRX_P0
<22> SATA_ITX_DRX_N0
HDD
1
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Change R199, R196, R187, R192 to RP8

Michael 2010/12/23
Change RP8 to R237 , R239 , R240 , R245
Tock 2010/12/30
2010/11/09
Issued Date
Compal Secret Data
2012/11/09
Deciphered Date
A
Title
FCH-SATA/SPI
Custom
Date:
P1VE6 Schematics
Sheet
E
14
of
37
Rev
1.0
.1U_0402_16V7K
C249
C250
2.2U_0603_6.3V6K
L20
2
+VDDAN_11_USB C11
D11
VDDPL_33_USB_S
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
VDDAN_33_HWM_S
VDDXL_33_S
10U_0603_6.3V6M
22U_0805_6.3V6M
C228
C227
1U_0402_6.3V6K
C226
1U_0402_6.3V6K
.1U_0402_16V7K
+1.1VS
C223
SF000002Z00
10U_0603_6.3V6M
C221
C220
1U_0402_6.3V6K
C219
1U_0402_6.3V6K
C218
C217
.1U_0402_16V7K
.1U_0402_16V7K
C225
.1U_0402_16V7K
8/25 Change C222 from poly-cap to E-cap (SF000002Z00)
C238
+VDDIO_33_S
A21
D21
B21
K10
L10
J9
T6
T8
2.2U_0603_6.3V6K
8/23 Add R346 R347, +VDDIO_33, +VDDIO_33_S
R347
2
0_0603_5%
+3VALW
2
165mA
15mA
M8
58mA
A11
B11
+VDDIO_AZ
+1.1VALW
+VDDCR_11_USB
M21
+VDDPL33
46mA
L22
+VDDPL11
65mA
F19
+AVDD_USB
16mA
D6
+VDDAN33_HWM
5mA
L19
1
+1.1VALW
0_0805_5%
12mA
L21
+VDDXL_33_S
L20
C248
F26
G26
10U_0603_6.3V6M
VDDPL_11_SYS_S
L15 2
FBMA-L11-201209-221LMA30T_0805
C247
VDDPL_33_SYS
PLL
88mA
FBMA-L11-160808-221LMT_2P
M6
P8
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
M10
VDDIO_GBE_S_1
VDDIO_GBE_S_2
VDDIO_AZ_S
C222
330U_2.5V_M
V1
L7
L9
VDDCR_11_S_1
VDDCR_11_S_2
.1U_0402_16V7K
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
.1U_0402_16V7K
C245
C244
.1U_0402_16V7K
1U_0402_6.3V6K
C243
C242
1U_0402_6.3V6K
10U_0603_6.3V6M
C241
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
USB I/O
10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805
C246
+AVDD_USB
49mA
CORE S5
L18
+1.1VS
+VDDAN_11_CLK
K28
K29
J28
K26
J21
J20
K21
J22
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
C240
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
1U_0402_6.3V6K
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
534mA
+1.1VALW
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
+VDDPL_33_SATA AD14
1354mA
+3VALW
U26
V22
V26
V27
V28
V29
W22
W26
382mA
15mA
+AVDD_SATA
VDDPL_33_PCIE
2.2U_0603_6.3V6K
1115mA
+PCIE_VDDAN
AE28
1U_0402_6.3V6K
+VDDPL33_PCIE
C237
C232
C236
C235
VDDRF_GBE_S
VDDIO_33_GBE_S
+1.1VS
1
C239
.1U_0402_16V7K
1U_0402_6.3V6K
C234
C233
2
1
FBMA-L11-201209-221LMA30T_0805
22U_0805_6.3V6M
L17
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
22mA
3.3V_S5 I/O
2
+1.1VS
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
GBE LAN
AF22
AE25
AF24
AC22
SERIAL ATA
2
1
FBMA-L11-160808-221LMT_2P
+3VS
0.15mA
PCI EXPRESS
L16
.1U_0402_16V7K
2.2U_0603_6.3V6K
.1U_0402_16V7K
C231
.1U_0402_16V7K
C229
C230
1
R208
0_0402_5%
FLASH I/O
4.7U_0603_6.3V6K
+VDDIO_18_FC
2
0_0603_5%
N13
R15
N17
U13
U17
V12
V18
W12
W18
2.2U_0603_6.3V6K
.1U_0402_16V7K
C216
.1U_0402_16V7K
C214
C215
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
CLKGEN I/O
R207
1
GPIO I/F implemented: tied to +1.8V_S0

GPIO I/F not implemented: tied to
+1.8V_S0 or 0 ohm to ground
+1.8VS
.1U_0402_16V7K
C213
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
PCI/GPIO I/O
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
790mA
POWER
U5C
+VDDIO_33
C224
42mA
R346
2
0_0603_5%
CORE S0
22U_0805_6.3V6M
+3VS
C251
+3VS
FBMA-L11-160808-221LMT_2P
For 3V AZ device
+VDDPL11
HWM@ C260
L25
+VDDPL33
L27
2
1
FBMA-L11-160808-221LMT_2P
C262 1
2 2.2U_0603_6.3V6K
C257
C256
C255
1
R209
1
+3VS
2
0_0603_5%
1
2
R210
0_0603_5%
C258
2.2U_0603_6.3V6K
change +1.5V to +3VS and mount R210 reserve R209

11/26 Tock
Wake On Ring Not Implemented:

Tied to a +1.5V_S0 or +3.3V_S0 rail.
VDDIO_AZ_S and audio CODEC chip HD link IO power rail
should be at same voltage level/domain.
Compal Secret Data

2010/11/09
Issued Date
SD013000080
2012/11/09
Deciphered Date
B
9/3 Change L26 to L25(NONHWM@)
0_0603_5%
NONHWM@
C261
2
1
FBMA-L11-160808-221LMT_2P
HWM@
2.2U_0603_6.3V6K
+3VALW
2 2.2U_0603_6.3V6K
+3VS
+3VALW
@
L25
2
1
FBMA-L11-160808-221LMT_2P
C259 1
+VDDIO_AZ
+VDDAN33_HWM
L24
+1.1VALW
.1U_0402_16V7K
.1U_0402_16V7K
1U_0402_6.3V6K
2 2.2U_0603_6.3V6K
.1U_0402_16V7K
C252 1
C254
2
1
FBMA-L11-160808-221LMT_2P
L22
2
1
FBMA-L11-201209-221LMA30T_0805
C253
+3VS
+1.1VS
1U_0402_6.3V6K
+VDDPL_33_SATA
L23
22U_0805_6.3V6M
+AVDD_SATA
Title
FCH PWR
Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
E
15
of
37
U5D
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
VSSPL_SYS
PCI_CLK1
PCI_CLK3
PCI_CLK4
LPC_CLK0 CLK_PCI_DB
ALLOW PCIE
GEN2
USE
DEBUG
STRAP
Reserved
internal EC
ENABLE
Internal
CLKGEN
Mode
*
IGNORE
DEBUG
STRAP
internal EC
DISABLE
CLKGEN Mode
Internal
R215
10K_0402_5%
2
1
+3VS +3VALW +3VALW
R213
10K_0402_5%
2
1
+3VS
R212
10K_0402_5%
2
1
+3VS
External
CLKGEN
Mode
R214
10K_0402_5%
2
1
FORCE PCIE
GEN1
PULL
LOW
9/13 Change R211 from mount to @, R216 from @ to mount

9/13 Change R211 from @ to mount, R216 from mount to @
<12>
<12>
<12>
<12>
<12>
PCI_CLK1
PCI_CLK3
PCI_CLK4
LPCCLK0
CLK_PCI_DB
R220
10K_0402_5%
2
1
VSSAN_HWM
M19
PULL
HIGH
Check Internal PU/PD
R219
10K_0402_5%
2
1
EFUSE
REQUIRED STRAPS
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
R218
10K_0402_5%
2
1
Y4
D8
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
R211
10K_0402_5%
2
1
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
GND
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
R216
10K_0402_5%
2
1
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
R217
10K_0402_5%
2
1
M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
DEBUG STRAPS
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
ILA
AUTORUN
Enabled
FC PLL
bypassed
Disable I2C
ROM
Required Setting
<12>
<12>
<12>
<12>
<12>
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PULL
LOW
BYPASS
PCI PLL
Getting Value
from I2C EPROM
Reserved
Check AD29,AD28 strap function
Issued Date
2010/11/09
Deciphered Date

2012/11/09
Title
5
check default
Compal Secret Data
R225
2.2K_0402_5%
2
1
ILA AUTORUN Selects

Disabled
FC PLL
PCI_AD23
Enable ROM Straps
PCI_AD24
R224
2.2K_0402_5%
2
1
USE internal
PLL generated
PLL CLK
PCI_AD25
R223
2.2K_0402_5%
2
1
PULL
HIGH
PCI_AD26
R222
2.2K_0402_5%
2
1
PCI_AD27
R221
2.2K_0402_5%
2
1
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
FCH-VSS/Strap
Size
B
Date:
Document Number
P1VE6 Schematics
Sheet
1
16
of
37
Rev
1.0
11/04 Change RA19 RA20 from 47k to 10k
+3VS_AUDIO
<26>
1
RA19
BEEP#
2
33_0402_5%
MONO_IN
change RA19 from 10K to 33 ohm

Tock 2011/02/11
10U_0603_6.3V6M
1
1
RA32
1
RA54
+5VS
CA21
CA20
2
2
0.1U_0402_16V4Z
10/26 Remove DA4 CA46 CA47 RA23 RA24
Change RA54 package to 0603

Michael 2010/11/18
2
0_0603_5%
CA12
1
CA24
2
0.1U_0402_16V4Z
10/12 Change RA40 to 0.1 ohm (1206)
CA14
2 0.1U_0402_16V4Z
28
Add INT Mic circuit on port F

Tock 2010/11/26
33
34
RA17
2
MIC0_R
CA42 1
100_0402_1%
CA43 1
change RA17 from 0 ohm to 100 ohm

Tock 2011/01/03
<24> MIC1_L
<24> MIC1_R
CA2
1U_0402_6.3V6K
MIC1_L
CA38 1
MIC1_R
CA39 1
41
42
22
SPK_OUT_L+
PORTD_R
SPK_OUT_LPORTE_L
SPK_OUT_R+
PORTE_R
SPK_OUT_RPORTF_L
PORTB_L
PORTF_R
PORTB_R
FLY_P
23
2 MIC1_C_L
2.2U_0603_6.3V6K
2 MIC1_C_R
2.2U_0603_6.3V6K
35
36
37
FLY_N
SDATA_IN
SDATA_OUT
PORTC_L
SYNC
PORTC_R
RESET#
C_BIAS
BIT_CLK
20 mil
MIC_PLUG#
MONO_IN
2
1
<26> EC_MUTE#
RA34 39.2K_0402_1%
Add net GPIO_0 by vender review

Tock 2011/01/03
<24>
SENSEA
9/7 Add 0.1U (CA50) between GND & GNDA
1
CA51
2
0.1U_0402_16V4Z
1
CA52
2
0.1U_0402_16V4Z
1
CA53
2
0.1U_0402_16V4Z
DMIC_3/4
PCBEEP
DMIC_CLK0
EXT_MUTE#
DMIC_1/2
44
43
48
+AVEE
12
47
GPIO_0
20 mil
2
0.1U_0402_16V4Z
13
CA16
CA17
CA18
A:
B:
C:
D:
E:
F:
G:
J:
H:
GND
2
0.1U_0402_16V4Z
24
49
SENSE A
SENSE B
GPIO1/SPK_MUTE#
GPIO2/SPDIF2
1000P_0402_50V7K
10/26 Remove SPKR+ SPKR- function

14
SPKL+
16
SPKL-
19
SPKR+
10/28 Reserve CA57 CA58 for EMI
SPKR-
17
39
MIC2_C_L 1
40
MIC2_C_R 1
RA16
MIC2_R
2 CA40
2.2U_0603_6.3V6K
2 CA41
2.2U_0603_6.3V6K
COM_MIC
100_0402_1%
1
RA27
2
33_0402_5%
HDA_SDIN0 <13>
@
HDA_SDOUT_AUDIO <13>
2 CA48
22P_0402_50V8J
@
<13>
1
2 CA36
22P_0402_50V8J
HDA_RST_AUDIO# <13>
HDA_BITCLK_AUDIO_R 1
2
HDA_BITCLK_AUDIO <13>
RA28
0_0402_5%
1
2 CA31
22P_0402_50V8J
@
DMIC_CLK_R
11
7
Remove CA57 , CA58

Tock 2010/11/29
9/1 Add CA49 RA41 on HP_SENSE

HDA_SDIN0_AUDIO
6
10
11/01 Change CA57, CA58 from @ to mount
COM_MIC <24>
38
08/31 Reserve CA48(22P) on HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO
9/6 UA1 Pin 1 link to GNDA

9/7 Change UA1 Pin1 to GND
9/13 Add RA49 for DMIC
Layout Note: close to UA1
@
1
RA49
DMIC_CLK0
2
90.9_0402_1%
DMIC_DATA0
9/13 Add RA50~RA53 for DMIC
RA51 1
2 0_0402_5%
DMIC_CLK <4,9>
RA53 1
2 0_0402_5%
DMIC_DATA <9,26>
0.1U_0402_16V4Z
1
RA29
2
0_0402_5%
EAPD
10/01 Remove RA50,R52
<26>
Add INT Mic circuit on port F

Tock 2010/11/26
20 mil
SPDIFO
FILT_1.8
AVEE
FILT_1.65
EP_GND
AVDD_3.3
CX20584-21Z_QFN48_7X7
CA10
46
45
GPIO0/EAPD#
CA11
2
10U_0603_6.3V6M
+FILT_1.8V
5
32
+FILT_1.65V
30
+LDO_OUT_3.3V
1
CA6
0.1U_0402_16V4Z 2
1U_0402_6.3V6K
0.1U_0402_16V4Z
1
1
+LDO_OUT_3.3V CA1
20 mil
1
CA7
CA9
2
0.1U_0402_16V4Z
10U_0603_6.3V6M
1
@
CA8
RA26
2
20 mil
+LDO_INT_MIC
RA42
1
2
1K_0402_5%
CA27
10U_0805_10V6K
10K_0402_5%
RA15
2.2K_0402_5%
CA5
2 10U_0603_6.3V6M
+LDO_OUT_3.3V
INT_MIC0 <24>
10/11 Update UA1 PN:SA000034020

Remove RA36,RA37,RA38,RA39
Add CA51,CA52,CA53,CA54
by vender review
Tock 2010/12/08
10/12 Update UA1 PN:SA000034010 (-11Z)

12/08 Update UA1 PN:SA000034020 (-21Z) Tock
2010/11/09
Issued Date
Compal Secret Data
2012/11/09
Deciphered Date
GNDA
5
CA47
Headphone jack (jack shared with S/PDIF)

Internal MIC (mono or stereo)
Microphone/LI/LO jack
Line Out jack (Optional)
Line In jack (Optional)
Internal AMIC
Internal stereo speakers
Internal stereo digital mic (Optional)
S/PDIF (jack shared with headphone)
INT_MIC0
1
CA54
1
2
RA18 10K_0402_1%
COM_MIC_PLUG# 2
1
RA33 20K_0402_1%
1
CA50
Port
Port
Port
Port
Port
Port
Port
Port
Port
<24> MIC_PLUG#
<24> COM_MIC_PLUG#
HP_PLUG#
2
5.11K_0402_1%
+3VS_AUDIO
<24> HP_PLUG#
CA15
20
15
31
18
RPWR5.0
LPWR5.0
AVDD_5V
21
29
AVDD_HP
PORTD_L
B_BIAS
+MIC1_VREFO
1
RA7
10U_0805_10V6K
1
2 MIC0_C_L
2.2U_0603_6.3V6K
2 MIC0_C_R
2.2U_0603_6.3V6K
1
PORTA_R
CLASSDREF
27
PORTA_L
DVDD_3.3
26
VDD_IO
HP_RIGHT
VAUX_3.3
<24> HP_RIGHT
25
Port Configuration
12/08 Change RA40 to 0 ohm (1206) Tock
10U_0805_10V6K
UA1
INT_MIC0 1
0.1U_0402_16V4Z
1
CA23
2 10U_0603_6.3V6M
HP_LEFT
CA46
9/6 Update QA2 symbol
+CLASSD_5V
1
+3VS_VAUX
<24> HP_LEFT
10/11 Change RA40 to 0 ohm (1206)
20 mil
2
0.1U_0402_16V4Z
Delete JSPK1
2010/12/15 Tock
11/17 Change CA13 CA17 CA18 package from 0603 to 0805
0.1U_0402_16V4Z
CA22
1000P_0402_50V7K
1
CA45
11/16 Change CA5,CA8,CA11,CA13,CA17,CA18,CA19,CA23,CA25, package from 0805 to 0603

CA13
10U_0805_10V6K
60 mil
+3VS_AUDIO
1000P_0402_50V7K
5
6
G1
G2
10/28 Add JSPK1 (2 pin)
RA40
0_1206_5%
CA3
9/3 Change CA38~ CA43 from 4.7U to 2.2U

Change RA16 from 1k to 100 ohm
0.1U_0402_16V4Z
1
1
+5VS_AVDD
+VDD_IO
1U_0402_6.3V6K
1
2
3
4
DA4
PJDLC05C_SOT23-3
10/28 Add DA4 CA46 CA47 RA23 RA24
60 mil
20 mil
2
0_0402_5%
DA5
PJDLC05C_SOT23-3
CA19
2
0_0402_5%
CA34
100P_0402_50V8J
9/25 Add RA54~RA56
+3VS_DVDD
0.1U_0402_16V4Z
1
1
2
3
4
ACES_88266-04001
CONN@
08/21 Follow PAV70
+3VS_AUDIO
1
RA31
JSPK2
SPK_L+
SPK_LSPK_R+
SPK_R-
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
CA44
1000P_0402_50V7K
40 mil
+1.5VS
RB751V-40_SOD323-2
@
CA32
0.1U_0402_16V4Z
reserve DA21,DA22 by vender review

Tock 2010/12/08
+3VS_AUDIO
RA21
10K_0402_5%
2
2
2
2
2
1
@ DA21
Change RA31/ RA32 package to 0402

Michael 2010/11/18
2
10K_0402_5%
1
RA20
<13> FCH_SPKR
1
1
1
1
20mil
0.1U_0402_16V4Z
Remove RA55,RA56 and add RA340 for power consumption

11/26 Tock
RA22
RA25
RA23
RA24
2
0_0805_5%
CA33
1
RA340
+3VS
SPKL+
SPKLSPKR+
SPKR-
RB751V-40_SOD323-2
Int. Speaker Conn.
@ DA22
08/19 Follow NTUC0
Title
Audio Codec CX20584

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
17
of
37
Power On strapping
+3V_LAN
Pin
LAN_CLKREQ#_R
PLT_RST#
Description
LED0
L:Over Clock Disable
UL1
TX_P
22
TX_N
<12> PCIE_FTX_C_DRX_P2
28
RX_P
<12> PCIE_FTX_C_DRX_N2
29
RX_N
26
25
<12> CLK_PCIE_LAN
<12> CLK_PCIE_LAN#
1
RL12
<13> LAN_CLKREQ#
LAN_CLKREQ#_R
2
0_0402_5%
<12,20,21,26> PLT_RST#
<26> LAN_WAKE#
1
RL14
12
13
14
15
CLKREQ#
2 49.9_0402_1%
CL550
RL526
2 49.9_0402_1%
CL592
MDI1+
RL529
2 49.9_0402_1%
CL551
MDI1-
RL528
2 49.9_0402_1%
CL593
11
LAN_WAKE#
WAKE#
VDD33
+3V_LAN
LX
+1.7_LX
VDDCT
VDDCT_REG
6
5
+1.7_VDDCT
+1.7_VDDCT_REG
30
+1.1_DVDDL
2
0_0402_5%
18
19
SMCLK
SMDATA
TESTMODE
GND
LAN_X1
LAN_X2
CL11
27P_0402_50V8J
8
9
XTLO
XTLI
21
LAN_RBIAS
RL522
2 2.37K_0402_1%
CL552 1
1000P_0402_50V7K
2
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
Close Pin 11
2 0.1U_0402_16V4Z
W=40mils
+3V_LAN
DVDDL_REG
RL527
MDI0-
RBIAS
LAN_X2
CL10
27P_0402_50V8J
MDI0+
PERST#
20
33
25MHZ_20PF_7A25000012
TRXP0
TRXN0
TRXP1
TRXN1
ACTIVITY
LAN_LINK#
YL1
1
31
32
16
PLT_RST#
2010.08.21 Follow PAWGC

LAN_X1
REFCLK_P
REFCLK_N
17
LED[0]
LED[1]
LED[2]
NC
AVDDH_REG
10
AVDDL
AVDDL
AVDDL_REG
24
27
7
CL562
1U_0402_6.3V6K
CL563
0.1U_0402_16V4Z
CL571
1U_0402_6.3V6K
CL572
0.1U_0402_16V4Z
+2.7_AVDDH
+3VALW
RL13 1
1A
2 0_0603_5%
@ QL1
AP2301GN-HF_SOT23-3
CL5
+1.1_AVDDL
+1.1_AVDDL
LL39
LAN_CLKREQ#
@
1
SWR@
LAN_CLKREQ#_R
RB751V-40_SOD323-2
CL548
1
2
4.7UH_SIA4012-4R7M_20%
SWR@
DL8
CL569
CL7
CL1
CL34
@
close to LAN Pin 1
0.1U_0402_16V4Z
CL567
0.1U_0402_16V4Z
CL568
RL18 1
2
2 10K_0402_5%
EN_WOL# <26>
CL41
@
1
LDO@
+1.7_VDDCT
0.1U_0402_16V4Z
+1.7_LX
0.1U_0402_16V4Z
CL597
CL419
100P_0402_50V8J
CL547
Reserve CL419 for PLT_RST#

Michael 2010/11/18
10U_0805_10V6K
PLT_RST#
1U_0402_6.3V6K
AR8158-BL1A-RL_QFN32_4X4
CL8
10U_0603_6.3V6M
CL9
10U_0603_6.3V6M
CL6
<12> PCIE_FRX_DTX_N2
D
PCIE_C_RXP1
.1U_0402_16V7K
PCIE_C_RXN1
.1U_0402_16V7K
23
<12> PCIE_FRX_DTX_P2
Chip Default
H:Over Clock Enable
1U_0402_6.3V6K
1 4.7K_0402_5%
1 4.7K_0402_5%
0.1U_0402_16V4Z
@
@
1000P_0402_50V7K
RL15 2
RL16 2
0.1U_0402_16V4Z
+1.7_VDDCT_REG
RL520 1
2 0_0402_5%
SWR@
CL549
0.1U_0402_16V4Z
LL2
CL564 LDO@
1U_0402_6.3V6K
CL427
1 1U_0402_6.3V6K
+1.7_VDDCT_R
+1.7_VDDCT
BLM18AG601SN1D_2P
TL1
Reserve DL8 for LAN_CLKREQ#

Tock 2011/01/05
MDI1+
MDI1CL436
CL554
CL437
CL555
1
2
3
4
5
6
7
8
1 0.1U_0402_16V4Z
1000P_0402_50V7K
MDI0+
MDI0-
1 0.1U_0402_16V4Z
1000P_0402_50V7K
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0
16
15
14
13
12
11
10
9
RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-
350uH_NS0013LF
RJ45_MIDI1+
3
4
RJ45_MIDI1-
LED_YELLOW_A1
PR1LED_YELLOW_A2
LED_GREEN_B1
PR3-
PR2-
LAN_ACTIVITY#_R
10
2
RL17
@
CL33 1
PR3+
LED_GREEN_B2
PR4+
GND
GND
change T1 to SP050005900 <MHPC>

but use BOTH_GST5009-LF_24P footprint
2010/12/14 Tock
PR2+
CONN@
PR1+
RL19
12
LAN_SK_LAN_LINK#_1
change TL1 PN to SP050006E00

2011/02/11 Tock
2 470P_0402_50V7K
LAN_LINK#
11
ACTIVITY
1
511_0402_1%
1
RJ45_MIDI0-
RL11 1
511_0402_1%
+3V_LAN
5.1K_0402_5%
13
14
PR4-
JRJ45
RJ45_MIDI0+
CL35 @
470P_0402_50V7K
CL32
470P_0402_50V7K
@
SANTA_130451-F
For EMI.
LANGND
change JRJ45 to DC234005300

2010/12/14 Tock
CL40
0.1U_0402_16V4Z
CL39
0.1U_0402_16V4Z
CL38
CL15
1000P_1206_2KV7K
DL1
RJ45_GND
1000P_1206_2KV7K
LANGND
LANGND
RL7
RJ45_CT0
75_0402_5% 2
RL8
RJ45_CT1
Remove DL2~DL13
2010/12/06 Tock
RJ45_GND
PJDLC05C_SOT23-3
LL3
1
MCK3225201YZF_2P
2
Compal Secret Data
Issued Date
2010/11/09
2012/11/09
Deciphered Date
5
75_0402_5% 2
Title

LAN AR8158

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
18
of
37
+CARDPWR
+CARDPWR
30mil
30mil
RC6
100K_0402_5%
@
1
CC8
0.1U_0402_16V4Z
CC9
0.1U_0402_16V4Z
close pin 11
CC7
0.1U_0402_16V4Z
close pin 18
Card Reader Connector
close pin 22
JREAD1
+CARDPWR
22
XD-VCC
XDD0_SDCLK_MSD2
XDD1_MSD0
XDD2_SDCMD
XDD3
XDD4_SDD3_MSD1
XDD5_SDD2
XDD6_MSBS
XD_D7
30
29
28
27
26
25
24
23
XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7
XDWE#_SDCD#
XDWP#
XDALE_MSD3
XD_CD#
XDDRY_SDWP_MSCLK
XDRE#_MSINS#
XDCE#_SDD1
XDCLE_SDD0
33
32
34
39
38
37
36
35
31
40
CONN@
SD4-VDD
MS9-VCC
SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP
XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE
SD6-VSS
SD3-VSS
+CARDPWR
RC7 @
XDD0_SDCLK_MSD2
XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2
XDD4_SDD3_MSD1
XDD2_SDCMD
XDWE#_SDCD#
XDDRY_SDWP_MSCLK
9
4
3
21
19
16
1
2
@
CC11
4.7P_0402_50V8C
0_0402_5%
Reserve RC7 , CC11 , RC8 , CC12 for EMI

Tock 2010/12/28
6
13
2010.11.02 Del LED circuit
RC8 @
MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS
XD GND
XD GND
41
42
11
18
SD CD/WP GND
SD CD/WP GND
XDDRY_SDWP_MSCLK
XDD1_MSD0
XDD4_SDD3_MSD1
XDD0_SDCLK_MSD2
XDALE_MSD3
XDRE#_MSINS#
XDD6_MSBS
17
10
8
12
15
14
7
5
20
@
CC12
4.7P_0402_50V8C
0_0402_5%
Remove CC13 by vender review

12/08 Tock
T-SOL_144-1300002600_NR
2010.08.19 Copy Symbol from NCQF0

change JREAD1 to SP07000LW00 for Layout
2010/01/05 Tock
change JREAD1 to SP07000NV00

2010/12/14 Tock
+3VS
+3VS_CR
+3VS
JR1 @
2
30mil
RTS5138
1
RC1
10mil
2
6.2K_0603_1%
<13> USB20_N6
<13> USB20_P6
30mil
2
2
3
REFE
GPIO0
DM
DP
+3VS_CR
+CARDPWR
VREG
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
XD_CD#
CC3
2
1U_0402_6.3V6K
CC10
1
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
CC1
2
10mil
USB20_N6
USB20_P6
XDDRY_SDWP_MSCLK_L 8
XDRE#_MSINS#
9
XDCE#_SDD1
10
XDCLE_SDD0
11
XDALE_MSD3
12
SP1
SP2
SP3
SP4
SP5
CLK_IN
XD_D7
25
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
RC3
XDD0_SDCLK_MSD2_L 1
RC4
CARD_LED#
MS_CLK
XD_RDY
CLK_48M_CR <12>
SP2
XD_RE#
SP3
XD_CE#
SD_D1
23
XD_D7
22
21
20
19
18
16
15
14
13
XDD6_MSBS
XDD5_SDD2
XDD4_SDD3_MSD1
XDD3
XDD2_SDCMD
XDD1_MSD0
XDD0_SDCLK_MSD2_L
XDWP#
XDWE#_SDCD#
SP4
XD_CLE
SD_D0
SP5
XD_ALE
SP6
XD_WE#
SP7
XD_WP
SP8
XD_D0
SP9
XD_D1
SP10
XD_D2
SP11
XD_D3
SP12
XD_D4
SD_D3
SP13
XD_D5
SD_D2
SP14
XD_D6
MS_INS#
RC2
22_0402_5%
MS_D3
CC4
10P_0402_50V8J
SD_CD#
Change net name from XDD5_SDD2_MS_D5 to XDD5_SDD2

11/26 Tock
CC5 @
4.7P_0402_50V8C
SD_CLK
MS_D2
MS_D0
SD_CMD
MS_D1
MS_BS
A
XDD0_SDCLK_MSD2
0_0402_5%
XD_D7
1
CC6 @
4.7P_0402_50V8C
2010/11/09
Issued Date
Compal Secret Data
Add RC3 , CC5 ,RC4 , CC6 by vender review for EMI sol.
12/08 Tock
2012/11/09
Deciphered Date
change CC5 , CC6 BOM structure to @

2011/01/03 Tock
5
SD_WP
SP1
CARD_LED# <22>
24
17
XDDRY_SDWP_MSCLK
0_0402_5%
MS
RTS5138-GR_QFN24_4X4
Close to chip
XDDRY_SDWP_MSCLK_L 1
RC5
10K_0402_5%
UR1
RREF
SD
XD_CD#
1 100P_0402_50V8J
EPAD
CC2
XD
Share Pin
JUMP_43X39
Title
CARD READER RTS5138

Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet
1
19
of
37
W=40mil
+3VS_WWAN
3G@
Reserve C293 for RF

Tock 2010/12/28
1
C293
22P_0402_50V8J
@
8/22 Reserve R335 (0 ohm 0805) Add net +1.5VS_WWAN
3G@
3G@
0.1U_0402_16V4Z
1
C270
1
C269
0.1U_0402_16V4Z
+3VS
9/3 Reserver +3VALW for BT (R378 R374)
8/31 Change MCP@ to 3G_MP@
3G@
C268
C266
2
1
C271
0.01U_0402_25V7K
R226
C272
47P_0402_50V8J <21,26> BT_ON#
10K_0402_5%
+3VS_WWAN
1
R227
2
0_1206_5%
1
R228
2
0_1206_5%
2
0_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WWAN_CLKREQ#
<13> WWAN_CLKREQ#
<12> CLK_PCIE_WWAN#
<12> CLK_PCIE_WWAN
C275 10U_0805_10V6K 3G@
1
2
+3VS_WWAN
WWAN_WAKEUP_R#
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
C284 2
3G@
1 56P_0402_50V8
R230
R231
3G@ 2
1
R232
0_0402_5%
5
6
9/1 Change R230 R231 from NON3G@ to mount

8/22 Update JBT1 Symbol from database (ACES_88266-04001_4P)
WWAN_LED# <21,22>
WLAN_LED# <21,22>
(9~16mA)
USB20_MINI_N
USB20_MINI_P
R246 1
R248 1
@
@
2 0_0402_5%
2 0_0402_5%
USB20_MINI_P
USB20_MINI_N
R250 1 3G@
R252 1 3G@
2 0_0402_5%
2 0_0402_5%
USB20_N3 <13>
USB20_P3 <13>
USB20_P9 <13>
USB20_N9 <13>
10/31 Add R417~R420 for co-lay USB port3 & port9

Change R419 R420 from mount to @ SW request (P0VE6-0045)

Michael 2010/12/23

Michael 2010/12/23
Swap USB net of RP10 for layout

Tock 2010/12/24
3

Tock 2010/12/30
PLT_RST#
+UIM_PWR
UIM_RST
UIM_CLK
USB20_P4
USB20_N4
R233
<13>
@
10K_0402_5%
2
C277
1 22P_0402_50V8J
22P_0402_50V8J
C276
UIM_RST
56P_0402_50V8
3G@ 1
G1
G2
FCH_SMCLK0 <7,8,13,21>
FCH_SMDAT0 <7,8,13,21>
54
JSIM1
W=20mil
UIM_VPP
2 0_0402_5%
2 0_0402_5%

Tock 2010/12/30
<13>
C279
1 3G@
1 3G@
WXMIT_OFF# <26>
PLT_RST# <12,18,21,26>
+UIM_PWR
UIM_DATA
3G@
1 100P_0402_50V8J
10/06 Remove C398

2 0_0402_5%
1
2
3
4
ACES_88266-04001
CONN@
USB20_MINI_N
USB20_MINI_P
WLAN_LED#_R
JBT1
1
2
3
4
USB20_P7
USB20_N7
<13> USB20_P7
<13> USB20_N7
10/04 Add 100p(C398) on UIM_RST
WXMIT_OFF#
R229 1 3G@
change JMIN1 to SP07000QC00

2010/12/14 Tock
3G@
C285 2
1 56P_0402_50V8
C278 2
Close to WWAN CONN
+UIM_PWR
Modifiy 05/11
1
2
3
4
5
6
7
8
9
10
11
VCC
RST
CLK
Reserved
GND
VPP
I/O
Reserved
CD
3G@
1
C479
100P_0402_50V8J
+3VALW
3G@
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z
R234
10K_0402_5%
GND
GND
@
2
C283 2
9/9 Remove D9
+1.5VS_WWAN
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
PLAST_SSM010-52-B-K
3G@
C282 2
1 1U_0402_6.3V6K
CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_BT
150U_B_6.3VM_R40M
JMINI1
@
1
R412
C274
BT@
C273
+3V_BT
1
9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

FCH_PCIE_WAKE#
+3VS_WWAN
+3VALW
3G@
10/27 Add R412 (0 ohm) on FCH_PCOE_WAKE#
+3VS_BT
Q13 BT@
AO3413L_SOT23-3
+3VS
C402
100P_0402_50V8J
06/29
BT MODULE CONN
BT@
R378
0_0603_5%
R374
0_0603_5%
@
+3VALW +3VS
10U_0805_10V6K
BT@
2011/02/11 Change Q13 PN to SB000006R10
C267 BT@
0.1U_0402_16V4Z
BT@
8/25 Change C269,C275 to SE000004880 Standard Part
Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T
10/04 Add 100p(C402) on BT_ON#
3G@
C263
+1.5VS_WWAN
2
0_0805_5%
3G@
1
C265
C264
0.1U_0402_16V4Z
3G@
1
R335
3G@
1
3G@
1
+1.5VS
4.7U_0603_6.3V6K
3G@
47P_0402_50V8J
Mini-Express Card for WWAN
+1.5VS_WWAN
W=40mil
0.01U_0402_25V7K
ACON_SCR4W-8K1000
CONN@
<26> WWAN_WAKEUP#
1
R235
WWAN_WAKEUP_R#
2
0_0402_5%
change JSIM1 to SP07000NW00

2010/12/28 Tock
@
4
C280 2
1 22P_0402_50V8J
UIM_CLK
4
8/22 Update JP1 Symbol from database (TAITW_PMPAT7-08GLBS1N14H0_9P)

3G@
C281 2
1 22P_0402_50V8J
Reserve for SIM card does not meet rise time

and pull-up is needed.
10/06 Change C278 to 100p
2010/11/09
Issued Date
Compal Secret Data
Deciphered Date
2012/11/09
A
Title
Mini-Card/BT CONN
Size
Document Number
Rev
1.0
P1VE6 Schematics
Date:
Sheet
E
20
of
37
EC_TX_P80_DATA
EC_RX_P80_CLK
<26> EC_TX_P80_DATA
<26> EC_RX_P80_CLK
R253 1
R254 1
2 0_0402_5% EC_TX_P80_DATA_R
2 0_0402_5% EC_TX_P80_CLK_R
Mini-Express Card for WLAN

Michael 2010/12/23
Michael 2010/12/30
W=40mil
+3VS_WLAN
1
C286
4.7U_0603_6.3V6K
W=40mil
+1.5VS_WLAN
1
C287
0.1U_0402_16V4Z
1
C288
47P_0402_50V8J
1
C289
4.7U_0603_6.3V6K
1
C290
0.1U_0402_16V4Z
1
R336
+1.5VS
2
0_0805_5%
+1.5VS_WLAN
C291
47P_0402_50V8J
8/22 Reserve R336 (0 ohm 0805) Add net +1.5VS_WLAN

C
change JMIN2 to SP07000QC00

2010/12/14 Tock
PLT_RST#
9/2 Change ICH_PCIE_WAKE# to FCH_PCIE_WAKE#

2 R238
1
@ 0_0402_5%
<20,26> BT_ON#
<13> WLAN_CLKREQ#
<12> CLK_PCIE_WLAN#
<12> CLK_PCIE_WLAN
+3VS_WLAN
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS_WLAN
J2
JUMP_43X79
@
1 1
2 2
+3VS
C446
100P_0402_50V8J
+1.5VS_WLAN
Add C446 on PLT_RST#

Tock 2010/12/28
WL_OFF# <26>
PLT_RST# <12,18,20,26>
R255 1
R256 1
Change RP12 to R255 ,R256

Tock 2010/12/30
2 0_0402_5%
2 0_0402_5%
FCH_SMCLK0 <7,8,13,20>
FCH_SMDAT0 <7,8,13,20>
USB20_N8 <13>
USB20_P8 <13>
WWAN_LED#_R
1 R241
2
0_0402_5%
R242
for switching noise
9/20 Add R393 R394 for SMBus

9/17 Remove R239,R240
WWAN_LED# <20,22>
0_0402_5%
1
EC_TX_P80_DATA_R
EC_TX_P80_CLK_R
1
C292
10U_0603_6.3V6M
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CONN@
JMINI2
53
GND1
GND2
(9~16mA)
54
WLAN_LED# <20,22>
PLAST_SSM010-52-B-K
R243
100K_0402_5%
5/12
6/1
6/12
6/26
7/01
Update WLAN connector(the same as KAV60)

Revised 37 39 41 42 43 to NC
Update connector to DC040006S00
Update JMINI1 footprint
update pin 23,25,31,33

Title
WLAN
Size
Document Number
CustomP1VE6 Schematics
Date:
5
WLAN
Rev
1.0
LA-6222P
Sheet
1
21
of
37
+3VS
1
LED PCB CONN

JLED1
GND
GND
HDD_LED#
<14> HDD_LED#
13
14
Y
A
2
U8
2
<19> CARD_LED#
+3VS
W=40mil
<20,21> WWAN_LED#
<20,21> WLAN_LED#
2
G
D
MEDIA_LED#
MEDIA_LED#
R373
10K_0402_5%
+3VS
PWR_LED#
PWR_SUSP_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
1
2
3
4
5
6
7
8
9
10
11
12
<26>
<26>
<26>
<26>
1
2
3
4
5
6
7
8
9
10
11
12
+3VALW
Q34
SSM3K7002FU_SC70-3
2
G
W=40mil
Q35
SSM3K7002FU_SC70-3
ACES_85201-1205N
CONN@
8/22 Update JP2 Symbol from database (ACES_85201-1605N_16P)

8/24 Update JLED1 Symbol from database (ACES_85201-1205N_12P) & Update pin definition
9/1 Add LED Circuit (LED2~4(SC597UDB000)LED5(SC5191NB000), R360~R369, Q33)
9/1 Add R373, Q34, Q35 for MEDIA_LED#
9/1 Change All LED power to 5V

9/9 Change LED2~4 footprint to LED_HT-297DQ-GQ_4P
9/11 Remove LED portion
Add C11~C14 from HDD board

2011/01/07 Tock
+5VS_HDD
0.1U_0402_16V4Z
1
C12
1000P_0402_50V7K
C11
10U_0805_10V6K
1
1
C13
C14
1U_0402_6.3V6K
SATA HDD Conn.
8/22 Change C298 from 10U 6.3V to 10U 10V

8/22 Reserve R337 R338 Add net +3VS_HDD,+5VS_HDD
9/1 Change Q33 to SB000009610(SSM3K7002FU_SC70-3)
change JHDD1 to SP01000E400 , delete C293 ~ C298
2010/12/14 Tock
JHDD1
W=40mil
+3VS
1
R337
2
0_0805_5%
+3VS_HDD
+5VS
1
R338
2
0_0805_5%
+5VS_HDD
<14> SATA_ITX_DRX_P0
<14> SATA_ITX_DRX_N0
<14> SATA_DTX_C_IRX_N0
<14> SATA_DTX_C_IRX_P0
1
2
3
4
5
6
7
8
9
10
11
12
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
+3VS_HDD
+5VS_HDD
W=100mil
1
2
3
4
5
6
7
8
9
10
11
12
Modify JHDD1 pin define

2010/12/15 Tock
GND
GND
13
14
ACES_85201-1205N
CONN@
Issued Date
Compal Secret Data
2010/11/09
2012/11/09
Deciphered Date
A
Title
Size
B
SATA CONN./LED/B CONN./BATT CONN.

Document Number
Rev
1.0
P1VE6 Schematics
Date:

G
Sheet
22
H
of
37
ON/OFF Button
8/26 Change D11 to SC600000B00 Standard Part
G
G
6
5
updated SW1 symbol for SN100002K00

2010/12/06 Tock
ON/OFFBTN#
+3VALW
3
SW1
EVQPLMA15_4P
9/20 Remove R245,R248,D12
R247
100K_0402_5%
FOR EMI
D11
ON/OFF#
ON/OFFBTN#
ON/OFF# <26>
51_ON#
51_ON# <30>
BAV70W_SOT323-3
PWR_LED1#
C299 1
2 @ 100P_0402_50V8J
ON/OFFBTN#
C301 1
2 @ 100P_0402_50V8J
place close to PR4

C300
51_ON#
1000P_0402_50V7K
1
Q14
SSM3K7002FU_SC70-3
10K_0402_5%
9/6 Change D13 from mount to @
C478
100P_0402_50V8J
Reserve C478 for 51_ON#

Tock 2011/01/07
2
G
R249
EC_ON
1
EC_ON
EC_ON
<26>
C473
100P_0402_50V8J
Reserve C473 for EC_ON

Tock 2011/01/07
10/05 Remove D13
9/1 Remove LED2 LED3 circuit, Change 70@ to mount
9/24 Change U9 to SA00001TC00
9/20 Add LED2 LED3 Circuit

9/21 Remove LED2 LED3 Circuit
LID Switch
W=20mil
+3VS
change R251 from 51 ohm to 220 ohm

2011/03/07 Tock
1
(BLUE)
C302
0.1U_0402_16V4Z
R251
100_0402_1%~N
VDD
AH180WG-7_SC59-3
GND
change R251 from 220 ohm to 100 ohm

2011/03/16 Tock
+3VALW
LID_SW# <26>
1
U9
LED1
HT-191NB5-DT BLUE 0603
C303
PWR_LED1#
10P_0402_50V8J
OUTPUT
LED2
HT-191NB5-DT BLUE 0603
PWR_LED1# <26>
10mil
Issued Date
Compal Secret Data
2010/11/09
Deciphered Date
2012/11/09
Title
Size
B
Date:
ON/OFF / PWR SW/ LID SW

Document Number
P1VE6 Schematics
Sheet
23
of
37
Rev
1.0
KSO15
KSO14
KSO13
KSO12
C398
C419
C448
C449
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
Change CP4 to C461 , C458 , C460 , C459

Change CP5 to C465 , C462 , C464 , C463
Change CP6 to C469 , C466 , C468 , C467
Tock 2010/12/30
KSO7
KSO6
KSO5
KSO4
C461
C458
C460
C459
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
KSI5
KSO9
KSI4
KSO8
C453
C450
C452
C451
1
1
1
1
C457
C454
C456
C455
2
2
2
2
1
1
1
1
2
2
2
2
KSI[0..7]
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
KSO3
KSI3
KSO2
KSO1
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
KSI[0..7]
C465
C462
C464
C463
KSO0
KSI2
KSI1
KSI0
C469
C466
C468
C467
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
To TP/B Conn.
JKB1
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI0
KSI1
KSI2
KSO0
KSO1
KSO2
KSI3
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSI4
KSO9
KSI5
KSI6
KSO10
KSO11
KSI7
KSO12
KSO13
KSO14
KSO15
Swap KB signal
for layout
Tock
2010/12/24
KSI7
KSO11
KSO10
KSI6
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
8/22 Update JP3 Symbol from database (ACES_85201-0605N_6P)

8/22 Reserve R339 (0 ohm 0402) Add Net name +5VS_TP
G2
G1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8/24 Update JTP1 Symbol from database (ACES_85201-0405N_4P)

& Update pin definition
W=20mil
<26> TP_DATA
<26> TP_CLK
+5VS
0_0402_5%
TP_DATA
TP_CLK
2
1
+5VS_TP
R339
Change CP1 to C398 , C419 , C448 , C449

Change CP2 to C453 , C450 , C452 , C451
Change CP3 to C457 , C454 , C456 , C455
Tock 2010/12/30
JTP1
1
2
3
4
5
6
1
2
3
4
G1
G2
ACES_85201-0405N
CONN@
D14
@
PJDLC05C_SOT23-3
ACES_85202-24051
CONN@
<26>
8/22 Update JKB1 Symbol from database (ACES_85202-24051_24P)

8/23 Update KB pin definition
KSO[0..15]
KSO[0..15] <26>
INT_KBD Conn.
Combo Jack
CMBS@ QA36
MMBT3906H_SOT23-3
RA14 1
CMBS@
+LDO_OUT_3.3V
2 0_0402_5%
COM_MIC_R
change RA59 from 750 to 220 ohm

by vender review for bo bo noise
Tock 2011/03/16
RA35
2.2K_0402_5%
NCMBS@
RA13
2
G
CMBS@
change RA57 from 47K to 15K ohm

by vender review for bo bo noise
Tock 2011/03/16
CA26
1U_0603_10V6K
CMBS@
JIO1
<17> INT_MIC0
<17>
MIC1_L
<17>
MIC1_R
+MIC1_VREFO
<17> MIC_PLUG#
<17> COM_MIC
<17> HP_LEFT
<17> HP_RIGHT
RA14
change RA12 BOM structure to @

by vender review for pop issue
Tock 2010/12/08
Add net INT_MIC0 on JIO1 pin 2

Tock 2010/11/26
1K_0402_5%
NCMBS@
<25,26> USB_ON#
COM_MIC_PLUG#
RA9
0_0402_5%
RA41
20K_0402_5%
3
1
0_0402_5%
QA4
BSS138_NL_SOT23-3
QA1B
2N7002KDW H_SOT363-6
CA49 @
0.1U_0402_16V4Z
USB_ON#
USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB_OC0#
USB20_P0
USB20_N0
USB20_P1
USB20_N1
RA55
10K_0402_5%
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
Add IO connector
Michael 2010/11/18
CONN@
ACES_85202-24051
COM_MIC
Add QA4,RA55,CA29,RA36 for Internal Mic

can't record issue . Tock 2011/02/21
CA29
1U_0603_10V6K
A
remove CA4 change QA1 , QA2 from SB501380020 <BSS138> to SB00000EO10 <2N7002>.
Tock 2011/02/24
Compal Secret Data
change CA49 BOM structure to @

change RA41 from 47K to 4.7K
Tock 2010/12/08
2
G
3
<13> USB_OC0#
<13>
<13>
<13>
<13>
QA1A
2N7002KDW H_SOT363-6
RA36
1
HP_SENSE
+5VS
2
HP_PLUG# <17>
COM_MIC_PLUG# <17>
change RA9 from 20K to 0 ohm

Tock 2011/03/03
HP_PLUG#
MIC_PLUG#
COM_MIC
HP_LEFT
HP_RIGHT
+5VALW
11/17 Add Combo solution circuit for P0VE6 "POPO" noise

change RA52,DA10,CA26 BOM structure to @
Tock 2010/12/08
INT_MIC0
MIC1_L
MIC1_R
HP_SENSE
RA57
15K_0402_1%
QA3
CMBS@
BSS138_NL_SOT23-3
RA58
270K_0402_5%
CMBS@
11/17 Move HP JACK and MIC JACK Circuit to IO Board.
COM_MIC <17>
1
2
1
1
2
RA52
100K_0402_5%
CMBS@
COM_MIC
1
CA28
10U_0805_10V6K
CMBS@
RB491D_SC59-3
CMBS@
2K_0402_5%
HP_SENSE
B
CMBS@
CMBS@ RA50
10K_0402_5%
1
DA10
CMBS@
RA59
220_0402_5%
change GPIO_1 to GPIO_0

Tock 2011/01/03
GPIO_0
CMBS@ RA30
100K_0402_5%
Add RA58 for net GPIO_1

Tock 2010/12/08
<17>
1
CA25
10U_0805_10V6K
@
2010/11/09
Issued Date
Deciphered Date
2012/11/09
4
Title
KB Conn/TP/IO Conn
Size
B
Date:
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
1
24
of
37
11/17 Move Left Side USB CONN. Circuit to IO board
+5VALW
<24,26> USB_ON#
1
2
3
4
GND
VIN
VIN
EN
W=80mils
U11
EPAD
C338
0.1U_0402_16V4Z
Right Side USB CONN.
+USB_VCCC1
W=80mils
VOUT
VOUT
VOUT
FLG
8
7
6
5
Change C340 to SF000001500

2010/12/14 Tock
USB_OC1# <13>
AP2301MPG-13_MSOP8
1
+USB_VCCC1
9/28 Swap L28
W=80mils
C339
@ 1000P_0402_50V7K
1
C340
220U_6.3V_M
SA00003XM00
+
2
C341
R257
0_0402_5%
@
2
470P_0402_50V7K
L28
8/25 Change C340 from poly-cap to E-cap (SF000001500)
<13> USB20_N2
JUSB1
SGA00002N80
USB20_N2_1
USB20_P2_1
1
2
3
4
5
6
7
8
VCC
DD+
GND
GND
GND
GND
GND
<13> USB20_P2
2
3
USB20_N2_1
USB20_P2_1
WCM-2012-900T_4P
1
R258
2
0_0402_5%
SUYIN_020173GB004M25MZL
CONN@
change JUSB1 to SP060004B00

2010/12/14 Tock
delete D17 for DFB issue

2011/02/25 Tock
2010/11/09
Issued Date
Compal Secret Data
2012/11/09
Deciphered Date
A
Title
USB PORTS
Size
B
Date:
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
E
25
of
37
8/23 Pull up 10k (R345) to +3VALW on USB_ON#

place close to PU4 and PU7
R272
2 2.2K_0402_5%
EC_SMB_DA1
2 2.2K_0402_5%
EC_SMB_CK1
C353
R275
10P_0402_50V8J 22_0402_5%
2
1
1
2
Reserve for EMI please close to U12

R276
+3VALW
R277
2 2.2K_0402_5%
EC_SMB_CK2
2 2.2K_0402_5%
EC_SMB_DA2
<24>
KSI[0..7]
<24>
KSO[0..15]
KSI[0..7]
KSO[0..15]

R279
EC_SCI#
2 10K_0402_5%
8/31 EC_SCI# Pull up to +3VALW

8/23 Delete R280
Reserve C436, C437 for SMB
Michael 2010/11/18
EC_SMB_CK2
8/25 Delete KSO16 KSO17
C436
100P_0402_50V8J
C437
100P_0402_50V8J
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
Battery<29>
<29> EC_SMB_DA1
<4> EC_SMB_CK2
<4> EC_SMB_DA2
APU_ALERT#_EC
APU
@
C407 1
2 100P_0402_50V8J
EC_XCLK1
OSC
OSC
1
1
8/24 Delete Net FAN_SPEED1
C355
<9> INVT_PWM
<27> FAN_SPEED1
<20,21> BT_ON#
<21> EC_TX_P80_DATA
<21> EC_RX_P80_CLK
<23> ON/OFF#
<22> PWR_SUSP_LED#
15P_0402_50V8J
X1
32.768KHZ_12.5PF_Q13MC14610002
Board ID
<12>
R282
@
C357
0.1U_0402_16V4Z
ECAGND
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
67
9/23 Reserve R395 on ACIN
PS2
EC_XCLK1
EC_XCLK0
0_0402_5%
122
123
21
23
26
27
63
64
65
66
75
76
DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D
IREF/DA2/GPO3E
DA3/GPO3F
68
70
71
72
EC_MUTE#/PSCLK1/GPIO4A
USB_EN#/PSDAT1/GPIO4B
CAP_INT#/PSCLK2/GPIO4C
Interface
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXIOA00
WOL_EN/SDICLK/GPXIOA01
ME_EN/SDIMOSI/GPXIOA02
LID_SW#/GPXIOD00
10/08 Change D18 to SCS00000Z00
C399
ACOFF
83
84
85
86
87
88
97
98
99
109
ACOFF
GPIO
EC_SMB_CK1/SCL0/GPIO44
EC_SMB_DA1/SDA0/GPIO45
EC_SMB_CK2/SCL1/GPIO46
EC_SMB_DA2/SDA1/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO
GPIO0C
SUS_PWR_DN_ACK/GPIO0D
INVT_PWM/PWM2/GPIO11
FAN_SPEED1/FANFB0/GPIO14
FANFB1/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
BATT_TEMP
GPI
SPIDI/MISO
SPIDO/MOSI
SPICLK/GPIO58
SPICS#
GPIO40
H_PECI/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
PWR_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
PM_SLP_S4#/GPXIOD01
ENBKL/GPXIOD02
EAPD/GPXIOD03
EC_THERM#/GPXIOD04
SUSP#/GPXIOD05
PBTN_OUT#/GPXIOD06
EC_PME#/GPXIOD07
XCLK1
XCLK0
V18R
SA00003QQ10
@
C424
100P_0402_50V8J
Reserve C424, C425,

for SLP_S3#, SLP_S5#
Michael 2010/11/18
Reserve C428 for ON/OFF#

Michael 2010/11/18
ADP_I
2
0_0402_5%
@
RB751V-40_SOD323-2
2
D19
1
ICH_POK_EC
LID_SW#
R273
PWR_LED1# <23>
TP_CLK <24>
TP_DATA <24>
<31>
Follow PAWGC
EN_FAN1 <27>
IREF
<31>
CHGVADJ <31>
EC_MUTE# <17>
USB_ON# <24,25>
ACIN
C470
220P_0402_50V7K
0_0402_5%
ICH_POK <13>
R274
+3VS
C
10K_0402_5%
Reserve C470 for LID_SW#

Tock 2011/01/07
9/25 Change VLDT_EN to VLDT_EN#

EN_WOL#
VLDT_EN#
LID_SW#
EN_WOL# <18>
VLDT_EN# <28>
LID_SW# <23>
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#
73
74
89
90
91
92
93
95
121
127
EDP_BIST
R390 eDP@
1
2
0_0402_5%
110
112
114
115
116
117
118
VGATE
APU_ENBKL
EAPD
EC_PROCHOT#
SUSP#
PBTN_OUT#
WWAN_WAKEUP#
124
V18R
1
R278
DMIC_DATA <9,17>
VR_ON
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_PME#
ICH_POK_EC
BKOFF#
WL_OFF#
WXMIT_OFF#
LID_SW#
DMIC_DATA
+3VALW
place close to PU2
Project ID
Ra
1
C400
2
EC_RSMRST# <13>
100P_0402_50V8J
EC_LID_OUT# <13>
EC_ON <23>
VGATE
@
BKOFF# <9>
WL_OFF# <21>
WXMIT_OFF# <20>
1 100K_0402_5%
FSTCHG
BATT_AMB_LED# <22>
PWR_LED# <22>
SYSON <28,33>
VR_ON <36>
+3VALW
R285
100K_0402_5%
FSTCHG <31>
BATT_BLUE_LED# <22>
BATT_AMB_LED#
PWR_LED#
SYSON
VR_ON
EC_ACIN
100
101
102
103
104
105
106
107
108
Add EDP_BIST and Reserve C390 , R285

Tock 2010/12/30
EDP_BIST
EC_SI_SPI_SO <27>
EC_SO_SPI_SI <27>
EC_SPICLK <27>
EC_SPICS#/FSEL# <27>
FSTCHG
BATT_BLUE_LED#
C477
100P_0402_50V8J
R398 @
0_0402_5%
AD_PID0
1
Reserve C477 for FSTCHG

Tock 2011/01/07
Rb
R399 @
8.2K_0402_5%
C393 @
0.1U_0402_16V4Z
1
C423
100P_0402_50V8J
Reserve C423 for VGATE

Michael 2010/11/18
VGATE
<13,36>
APU_ENBKL <4>
EAPD
<17>
EC_PROCHOT# <4>
SUSP# <28,33,34>
PBTN_OUT# <13>
WWAN_WAKEUP# <20>
1
R281
100K_0402_5%
C356
PME Follow PAWGC

+3VALW
C447
100P_0402_50V8J
R322
10K_0402_5%
Reserve C447 for APU_ENBK

Tock 2011/01/07
1
R324
1
C471
100P_0402_50V8J
Reserve C471,C472
Tock 2011/01/07
2
@ 0_0402_5%
<13> PCI_PME#
C472
100P_0402_50V8J
+3VALW
1
A
Q29
SSM3K7002FU_SC70-3
@
for LAN_WAKE# , BKOFF#
Compal Secret Data

2010/11/09
EC_PME#
2
0_0402_5%
BKOFF#
1
C430
100P_0402_50V8J
1
R323
<18> LAN_WAKE#
LAN_WAKE#
Reserve C430 for EC_PROCHOT#

Michael 2010/11/18
R395
L30
ECAGND 2
1
FBMA-L11-160808-800LMT_0603
Issued Date
<31>
8/23 Delete DAC_BRIG

8/25 Delete CHG_ON#
8/31 Add EN_FAN1 on U12.70
PWR_LED1#
TP_CLK
TP_DATA
1
RB751V-40_SOD323-2
2
1 100P_0402_50V8J
C352
BATT_TEMP <29>
EC_MUTE#
USB_ON#
C428
100P_0402_50V8J
EC_ACIN
4.7U_0603_6.3V6K
1
C425
100P_0402_50V8J
D18
2
1 100P_0402_50V8J ECAGND
EN_FAN1
IREF
CHGVADJ
1 200K_0402_5%
2
10/27 Change
C356 from 10V_0805 to 6.3V_0603
20mil
ON/OFF#
1
<31>
ADP_I
AD_BID0
AD_PID0
EC_PROCHOT#
SLP_S5#
<17>
ACOFF
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
EC_ON/GPXIOA05
EC_SWI#/GPXIOA06
ICH_PWROK/GPXIOA07
BKOFF#/GPXIOA08
GPO RF_OFF#/GPXIOA09
GPXIOA10
GPXIOA11

SLP_S3#
C351 2
BEEP#
+3VALW
1
100P_0402_50V8J
BEEP#
SPI Device I/F
SPI Flash ROM
8/26 Change D18 to SCS00002G00 Standard Part
2012/11/09
Deciphered Date
5
4.7K_0402_5%
10/04 Add 100p(C399) on ACOFF
BATT_TEMP/AD0/GPI38
BATT_OVP/AD1/GPI39
ADP_I/AD2/GPI3A
AD3/GPI3B
AD Input
AD4/GPI42
AD5/GPI43
DA Output
KB930QF-A1_LQFP128_14X14
2
1
R284
8.2K_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
8/31 Add 100k(R358) pull-down on SUSCLK
SUSCLK
AD_BID0
1
Rb
CLK_PCI_EC/PCICLK
PCIRST#/GPIO05
EC_RST#/ECRST#
EC_SCI#/GPIO0E
CLKRUN#/GPIO1D
2 R358
1
@
100K_0402_5%
change R284 from 0 ohm to 8.2K ,

2011/01/28 Tock
change R283 from 0 ohm to 100K ,
2011/02/11 Tock
R264
Analog Board ID definition,

Please see page 3.
R283
100K_0402_5%
Ra
LPC & MISC
10/11 Change C354,C355, X1 from @ to mount

X1 C354 C355 from @ to mount
X1 C354 C355 from mount @
+3VALW
INVT_PWM
FAN_SPEED1
BT_ON#
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
PWR_SUSP_LED#
NC
15P_0402_50V8J
EC_XCLK0
77
78
79
80
SLP_S3#
SLP_S5#
EC_SMI#
APU_ALERT#_EC
<13> SLP_S5#
<13> EC_SMI#
<4> APU_ALERT#_EC
NC
C354
PWM0/GPIO0F
BEEP#/PWM1/GPIO10
FANPWM0/GPIO12
ACOFF/FANPWM1/GPIO13
SM Bus
10/05 Add 100p(C407) on APU_ALERT#_EC

<13> SLP_S3#
TP_DATA
9/23 Update EC pin definition follow P5WE6

Delete EC_FAN_PWM
Tock 2011/01/28
PWM Output
EC_SMB_DA2
@
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LPC_FRAME#/LFRAME#
LPC_AD3/LAD3
LPC_AD2/LAD2
LPC_AD1/LAD1
LPC_AD0/LAD0
GND
GND
GND
GND
GND
12
13
37
20
38
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
11/02 Change C353 to 10p R275 to 22 ohm
+3VS
<12> LPC_CLK0_EC
<12,18,20,21> PLT_RST#
EC_SMI#
2 1K_0402_5%
4.7K_0402_5%
R266
1
2
3
4
5
7
8
10
LPC_CLK0_EC
PLT_RST#
EC_RST#
EC_SCI#
<13> EC_SCI#
R271
KSO2
2 47K_0402_5%
R263
+5VS
C444
100P_0402_50V8J
TP_CLK
1 10K_0402_5%
KSO1
R270
2 47K_0402_5%
R345
10/1 ENE Recommand

R269
USB_ON#
1 10K_0402_5%
1
C443
@
100P_0402_50V8J
+3VALW
C348
0.1U_0402_16V4Z
TP_DATA
1
C403
@
100P_0402_50V8J
R259
R268
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<13> GATEA20
<13> KB_RST#
<12> SERIRQ
<12> LPC_FRAME#
<12> LPC_AD3
<12> LPC_AD2
<12> LPC_AD1
<12> LPC_AD0
0.1U_0402_16V4Z
Reserve C420 for PLT_RST#

Michael 2010/11/18
TP_CLK
1
@
AGND
C350 2
C420
100P_0402_50V8J
EC_RST#
C347
1000P_0402_50V7K
1 47K_0402_5%
U12
R267 2
C346
1000P_0402_50V7K
PLT_RST#
C345
0.1U_0402_16V4Z
LPC_CLK0_EC
C344
0.1U_0402_16V4Z
C343
0.1U_0402_16V4Z
@R265
@
R265
33_0402_5%
2
1
C342
0.1U_0402_16V4Z
ADP_I
EC_MUTE#
+3VALW_EC
1
@C349
@
C349
22P_0402_50V8J
2
1
L29
W=20mils
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
1
W=40mils
AVCC
R262
+3VALW 0_0603_5%
1
2
69
Reserve C475,C476 for SUSP#

Tock 2011/01/07
+3VALW
+3VALW
8/21 Change R262 from 0 ohm 0805 to 0 ohm 0603
9
22
33
96
111
125
C476
100P_0402_50V8J
Reserve C403, C443, C444

for ADP_I, TP_CLK, DATA
Michael 2010/11/18
11
24
35
94
113
C475
100P_0402_50V8J
+3VS
8/31 Change EC_MUTE# Pull-up to +3VS(@)
VCC
VCC
VCC
VCC
VCC
VCC
SUSP#
Title

EC ENE-KB930

Custom
Rev
1.0
P1VE6 Schematics
Date:
Sheet
1
26
of
37
+3VALW
R201 1
8/31 Remove EC ROM , Add SPI ROM
EC_SPICLK_R
2SPI_HOLD#
3.3K_0402_5%
1
R202 1
9/2 Change EC_SPICLK to EC_SPICLK_R
2MB SPI ROM

Share ROM.
2 SPI_WP#
3.3K_0402_5%
R200
33_0402_5%
@
W=20mil
+3VALW
C212
1
2
CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)
8
7
6
5
SPI_HOLD#
0_0402_5% R206
EC_SPICLK_R 1
2 EC_SPICLK
EC_SPI_SI
1
2 EC_SO_SPI_SI
SA00003FO00
EC_SPICLK <26>
EC_SO_SPI_SI <26>
EMI
33_0402_5% R205
W25Q16BVSSIG_SO8
Layout Note:
R204 close to U7
C211
22P_0402_50V8J
@
0.1U_0402_16V4Z
U7
EC_SPICS#/FSEL#_R 1
EC_SPI_SO
2
SPI_WP#
3
33_0402_5%
4
R204
Layout Note:
R203 R205 R206 close to U12
Delete U17,C382,C386,R355,D20,C383,C384,C385
for Fan control IC circuit
2010/12/15 Tock
Add U17,C382,C386,R355,D20,C383,C384,C385
for Fan control IC circuit
2011/01/19 Tock
+5VS
FAN Conn.
EC_SPICS#/FSEL#
EC_SI_SPI_SO
<26> EC_SPICS#/FSEL#
<26> EC_SI_SPI_SO
R203
0_0402_5%
1
2
1
2
D20
DAN217_SC59
+5VS
C382
1
2.2U_0603_10V6K
@
2 C383
1
U17
H2
H_3P2
H3
H_3P2
9/15 Update the Screw Hole

<26>
1
R355
GND
GND
GND
GND
4.7U_0603_6.3V6K
@
10/07 Change H13 from LANGND to GND
EN
VIN
VOUT
VSET
APL5607KI-TRG_SO8
10/07 Change H13 from GND to LANGND

@
+VCC_FAN1
EN_FAN1_R
2
330_0402_5%
9/20 Add H20 (H_3P4X3P2N)
EN_FAN1
8
7
6
5
2
H4
H_3P0N
2 C385
+3VS
C386
0.01U_0402_16V7K
40mil
1000P_0402_50V7K
+VCC_FAN1
H1
H_3P2
3P2 x 3 (APU)
1
2
3
4
4.7U_0603_6.3V6K
@
1
2 C384
R290
10K_0402_5%
+5VS
1
R289
@
H9
H_2P3
2P3 x 2
1
1
@
H6
H_2P5
H7
H_2P5
H15
H_0P6X2P3
GND
GND
ACES_50273-0030N-001
CONN@
FM3
@
FM4
@
FIDUCIAL_C40M80
8/25 Update JFAN1 Symbol from database (ACES_85205-04001_4P) & Update pin definition
8/25 Add R290 10k pull-up tp +3VS
FM2
@
H11
H_2P5
1
H10
H_2P5
2P5 x 4
4
5
1
2
3
8/24 Update JFAN1 Symbol from database (ACES_85205-03001_3P) & Update pin definition
8/24 Delete R290
FM1
H12
H_0P6X2P3
1
2
3
Update the Screw Hole

2010/12/22 Tock
JFAN1
+VCC_FAN1
Update the Screw Hole

2010/12/16 Tock
H8
H_2P3
+VCC_FAN1
2
0_0603_5%
<26> FAN_SPEED1
1
C360
@
10U_0805_10V6K
2
40mil
3P0N x 1
8/31 Reserve U17,C382~C386, R355~R357, D20 (Fan Drive Circuit)

change JFAN1 footprint from ACES_85205-04001_4P to ACES_50273-0030N-001_3P , 2011/01/28 Tock ,
delete EC_FAN_PWM and R356,R357 , 2011/01/28 Tock ,
0P6X2P3 x 2
H13
H_3P0X4P0N
H14
H_3P0X4P0N
3P0X4P0N x 2
Issued Date
Compal Secret Data
2010/11/09
Deciphered Date
2012/11/09
Title
Screw / EC ROM /FAN

Size
B
Date:
Document Number
Rev
1.0
P1VE6 Schematics
Sheet
27
of
37
+3VALW TO +3VS
C370
0.1U_0603_25V7K
2
G
Q20
C371
0.1U_0603_25V7K
9/27 Change Q21.2 from SUSP# to SUSP
2
SUSP# 2
G
Q21
2
1
100K_0402_5%
2 +1.1VS_ON#
G
Q22 @
1
C404 1
SUSP
R400
100K_0402_5%
0_0402_5%
2
0_0402_5%
SUSP
SUSP
SYSON#
10/04 Add 100p(C403) on SUSP
VLDT_EN#
10/06 Remove C403
VLDT_EN# <26>
R403
0_0402_5%
2 100P_0402_50V8J
2
G
Q30
<26,33,34> SUSP#
10/04 Add 100p(C404) on VLDT_EN#

+1.1VS_GATE_R
1
<35>
C408 1
2 100P_0402_50V8J
10/06 Change C404 on +1.1VS_ON#
R404
10K_0402_5%
D
SYSON
<26,33> SYSON
S
SSM3K7002FU_SC70-3
@
2
G
Q31
SSM3K7002FU_SC70-3
2
1
+1.1VS_ON# 2
G
Q24
1
R402
@
R303
100K_0402_5%
+1.1VS_ON#
R302
100K_0402_5%
9/28 Remove C372
R300
470_0603_5%
@
R304
47K_0402_5%
1
9/28 Change U19 to Q15(SB934130020)
SSM3K7002FU_SC70-3 S
+1.1VS_GATE 2 R351
+5VALW
9/28 Change R296.1 from +VSB to +5VALW
C376
1U_0603_10V6K
SB548000210
+VSB
+5VALW
2011/02/11 Change Q15 to SB000006R10

+5VALW
10/29 Change R298 from 0 ohm to 100k
C373
0.1U_0402_16V4Z
10/31 Change C373 from 0603_25V to 0402_16V
9/28 Change Q21.2 from SUSP to SUSP#
10/12 Change R400 R403 from @ to mount
1
2
3
Remove C375 10U

Michael 2010/11/18
+1.5VS_GATE_R
1
S SSM3K7002FU_SC70-3
8
7
6
5
+1.1VS
SUSP
+1.5VS_GATE 2 R298
D
9/27 Change Q15 to U19(SB00000GV00)
U16
+1.1VALW
AP4800BGM-HF_SO-8
Remove C374 10U

Michael 2010/11/18
2
G
Q18
SSM3K7002FU_SC70-3 S
9/27 Change R296.1 from +5VALW to +VSB
+1.1ALW to +1.1VS
R296
200K_0402_5%
change R295 from 200K to 120K

Tock 2011/01/03
0_0402_5%
SSM3K7002FU_SC70-3
S
G
2+3VS_GATE_R
1
SB000006R10
1
1
SUSP
+3VS_GATE 1 R350
D
+5VALW
2 SUSP
G
Q17 @
SSM3K7002FU_SC70-3
R291
470_0603_5%
+5VS_GATE_R
1
C363
1U_0603_10V6K
2
G
3
20K_0402_5%
SSM3K7002FU_SC70-3
Q19
2
1
1
1
R293
470_0603_5%
@
R295
120K_0402_5%
R297
+5VS_GATE 1
Remove C362 10U

Michael 2010/11/18
SUSP
C369
1U_0603_10V6K
SB548000210
2 SUSP
G
Q16 @
SSM3K7002FU_SC70-3
1
R294
82K_0402_5%
3
1
+VSB
SB548000210
+1.5VS
Q15
AO3413L_SOT23-3
+VSB
R292
470_0603_5%
@
1
2
3
+1.5V
1 2
8
7
6
5
1 2
C366
1U_0603_10V6K
Remove C361 10U

Michael 2010/11/18
Remove C368 10U

Michael 2010/11/18
+3VS
1
2
3
10/27 Change R291 Q18 from @ to mount
+1.5V to +1.5VS
U15
+3VALW
Remove C367 10U
AP4800BGM-HF_SO-8
Michael 2010/11/18
8
7
6
5
Remove C365 10U

Michael 2010/11/18
+5VS
U14
+5VALW
Remove C364 10U
AP4800BGM-HF_SO-8
Michael 2010/11/18
+5VALW TO +5VS
C378
0.1U_0603_25V7K
10/27 Add C408(100P) on SUSP# close to PR70

9/27 Change R302 from @ to mount, remove R301
8/19 Change Q16~Q22 Q24~Q28 toSB000009610(SSM3K7002FU_SC70-3)
SSM3K7002FU_SC70-3
10/12 Change R294 to 100k
9/27 Change R304.1 from +5VALW to +VSB
10/12 Change R295, R296 to 200k
Change Q25 package to SOT363-6

Remove Q26
Michael 2010/11/18
+1.8VS
Change Q27 package to SOT363-6

Remove Q28
Michael 2010/11/18
+1.05VS

+1.5V
8/19 Change Q29 Q30 to Q23A Q23B (SB00000DH00 S TR DMN66D0LDW-7 2N SOT363-6)
10/31 Change C361 C362 from mount to @

3
8/21 Change U14~U16 to SB548000310 (SI4800BDY-T1-E3_SO8)

8/23 Remove R305 R299 Add R350 R351 for Sequence
8/24 Change Q23A Q23B to Q30 Q31(@) (SB000009610 SSM3K7002FU_SC70-3)
+0.75VS
1
@
2
Q27B
R309
470_0603_5%
@
8/25 Change C361,C362,C364,C365,C367,C368,C374,C375 to SE000004880 Standard Part

8/26 Change U14, U15, U16 to SB00000GV00 Standard Part
9/3 Delete C377(DIS@)
Q27A
SUSP
5
4
2N7002DW-T/R7_SOT363-6
R307
470_0603_5%
@
Q25B
SUSP
2N7002DW-T/R7_SOT363-6
2
1
Q25A
R308
470_0603_5%
@
SYSON#
2N7002DW-T/R7_SOT363-6
R306
470_0603_5%
@
8/25 Change C363,C366,C369,C376 to SE080105K80 Standard Part
SUSP
2N7002DW-T/R7_SOT363-6
9/23 Reserve R400~403, Q36 for VLDT_EN

9/25 Remove R401 Q36 on VLDT_EN
9/25 Add 10k(R404) PD on SUSP#
Compal Secret Data
2010/11/09
Issued Date
2012/11/09
Deciphered Date
A
Title
DC Interface
Custom
Date:
Rev
1.0
P1VE6 Schematics
Sheet

E
28
of
37
VMB
PL2
HCB2012KF-121T50_0805
1
2
PJP2
VMB
1
2
3
4
5
6
7
8
9
10
BATT+
EC_SMCA
PR6
1K_0402_1%
PC8
0.01U_0402_25V7K
PC7
1000P_0402_50V7K
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 72 degree C
EC_SMDA
B/I
TS
1
VL
@ PR10
100K_0402_1%
<31> MAINPW ON
PU1
PR8
22.1K_0402_1%
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
PR11
15K_0402_1%
OT2 RHYST2
+3VALW
PR14
1K_0402_1%
2
1
PR13
100_0402_1%
1
2
PR12
100_0402_1%
1
2
G718TM1U_SOT23-8
@ PR15
47K_0402_1%
1
BATT_TEMP <25>
1
PR9
6.49K_0402_1%
2
1
PR7
10K_0402_1%
VL
PC9
0.1U_0402_10V7K
@
SUYIN_200275MR008G15QZR
1
2
3
4
5
6
7
8
GND
GND
PH2 @
EC_SMB_CK1 <25>
PH1
100K_0402_1%_NCP15W F104F03RC
2
100K_0402_1%_NCP15W F104F03RC
EC_SMB_DA1 <25>
PQ2
TP0610K-T1-E3_SOT23-3
3
B+
+VSBP
1
PR18
100K_0402_1%
PR17
1
2
1
2
VL
PC10
0.22U_0603_25V7K
2
1
PR16
100K_0402_1%
PC11 @
0.1U_0603_25V7K
22K_0402_1%
PR19
<31,33>
POK
PQ3
SSM3K7002FU_SC70-3
2
G
PC12
.1U_0402_16V7K
0_0402_5%
Issued Date
Compal Secret Data
2010/08/12
Deciphered Date
2012/08/12
A
Title
BATTERY CONN / OTP

Size
Date:
Document Number
Rev
1.0
Sheet
D
29
of
37
VIN
PD1
1
RLS4148_LL34-2
+CHGRTC
VS
1
2
PC6
0.22U_0603_25V7K
PC5
0.1U_0603_25V7K
PR4
<22>
51_ON#
@ PJ2
@ PC248
.1U_0402_16V7K
+1.1VALW P
JUMP_43X118
PC241
.1U_0402_16V7K
@ PC254
.1U_0402_16V7K
+1.1VALW
1
+3VALW
PC242
.1U_0402_16V7K
+3VLP
PJ1
PR5
0_0603_5%
1
2
JUMP_43X118
2
22K_0402_1%
PR2
68_1206_5%
1
PR3
100K_0402_1%
SP02000GC00
+3VALW P
N1
RLS4148_LL34-2
1
2
<BOM Structure>
PC4
100P_0402_50V8J
PC3
1000P_0402_50V7K
1
2
PC2
100P_0402_50V8J
1
2
3
4
PR1
68_1206_5%
PD2
BATT+
PC1
1000P_0402_50V7K
1
2
5 GND 3
6 GND 4
PJP1
PQ1
TP0610K-T1-E3_SOT23-3
DC_IN_S1
CONN@
ACES 88266-04001
VIN
PL1
HCB2012KF-121T50_0805
1
2
+5VALW
@ PC252
.1U_0402_16V7K
PC243
.1U_0402_16V7K
JUMP_43X39
2
+1.05VS
PC244
.1U_0402_16V7K
@ PC253
.1U_0402_16V7K
+VSB
+0.75VSP
@ PJ6
1
JUMP_43X79
PC245
.1U_0402_16V7K
@ PC255
.1U_0402_16V7K
@ PJ5
+VSBP
JUMP_43X118
2
JUMP_43X118
+1.05VSP
@ PC256
.1U_0402_16V7K
+0.75VS
1
PJ3
PC246
.1U_0402_16V7K
@ PJ4
+5VALW P
@ PJ7
2
JUMP_43X118
@ PC257
.1U_0402_16V7K
+1.8VS
1
+1.8VSP
PC247
.1U_0402_16V7K
@ PJ9
1
2
JUMP_43X118
PC258
.1U_0402_16V7K
+1.5V
1
+1.5VP
PC249
.1U_0402_16V7K
Issued Date
Compal Secret Data
2010/08/12
Deciphered Date
2012/08/12
A
Title
DCIN/VIN DECTOR
Size
Date:
Document Number
Rev
1.0
Sheet
D
30
of
37
1
2
3
EN
CSON
22
PR34 2
PHASE
18
LX_CHG
6251VREF
VREF
UGATE
17
DH_CHG
.1U_0402_16V7K
6251VREF 1
6251ACLIM
4
2
1
3
CHLIM
BOOT
16
PR42
BST_CHG 1
2
0_0603_5%
10
ACLIM
VDDP
15
6251VDDP
11
VADJ
LGATE
14
DL_CHG
12
GND
PGND
13
1
2
20K_0402_1%
1 1
1
2
4.7K_0402_1%
PR46
1
2
0.01U_0402_25V7K
1
PC31
ACOFF
PR44
100K_0402_1%
2
<25>
PQ12
DTC115EUA_SC70-3
ACOFF
2
PR43
PL4
10UH_VMPI0703AR-100M-Z01_3.5A_20%
CHG
1
2
1
PC27
BST_CHGA 2
1
0.1U_0603_25V7K
PD5
SD103AW S SOD323-2
1
2 6251VDD
PR45
PC32
4.7U_0603_6.3V6M
PR38
BATT+
4
2
@ PR41
4.7_1206_5%
3
0.05_1206_1%
ICM
2
2_0402_5%
3
2
1
19
@ PC28
680P_0603_50V7K
IREF
CSIP
PC26
1
2
PR39
62K_0402_1%
2
1
VCOMP
1 20_0402_5%
PC25
0.1U_0603_25V7K
1
PR36
1
2
47K_0402_1%
ADP_I
6
PR37
<25>
@
PC21
2200P_0402_50V7K
PQ10
AON7408L_DFN8-5
PR40
47K_0402_1%
1
2
20
PR27
100K_0402_1%
1
2BATT_ON
CSOP
PQ11
AON7408L_DFN8-5
<25>
CSIN
6800P_0402_25V7K
10K_0402_1%
0.01U_0402_25V7K
ICOMP
CSON
PR35
CSOP
5
G
PACIN
PC24
1
2
CELLS
21
PQ9B
DMN66D0LDW -7_SOT363-6
PR32 20_0402_5%
1
2
PC22
0.047U_0402_16V7K
1
2
PR33
20_0402_5%
3
2
1
PC23
1
2
PQ7
DTC115EUA_SC70-3
PQ9A
PR28
14.3K_0402_1%
0.1U_0603_25V7K
ACPRN
ACSETIN
PC204
10U_0805_25V6K
23
VIN
PC205
10U_0805_25V6K
2
1
ACSET ACPRN
47K_0402_1%
2
G
PC19
1000P_0402_25V8J
2
1
1 1
6251_EN
24
100K_0402_1%
DCIN
PR21
PR25
10K_0402_1%
PC20
DCIN 2
VDD
PR31
PR30
150K_0402_1%
PQ8
DTC115EUA_SC70-3
6251VDD
PU2
1
PQ6
DTA144EUA_SC70-3
PR29
10K_0402_1%
2
1
FSTCHG
<25>
PR26
10_1206_5%
PR24
191K_0402_1%
PD4
RB751V-40_SOD323-2
BATT_ON
PC18
2.2U_0603_6.3V6K
ACSETIN
PR23
200K_0402_1%
PC17
0.1U_0603_25V7K
2
1
PR22
200K_0402_1%
VIN
PC13
5600P_0402_25V7K
PC16
4.7U_0805_25V6-K
2
1
CSIP
1
2
3
CSIN
PC15
4.7U_0805_25V6-K
2
1
PQ5
AON7403L_DFN8-5
CHG_B+
@ PL3
HCB2012KF-121T50_0805
2
1
PC30
10U_0805_25V6K
2
1
PC14
4.7U_0805_25V6-K
2
1
1
2
3
PC29
10U_0805_25V6K
2
1
SX34_SMA2
B+
PR20
0.05_1206_1%
1
4
PL18
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
2
1
PC251
10U_0805_25V6K
VIN
P3
AON7403L_DFN8-5
PQ4
P2
PD3
PC250
10U_0805_25V6K
2
1
CP = 85%*Iada ; CP = 1.789A
ADP_I = 19.9*Iadapter*Rsense
PC237
10U_0805_25V6K
2
1
Iada=0~2.105A(40W/19V=2.105A)
4.7_0603_5%
ISL6251AHAZ-TR5283_QSOP24
<25> CHGVADJ
PR47
1
CV mode
PR48
31.6K_0402_1%
CC=0.25~3.52A
Vth,rise(typical) = ((191K/14.3K)+1)*1.26
6251VDD
= 18.089V
BATT Type
15.4K_0402_1%
Charging Voltage
(0x15)
Vth,fall(typical) = ((191K/14.3K)+1)*1.26 -3.4uA*191K
IREF=0.7224*Icharge
12.60V
IREF=0.43V~3.24V
12600mV
= 17.44V
Normal 3S LI-ON Cells
PR49
47K_0402_1%
2
PR50
10K_0402_1%
ACIN
<25>
PACIN
Ki
Vchlim=Iref*(PR39/(PR39+PR44))
=Iref*(100K/(80.6K+100K))
=Iref*0.617
Ichanrge=(165mV/PR38)*(Vchlim/3.3V)
=(165m/50m)*(1/3.3V)*Iref*0.617
=0.617*Iref
Iref=1.62*Ichanrge =>Ki=1.62
PR51
10K_0402_1%
1
2
PQ13
DTC115EUA_SC70-3
2
PR52
14.3K_0402_1%
ACPRN
Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451
2010/08/12
Issued Date
Compal Secret Data
Deciphered Date
2012/08/12
5
Title
CHARGER
Size
Date:
Document Number
Rev
1.0
Sheet
1
31
of
37
2VREF
PC33
1U_0402_6.3V6K
UGATE1
21
LX_3V
11
PHASE2
PHASE1
20
LX_5V
LG_3V
12
LGATE2
LGATE1
19
LG_5V
PC37
0.1U_0603_25V7K
2
1
PC240
4.7U_0805_25V6-K
2
1
PL7
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2
1
+
PC46 @
680P_0603_50V7K
PC44
220U_6.3V_M
PQ17
FDMC7692S_MLP8-5
3
2
1
VL
PC48
4.7U_0603_6.3V6K
B++
PQ18B
PR64
+5VALWP
NC
RT8205EGQW _W QFN24_4X4
2VREF
PC49
0.1U_0603_25V7K
PR65
VL
<29,33>
PC42
2 0.1U_0603_25V7K
PR62 @
4.7_1206_5%
18
17
16
13
3
2
1
UGATE2
PC40
4.7U_0805_25V6-K
2
1
10
POK
PQ15
AON7408L_DFN8-5
2
S
FB1
UG_3V
PR60
BST_5V 1
2
0_0603_5%
UG_5V
EN
D
5
G
ENTRIP1
22
1
2
REF
BOOT1
VREG5
BOOT2
VIN
ENTRIP2
ENTRIP1
BST_3V
1
2
3
2
PC47
1U_0402_6.3V6K
B
PQ18A
TONSEL
23
GND
24
PGOOD
PR63
499K_0402_1%
1
2
B++
PQ16
FDMC7692S_MLP8-5
ENTRIP2
VO1
VREG3
100K_0402_5%
2
PC45 @
680P_0603_50V7K
6
ENTRIP2
VO2
PR58
143K_0402_1%
1
2
4.7_1206_5%
B++
PR61 @
PC43
220U_6.3V_M
P PAD
15
PR59
1
2
0_0603_5%
+3VALWP
PL6
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
1
2
25
1
2
3
PC41
0.1U_0603_25V7K
PU3
SKIPSEL
PR57
130K_0402_1%
1
2
14
PC38
PQ14
AON7408L_DFN8-5
PR56
19.1K_0402_1%
1
2
4.7U_0603_6.3V6K
PC36
2200P_0402_50V7K
2
1
PC239
4.7U_0805_25V6-K
2
1
PC35
4.7U_0805_25V6-K
2
1
+3VLP
PR55
20K_0402_1%
1
2
ENTRIP1
B+
PL5
HCB2012KF-121T50_0805
1
2
PR54
30K_0402_1%
1
2
FB2
B++
+5VALW Vo= (2*30K/19.1K)+2=5.141V
PR53
13.7K_0402_1%
1
2
PC39
2200P_0402_50V7K
2
1
+3VALW Vo= (2*13.7K/20K)+2=3.37V
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)

(2)SMPS2=375KHZ (+3VALWP)
1
1
100K_0402_1%
<29> MAINPW ON
PR66
1
2
100K_0402_1%
1
2
PC50
0.1U_0402_10V7K
PR67
2
42.2K_0402_1%
VS
PQ19
DTC115EUA_SC70-3
+3.3VALWP
Imax=4.214A ; Ipeak=6.02A ; Iocp=1.2*Ipeak=7.224A
f=375KHz, L=4.7UH,Rentrip2=130K ohm
Rdson=14.5~17.9m ohm (IRFH3707)
1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A
Vtrip2=(10*10^-6*150Kohm/9)-24mV=0.143V
Ilimit=0.143/(17.9m*1.2)~0.143/(14.5m)=6.642A~9.839A
Iocp=7.415A~10.613A (7.415A>7.224A -> OK)
+5VALWP
Imax=4.9A ; Ipeak=7A ; Iocp=1.2*Ipeak=8.4A
f=300KHz, L=4.7UH,Rentrip1=143K ohm
Rdson=14.5~17.9m ohm (IRFH3707)
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vtrip1=(10*10^-6*162Kohm/9)-24mV=0.156V
Ilimit=0.156/(17.9m*1.2)~0.156/(15m)=7.263~10.759A
Iocp=8.569~12.065A (8.569>8.4 -> OK)
Compal Secret Data
2010/08/12
Issued Date
Deciphered Date
2012/08/12
5
Title
3VALWP/5VALWP
Size
Document Number
Rev
1.0
Date:
Sheet
1
32
of
37
FB
1
PC55
2
200K_0402_1%
PC56
PR72
0.22U_0402_10V6K
FB_1.8VS
PR71
10K_0402_1%
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR69/PR71)=0.6*(1+20.5K/10K)=1.83V
Ipeak=2A, Imax=1.4A
499K_0402_1%
PR69
20.5K_0402_1%
PC54
22U_0805_6.3VAM
1
2
NC
FB=0.6Volt
NC
TP
11
2 EN_1.8VS
PR68
1
PR70
<25,27,33> SUSP#
+1.8VSP
1
PC51
22U_0805_6.3VAM
EN
SVIN
PC53
22U_0805_6.3VAM
LX
LX_1.8VS
PVIN
PC52
68P_0402_50V8J
2
1
JUMP_43X39
LX
PVIN
10
680P_0603_50V7K
4.7_0603_5%
+5VALW
PL8
1UH_FDV0630-1R0M-P3_10.3A_20%
PU4
SY8033BDBC_DFN10_3X3
@ PJ10
PG
14
BST
VFB=0.75V
FB
PGOOD
13
DH_1.5V
LX_1.5V
LX
12
ILIM
11
VDD
10
DL
PR73
1
2
15K_0402_1%
PC61
0.1U_0603_25V7K
2
1
PC62
2200P_0402_50V7K
2
1
1
+1.5VP
@ PR79
4.7_1206_5%
+5VALW
DL_1.5V
+ PC65
330U_2.5V_M
PC67
4.7U_0603_6.3V6K
PQ21
FDMC7692S_MLP8-5
@ PC66
680P_0603_50V7K
G5603RU1U_TQFN14_3P5X3P5
4
2
PGND
8
AGND
PC58
4.7U_0603_6.3V6K
0.1U_0603_25V7K
1
VCC
DH
PL10
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
PC64
1
2
OUT
BST_1.5V-1
100_0603_5%
0_0603_5%
PR78
TON
+5VALW
15
EN_SKIP
PU5
TP
PC63 @
.1U_0402_16V7K
PR76
30K_0402_5%
B+
3
2
1
BST_1.5V
0_0402_5%
PR77
3
2
1
PR75
<25,27> SYSON
PC60
4.7U_0805_25V6-K
2
1
PR74
255K_0402_1%
1
2
PQ20
AON7408L_DFN8-5
PC59
4.7U_0805_25V6-K
2
1
PL9
HCB2012KF-121T50_0805
1
2
PR80
5.36K_0402_1%
PR81
5.1K_0402_1%
2
<Vo=1.5V> VFB=0.75V
V=0.75*(1+5.36K/5.1K)=1.538V
Cout ESR=25m ohm
Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707)
Ipeak=6.5A, Imax=4.55A, Iocp > 7.8A
G5603
Temperature
Compensated
RT8209B
-1180ppm/
1600ppm/
TPS51117
4500ppm/
OCP setting
RT8209B
TPS51117
RT8209M
6.821A
7.235A
8.000A
8.178A
RT8209M
4800ppm/
Vtrip_min (SPEC)
30mV
50mV
30mV
50mV
Vtrip_max (SPEC)
200mV
200mV
200mV
200mV
Issued Date
Compal Secret Data
2010/08/12
Deciphered Date
2012/08/12
A
G5603
Title
1.8VSP/1.5VP
Custom
Date:
Rev
1.0

D
Sheet
33
of
37
PR82
255K_0402_1%
1
2
2
PR88
13K_0402_1%
DL_1.1VALW
DL
4
1
PGND
8
AGND
7
PC75
4.7U_0603_6.3V6K
+5VALW
PC76
4.7U_0603_6.3V6K
PC71
2200P_0402_50V7K
1
2
PC70
0.1U_0603_25V7K
2
1
1
2
PC74
330U_2.5V_M
10
G5603
RT8209B
TPS51117
RT8209M
5.799A
6.183A
6.845A
6.976A
+1.1VALW P
OCP setting
@ PR86
4.7_1206_5%
11
BST
ILIM
VDD
0.1U_0603_25V7K
@ PC77
680P_0603_50V7K
PGOOD
LX_1.1VALW
VFB=0.75V
DH_1.1VALW
12
FB
13
LX
PQ23
FDMC7692S_MLP8-5
VCC
14
15
DH
OUT
3
2
1
TON
+5VALW
PL12
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2
PC73
1
PR87
100_0603_1%
1
2
TP
PU6
EN_SKIP
PC72
.1U_0402_16V7K
@
PR84
30K_0402_5%
@
Cout ESR=25m ohm

Rdson(max)=17.9 mohm Rdson(typ)=14.5 mohm. (IRFH3707)
PQ22
AON7408L_DFN8-5
BST_1.1V ALW
POK
PR85
0_0603_5%
1
2
<29,31>
PR83
0_0402_5%
1
2
B+
<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.99K/10K)=1.124V
3
2
1
PC69
4.7U_0805_25V6-K
PC68
4.7U_0805_25V6-K
PL11
HCB2012KF-121T50_0805
1.1VALW _B+ 2
1
1
+
2
PR89
4.99K_0402_1%
1
2
2
PR90
10K_0402_1%
2
PL13
HCB2012KF-121T50_0805
DL
4
1
PGND
8
PGOOD
AGND
6
2
PC85
4.7U_0603_6.3V6K
PC86
4.7U_0603_6.3V6K
PC80
0.1U_0603_25V7K
2
1
PC79
4.7U_0805_25V6-K
2
1
PC81
2200P_0402_50V7K
+1.05VSP
PC84
330U_2.5V_M
DL_1.05VALW
+5VALW
@ PR97
4.7_1206_5%
PR96
15K_0402_1%
@ PC87
680P_0603_50V7K
10
VDD
LX_1.05VALW
1
ILIM
11
14
15
BST
12
0.1U_0603_25V7K
FB
LX
VCC
VFB=0.75V
13
PQ25
FDMC7692S_MLP8-5
OUT
DH_1.05VALW
DH
PL14
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2
PC83
1
3
2
1
PR95
100_0603_1%
1
2
+5VALW
TON
B+
PQ24
AON7408L_DFN8-5
BST_1.05V ALW
TP
PU7
EN_SKIP
PC82
.1U_0402_16V7K
<BOM Structure>
PR94
30K_0402_5%
@
<25,27,32> SUSP#
4
PR93
0_0603_5%
1
2
3
2
1
PR92
200K_0402_1%
1
2
1
2
5
PR91
255K_0402_1%
1
2
PC78
4.7U_0805_25V6-K
1.05VALW _B+ 2
1
+
<Vo=1.05V> VFB=0.75V
V=0.75*(1+3.57K/8.25K)=1.074V
Cout ESR=25m ohm

Rdson(max)=17.9m ohm Rdson(typ)=14.5 mohm.(IRFH3707)
PR98
3.57K_0402_1%
1
2
OCP setting
RT8209B
TPS51117
RT8209M
6.524A
7.003A
7.768A
7.881A
PR99
8.25K_0402_1%
G5603
G5603
Temperature
Compensated
RT8209B
-1180ppm/
1600ppm/
TPS51117
4500ppm/
RT8209M
4800ppm/
30mV
50mV
30mV
50mV
Vtrip_max (SPEC)
200mV
200mV
200mV
200mV
Issued Date
Compal Secret Data
Vtrip_min (SPEC)
2010/08/12
Deciphered Date
2012/08/12
B
Title
1.1VALWP/1.0VSP
Custom
Date:
Rev
1.0

D
Sheet
34
of
37
PJ11
JUMP_43X118
@
PU8
1
2
1
GND
NC
VREF VCNTL
+3VALW
8
7
6
PC89
1U_0402_6.3V6K
PR100
1K_0402_1%
NC
VOUT
PC88
4.7U_0603_6.3V6K
VIN
+1.5V
NC
TP
5
9
PQ26
SSM3K7002FU_SC70-3
+0.75VSP
PR102
1K_0402_1%
PC90
.1U_0402_16V7K
2
1
PC91
10U_0603_6.3V6M
PC92
.1U_0402_16V7K
2
G
PR101
300K_0402_5%
1
2
SUSP
<27>
APL5336KAI-TRL_SOP8P8
For shortage changed
Compal Secret Data
2010/08/12
Issued Date
2012/08/12
Deciphered Date
5
Title

0.75VSP
Size
Date:
Document Number
Rev
1.0
Sheet
1
35
of
37
PL15
HCB2012KF-121T50_0805
CPU_B+
PC93
33P_0402_50V8J
2
1
PR124
0_0402_5%
PR126
26.1K_0402_1%
2
1
6
7
8
SVC
PGND0
LGATE0
RBIAS
PVCC
OCSET
LGATE1
VDIFF0
PGND1
35
BOOT0
34
UGATE0
33
PHASE0
32
<4> APU_VDD0_RUN_FB_H
PC99
68U_25V_M_R0.44
PC98
2200P_0402_50V7K
2
1
PC97
0.1U_0603_25V7K
2
1
PC96
4.7U_0805_25V6-K
2
1
PC103
220U_D2_2VY_R15M
1
1 2
PC110
2200P_0402_50V7K
2
1
PC109
0.1U_0603_25V7K
2
1
PC108
4.7U_0805_25V6-K
2
1
PC107
4.7U_0805_25V6-K
2
1
PC106
4.7U_0805_25V6-K
2
1
3
2
1
+5VALW
30
29
28
PQ30
FDMC7692S_MLP8-5
PR123
7.5K_0402_1%
@PC112
@PC112
680P_0603_50V7K
PC113
2
1
0.1U_0603_16V7K
PC114
1U_0603_16V6K
2
LGATE0
27
PR127
1.69K_0402_1%
26
TP
25
49
ISN1
24
ISP1
23
VW1
22
COMP1
21
FB1
20
VDIFF1
19
VSEN1
18
RTN1
17
14
ISN0
ISP0
VSEN1
PR129
0_0402_5%
PR130
0_0402_5%
2
1
BOOT1
+APU_CORE
@ PR122
4.7_1206_5%
LGATE0
31
+APU_CORE
ISP0
ISN0
PR128
10_0402_1%
1
2
13
VSEN1
RTN0
UGATE1
VW0
VSEN0
COMP0
ISP0
12
PHASE1
16
11
FB0
PC111
0.22U_0603_10V7K
PHASE0
36
PL17
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2
UGATE0
SVD
ISL6265CHRTZ-T_TQFN48_6X6
PR118
2.2_0603_1%
BOOT0 1
2 1
38
39
40
41
PWROK
15
10
37
UGATE_NB
PHASE_NB
LGATE_NB
PGND_NB
42
43
44
45
46
BOOT0
BOOT_NB
BOOT_NB
PGOOD
ENABLE
ISN0
PR125
90.9K_0402_1%
2
1
VR_ON
@ PC104
680P_0603_50V7K
ISP0
100P_0402_50V8J
1 2
2
PR121
0_0402_5%2
+APU_CORE_NB
PHASE0
3
2
1
<4>
PQ29
AON7408L_DFN8-5
@ PC124
@PC124
2
1
OFS/VFIXEN
OCSET_NB
ISN0
<25>
PC123
100P_0402_50V8J
2
1
ISL6265_PWROK
<4> APU_SVD
APU_SVC
2
@ PR119 100K_0402_5%
2
PR120 100K_0402_5%
RTN_NB
VSEN_NB
<11> H_PWRGD_L
FSET_NB
<12> FCH_PWRGD
FB_NB
VCC
VGATE
COMP_NB
47
48
VIN
PU9
@PR107
4.7_1206_5%
CPU_B+
UGATE0
@ PR117
105K_0402_1%
PQ28
FDMC7692S_MLP8-5
PHASE_NB
@ PR114
105K_0402_1%
<12,25>
<4>
APU_VDDNB_RUN_FB_L <4>
UGATE_NB
@
PR116
10K_0402_1%
PR115
105K_0402_1%
PC102
0.22U_0603_10V7K
4
APU_VDDNB_RUN_FB_H
PR113
0_0402_5%
LGATE_NB
PL16
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%
1
2
PR139
10_0402_5%
100P_0402_50V8J
2
1
1
2
PR111
0_0402_5% PR112
PHASE_NB
2
1
17.8K_0402_1%
LGATE_NB
+3VS
PR108
10_0402_5%
1
2 +APU_CORE_NB
@ PC122
2
1
PC105
0.1U_0603_25V7K
PHASE_NB
PR105
2.2_0603_1%
BOOT_NB
1
2 1
B+
PR109
2_0603_5%
+3VS
+5VS
3
2
1
UGATE_NB
PR106
22K_0402_1%
2
1
PR110
0_0402_5%
2
1
@ PC121
100P_0402_50V8J
2
1
PC101
0.1U_0603_16V7K
CPU_B+
PC100
1000P_0402_50V7K
2
1
1
+5VALW
PC95
4.7U_0805_25V6-K
2
1
PR104
2_0603_5%
1
2
PC94
1000P_0402_50V7K
3
2
1
PR103
44.2K_0402_1%
2
PQ27
AON7408L_DFN8-5
VSEN0
2
@ PC119
@PC119
100P_0402_50V8J
2
<4> APU_VDD0_RUN_FB_L
2
PR131
10_0402_1%
1
@ PC120
@PC120
100P_0402_50V8J
1 RTN0
0_0402_5%
PR132
DIFF_0
VW0
PR134
PC115
255_0402_1% 4700P_0402_25V7K
2
1 2
1
COMP0
PC116
100P_0402_50V8J
PR135
1K_0402_5%
2
1
PR136
2
PC118
2
1
+3VS
7.87K_0402_1%
PR133
2
1
6.49K_0402_1%
PR140
2
1
PC117
1000P_0402_50V7K
PR137
6.81K_0402_1%
2
1
54.9K_0402_1% 1200P_0402_50V7K
Compal Secret Data
PR138
36.5K_0402_1%
2010/08/12
Issued Date
2012/08/12
Deciphered Date
Title

CPU_CORE
Size
Date:
Document Number
Rev
1.0
Sheet
E
36
of
37
Version change list (P.I.R. List)

Item
Rev.
PG#
Modify DCIN/VIN DECTOR power sequence
30
Modify charger power sequence
31
Modify 3VALWP/5VALWP power sequence
32
Modify 3VALWP/5VALWP power sequence
Reason for change
Page 1 of 1 for PWR
Fixed Issue
Modify List
Date
Add PC248 for +3VALWP

PC252 for +5VALWP PC253 for +VSBP
PC254 for +1.1VALWP PC255 for +1.05VSP
PC256 for +0.75VSP
PC257 for +1.8VSP
Phase
20101228
EVT
delete PC234
20101228
EVT
delete PC34
20101228
EVT
31
Chang PD5 from SCS00000Z00 (RB751V-40_SOD323-2

to SCS00005I00 (SD103AWS SOD323-2)
20110104
EVT
31
Chang PD3 from SCS00001I80 ( B340A SMA ) to SCS00000W00 (SX34_SMA2)

Chang PQ4&PQ5 fromSB00000KI00(SI7121DN-T1-GE3 1P POWERPAK1212-8) to
SB00000KZ00(AON7403L_DFN8-5)
20110106
EVT
32
Chang PL6 &PL7 from SH00000F900(4.7UH_FDVE0630-H-4R7M=

P3_5.5A_20%) to SH00000MB00(4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%) 20110110
EVT
EVT
Modify 1.8VSP/1.5VP power sequence
33
Chang PL10 from SH00000F800(2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%)

20110110
to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)
Modify 1.1VALWP/1.05VSP power sequence
34

P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)
20110110
EVT
20110110
EVT
20110110
EVT
Modify CPU_CORE power sequence
36

P3_8.3A_20%) to SH00000M700(2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%)
10
Modify CPU_CORE power sequence
36
Chang PR112 from SD034237280 (23.7k_0402_1%) to SD034178280 (17.8k_0402_1%)

Chang PR123 from SD000002680 (6.98k_0402_1%) to SD034750180 (7.5k_0402_1%)
Chang PR127 from SD034187180 (1.87k_0402_1%) to SD00000JB80 (1.69k_0402_1%)
11
33
add PC258 to +1.5V output capacitor (co-lay higt from 4.5

to 2.5) for thermal issue
20110208
DVT
12
34
add PC259 to +1.1VALWP output capacitor (co-lay higt

from 4.5 to 2.5) for thermal issue
20110208
DVT
13
33
delete co-lay PC258 for +1.5V output capacitor
20110225
PVT
14
34
delete co-lay PC259 for +1.1VALW output capacitor
20110225
PVT
15
31
delete co-lay PJ32

modify PQ4 PQ5 footprint from AON7403L_DFN8-5 to SIS412DN-T1-GE3_POWERPAK8-5
20110226
PVT
16
31
change charger IC from G5209 to ISL6251

change output choke from 8.2u to 10u
20110226
PVT
17
Modify DCIN/VIN DECTOR power sequence
30
Add PC258 for +1.5V jump by RF test
2010302
PVT
18
19
20
21
22
A
23
Issued Date
Compal Secret Data
2010/08/12
Deciphered Date
2012/08/12
5
Title
PIR (PWR)
Custom
Date:
Rev
1.0
Sheet
1
37
of
37

Compal Confidential: P1VE6 LA7071P Schematics Document

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A

AMD Ontario Processor with DDRIII + Hudson M1

Compal Electronics, Inc.

Compal Secret Data

Thursday, March 17, 2011

Model Name : P1VE6

Memory Bus (DDRIII)

204 Pin DDRIII SO-DIMM x2

1.5V DDRIII 800/1066

PCIE Gen1 2.5GT/S

Gen1 1.5GT/S ,Gen2 3GT/S

Compal Electronics, Inc.

Compal Secret Data

DC/DC Interface Ckt.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.0V switched power rail

1.5V power rail for CPU VDDIO and DDRIII

0.75VS switched power rail for DDR terminator

1.05V switched power rail for NB VDDC & VGA

1.1VS switched power rail

1.8V switched power rail

3.3V always on power rail

1.1V always on power rail

3.3V switched power rail

1.5VS switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

DDR DIMM1 (FCH_SMB0)

APU SIC/SID (FCH_SMB3)

Board ID / SKU ID Table for AD channel

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

SMBUS Control Table

MINI Card LCD DDC ROM

Compal Secret Data

HDMI DDC ROM

APU C50 P/N change to SA00004KD50

8/25 Pull-up 100k(@ R352) to +3VS

10/01 Remove T1,T3~T7,T11,T12,T31,T32

PAD T13 R386 1

9/9 Add R386 (1k@) to +1.8VS on TEST35

8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P

Reserve C438 for ALLOW_STOP#

Reserve R389 for eDP function

S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!

9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L

Add C429 for APU_PROCHOT#

Connection to EC, FCH input

9/15 Change R24 from mount to @

9/9 Change R24 from @ to mount R26 from mount to @

10/05 Add 100p(C405) on LDT_RST#

Reserve C432, C433, C434, C435

Change R10, R11 to RP1

9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32

If FCH internal pull-up disabled, level-shifter could be deleted.

9/20 Delete R41~R43

If Q8 or R429, R432 implemented,

Reserve C421 for APU_PWRGD

8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)

Compal Secret Data