2011

UTM
2011



521.8 525.8
,
.
: lect. sup. Anatol Alexei
lect. sup. Andrei Chihai
: conf. univ. dr. Pavel Nistiriuc
: conf. univ. dr. Nicolae Secrieru

:
_________________________________________


Hrtie ofset. Tipar RISO

Coli de tipar
nr.
_________________________________________
U.T.M., 2004, Chiinu, bd. tefan cel Mare, 168.
Secia Redactare i Editare a UTM
2068, Chiinu, str. Studenilor, 9/9
3


1. Nr. 1
4
1.2
.4
1.3
..12
1.4
14
1.5
..14
2. Nr.2....15
2.2
15
2.3
..34
2.4
35
2.5
..35
3. Nr.3....36
3.2
36
3.3
..54
3.4
55
3.5
..55
4. Nr.4....56
4.2
56
4.3
..65
4.4
67
4.5
..67

 nr.1

1.1 :
.
.
.
1.2 Noiuni teoretice:
,
,

.
(
) 1
0 .
2 :




-
.
()
1.1.

.

-.

1.1

( )
(OR)
x1+ x2
x1 x2
x1 x2

(AND)
( )
x1 x2
x1 x2
x1 x2

(NOT)
x
x
x

1 0 .
y = x1 x2 +x3

(1.1)

( )
(
)
,
.
X1

1.2

&
&

X3

1.2

X1
0
0
0
0
1
1
1
1

X2
0
0
1
1
0
0
1
1

X3
0
1
0
1
0
1
0
1

Y
0
0
0
0
1
1
1
1

2n , n
.
( )

( 1.2).

1.2.1
1.3
N
r.

x
0
1

f
1
0

x1

x
0
0
1
1

y
0
1
0
1

f
0
0
0
1

x
0
0
1
1

y
0
1
0
1

f
1
1
1
0

x1

y = x1x2 x3 xn
y = x1 x2 x3

x2

x1
x2

y = x1 x 2 x3 ...x n

x
0
0
1

y =x

y
0x1
1x2
0

y = x1+x2++xn
y = x1x2xn

(AND)

- (NAND)

f
(OR)
0

1
1
1

1
5

x
0
0
1
1

y
0
1
0
1

f
1
0
0
0

y = x1 + x2 +... + xn

x1
x2

- (NOR)

x
0
0
1
1

y
0
1
0
1

f
0
1
1
0

x1

y = x1 x2 ... xxn2

(XOR)

1.2.2


.
:
1)
x1 x2 x3 = (x1 x2) x3 = x1 (x2 x3) = ... ; (1.2)
x1 + x2 + x3 = (x1 + x2) + x3 = x1 + (x2 + x3) = ... ; (1.3)
2)
x1 x2 = x2 x1;
(1.4)
x1 + x2 = x2 + x1;
(1.5)
3)
x1 (x2 + x3) = x1 x2 + x1 x3;
(1.6)
x1 + (x2 x3) = (x1 + x2) (x1 + x3);
(1.7)
4)
x +y =x y

x + y =x y

xy =x +y

xy =x + y

5)

x + xy = x

x( x + y ) = x

(1.8)
(1.9)

6)
xy + x y = x

( x + y )(x + y ) = x

(1.10)

7)
x =x

(1.11)

f ( x1 , x 2 ... x n ) = f ( x1 , x 2 ...x n )

8) ()
x x x... = x
(1.12)
x + x + x + ... = x
9)

x +0 = x
x 0 =0

x + x =1
x x =0

x +1 =1
x 1 = x

(1.13)

:
a)

,
.

( x + y )( x + z ) = x x + x y + x z + y z =
= x(1 + y + z ) + yz = x + yz

(1.14)

b)

( ). -
.
x y =x + y
(1.15)
1.2.3

.
:
a) (
)
.
: x1 + x 2 ; x1 + x 2 + x 3
10

b) (
)

.
: x1 x 2 ; x1 x2 x3
c)

.
: x1 + x1 x 2 + x1 x 3
d)

.
: ( x1 + x 2 ) ( x 1 + x 2 )( x1 + x3 )
e)

.

.
: x1 x 2 x3 + x1 x 2 x 3 + x1 x 2 x3 = f ( x1 x2 x3 )
f)

.
: ( x1 + x 2 + x3 ) ( x 1 + x 2 + x 3 ) = f ( x1 x 2 x3 )

.
,
y 1 ( 1.4).

0
1.
y = x 1 x 2 + x1 x 2

(1.16)

1.4
11

X1

X2

0
0
1
1

0
1
0
1

Y
1
0
1
0

,
y 0.
,
1
0.

)(

y = x1 + x 2 x 1 + x 2

(1.17)

1.2.4

.

, ,
, .

:
1)

12


.
2) .
1.2.4.1
( )
- P1 P2
,
( )
( ) .


.
( )
P1 P2 ,
( :
, ),
.
:
a)
(1.18).
b)
. (1.19).
c) a) b)
.
Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +
+ x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4

(1.18)
Y = x1 x2 x3 + x1 x2 x3 + x1 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 = x1 x3 + x1 x3 x4 +
+ x1 x2 x3 x4 + x1 x2 x3

(1.19)
1.2.4.2 .
13

.
,
.
,

.

:
a) ,,
b) ,
c) ,
d) -
e) -
f) - ,
,
,
.
.
a) ,,

y = x1 + x 2 x3
X1

X2

&

X3

1.3 ,,
b) ,
y = x 1 x 2 x3
X1
X2

X1

XX
& 1 2

X1 X 2

&

X3

1.4 ,

14

c) -
y =x1 x 2 x3 =x1 x1 x 2 x3

X1

&

X1

&

X1 X 2

&

X2
X3

X1 X 2 X 3

&

1.5 -
d) -

y = x1 + x2 x3 = x1 + x2 + x3 = x2 + 0 + x1 + x3 + 0

X2

X2

X1
X3
0

X3

1.6 -
1.3
1.3.1

.
1.3.2 :
,, , ,-,-
.
15

1.3.3
,
1.5.
1.3.4
Circuit
Maker.
1.3.5 .
1.5

V
1
2
3

Y = x1 x2 x3 x4 + x1 x2 x3 x4 +x1 x2 x3 x4 +x1 x2 x3 x4 +
x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +x1 x2 x3 x4
Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +
x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4

(x + x
1

4
5

)(

)(

)(

+ x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

)(

)(

Y = ( x1 + x2 + x3 + x4 ) x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

(x

)(

)(

)(

+ x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +x1 x2 x3 x4 +
x1 x2 x3 x4 +x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4

)(

)(

Y = x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

(x

)(

)(

+ x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

)(

)(

Y = ( x1 + x2 + x3 + x4 ) x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

(x

+ x1 x2 x3 x4 + x1 x2 x3 x4

)(

Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +

)(

Y = x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

)(

)(

)(

+ x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +
+ x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4

16

10

)(

Y = ( x1 + x2 + x3 + x4 ) x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

(x

)(

)(

+ x2 + x3 + x4 x1 + x2 + x3 + x4 x1 + x2 + x3 + x4

Y = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 x3 x4 +

11

1.
2.
3.
4.
5.
6.
7.

+ x1x2 x3 x4 + x1 x2 x3 x4 + x1x2 x3 x4 + x1 x2 x3 x4

1.4
;
;
;
;
;
Bazele standarde de elemente logice;
;

1.5
1. ,
;
2. Gheorge Toace, Dan Nicula Electronica digital, Editura
tehnic, Bucureti, 2005;
3. John Wakerly Circuite digitale: principii i practice folosite n
proiectare, Teora, Bucureti, 2002;
4. Mihaela Lupea, Andreea Mihi Logici clasice i circuite
logice Editura albastr, Cluj-Napoca, 2008;
5. I. Spnulescu, S. Spnulescu Circuite integrale digitale i
sisteme cu microprocesoare Editura Victor, Bucureti, 1996.

17

 nr.2

2.1


.
2.2
(...)

),

,
, .

2.1,
:
yk = yk (x1, x2, ... , xn),

(2.1)

k = 1, 2, ... , m.
x1
x2
.
.
.

.
.
.

C. L. C.

.
.
.

xn

y1
y2
ym

2.1 ..
2.1

-
.
18

 . ...


, , ,
,
,
c.l.c.

tpd.
2.2.1

, :
...
2.2.1.1

...

,
,
.
,
..., 2.2, ,
,
:
(2.2)
Y = AB + AB
A

AB

A
B

Y = AB + AB
B

AB

19

 2.2 XOR


2.1.

2.1
B
A
0
0
0
1
1
0
1
1

... 2.2
B

1
1
0
0

1
0
1
0

AB

0
0
1
0

AB

0
1
0
0

Y = A B + AB

0
1
1
0

- (XOR).
2.2.1.2
...

()
.
: () ,
.
,
:
a)
;
b) NAND;
c) NOR.
, :
Y = A B
(2.3)
, 2.2,
.
20

 2.2 XOR
B
A
Y
0
0
0
0
1
1
1
0
1
1
1
0
a)

2.2,
()
2.2. ,
2.2. ,
(),
:
Y = ( A + B ) (A + B ) ,
(2.4)
2.3.
A+B
A
B

Y = ( A + B) A + B

A+B
B

2.3 XOR
b) NAND
, . 2.2,
:

( ) ( ),

Y =AB +AB = AB AB

(2.5)

NAND 2.4.
21

+Vcc
A

2.4 XOR NAND

c) NOR
,
2.4, :
(2.6)
Y = ( A + B) (A + B ) = (A + B) + (A + B ) ,
NOR
2.5.
A
Y

2.5 XOR NOR

.
22

2.2.2

(MUX)

,
n , , 2.6.
A0

Ap-1

A1
. . .

I0
I1
.
.
.

In-1

.
.
.

MUX

2.6 -


() p .
n=2p,
,

.
2.2.2.1 4-
MUX n=4 (I0, I1, I2, I3),
p=2 (A0, A1).
,
MUX 4 , 2.5,
, . 2.7,
2.7.

23

2.5 MUX 4
A 1 A 0 I0
I1
I2
I3
Y
E
1
x
x
x
x
x
x
0
0
0
0
I0
x
x
x
I0
0
0
1
x
I1
x
x
I1
0
1
0
x
x
I2
x
I2
0
1
1
x
x
x
I3
I3
+Vc
c

A1

A0

A0

A1

I0
I1

I2
I3

2.7 MUX 4
Y = E ( A1A 0 I 0 + A1A 0 I1 + A1A 0 I 2 + A1A 0 I 3 ).

P0

P1

P2

P3

(2.7)

E (ENABLE) , "L".
E =1 ,
,
0 MUX .
2.2.3
24

 (DMUX) ...
,
m
(a).
DMUX m p
(m=2p) 2.8.
A0

A1

. . .

Ap-1

. . .

Y0
DMUX
I

.
.
.

Y1
.
1.
.

Ym-1

2.8 - DMUX
2.2.3.1 4
m=4 (Y 0,Y1, Y2,
Y3), p=2 (A0,A1).
2.6 DMUX 4

A1
A0
I
Y0
Y1
Y2
Y3
0
0
I
I
0
0
0
0
1
I
0
I
0
0
1
0
I
0
0
I
0
1
1
I
0
0
0
I
,
2.6, :
25

Y0 = I A1 A 0 ,

Y1 = I A1A 0 ,

Y2 = I A1 A 0 ,

Y3 = I A1 A 0 ,

(2.8)

2.9.
A1

A0

+Vcc

I
Y0

Y1

Y2

Y3

2.9 DMUX 4-

2.2.4
n
m ,


(M.S.I.) (L.S.I.) : ,
ROM, PLA, ...
26

 2.10.
A0
A2

I1
I2
.
.
.

In

.
.
.

CD

.
.
.

.
.
.

Am-1

2.10 -
2.2.4.1

m , n
.
2.12

I1
I2 I3 I4 I5 I6 I7 A2
A1 A0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
)
n=2m-1 .
,
n=7 , m=3
.
, 2.12,
, . 2.9, 2.10 2.11,
2.11:
A0 = I1 + I3 + I5 + I7 ;
(2.9)
A1 = I2 + I3 + I6 + I7 ;
(2.10)
27

A2 = I4 + I5 + I6 + I7 .
I1

I2

I3

I4

I5

I6

I7

(2.11)

+Vcc

A0

A1

A2

2.11
:

. , I 1 I2
A2=0, A1=1, A0=1 (011)
,

,
I3.
,
().
7 3

2.12, 2.13 2.14
:
A 0 = I1 + I 3 + I 5 + I 7 = I1 I 3 I 5 I 7
A1 = I 2 + I 3 + I 6 + I 7 = I 2 I 3 I 6 I 7
A 2 =I 4 + I 5 + I 6 + I 7 = I 4 I5 I6 I7

(2.12)
(2.13)
(2.14)
28

 2.12.

I1 I2 I3 I4 I5 I6 I7

+Vcc

A0

A1

A2

2.12

2.2.5

n m ,
MSI ,

(m=2n).
2.13.

29

A0

Y0
Y1

A1
.
.
.

.
.
.

DCD

.
.
.

.
.
.

Ym-1

An-1

2.13 -
2.2.5.1

, .
n=2
m=22=4 2.14.
Y0

A0
A1

Y1

DCD

Y2
Y3

2.14 - 2 4

, 2.13,
2.15 2.15.
2.13 2
4
A1
A0
Y0
Y1
Y2
Y3
30

0
0
1
1

0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

Y0 = A1A 0 ; Y1 = A1A 0 ; Y2 = A1A 0 ; Y3 = A1A 0

A1

A0

(2.215)

+Vcc

Y0

Y1

Y2

Y3

2.15 2
4
2.2.5.2 BCD - 7
BCD - 7
2.16 BCD

( ) 7-

A0 A1 A2 A3
0, 1, .., 9.
DCD
BCD - 7 sgm

....
....

31

 2.16 - BCD - 7

7
, a, b, , g
7 , 2.17 a, LED
(), 2.17 b.
,
a , b,..., g
LED
(),
2.17 c.
, LED
() (), ,
, LED-,
+VCC, .
AC.

a
f

b
b

.
.
.

.
.
.

.
.
.

.
.
.

d
KC (la mas)

(a)

(b)

AC (la +VCC)

(c)

2.17 7 ,
32

a) ; b) ;
c) .

2.2.5.3 BCD - 7

,
BCD - 7
.


, 2.15,
0 15, 2 5
,
( ),
7 a, b, , g, 1
.
,

,

2.15,
2.18.
2.15 BCD 7

A A A A a b c d e f
g
0
1
2
3
4
5

0
0
0
0
0
0

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

1
0
1
1
0
1

1
1
1
1
1
0

1
1
0
1
1
1

1
0
1
1
0
1

1
0
1
0
0
0

1
0
0
0
1
1

0
0
1
1
1
1
33

6
7
8
9
10
11
12
13
14
15

0
0
1
1
1
1
1
1
1
1

1
1
0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1

1
1
1
1
x
x
x
x
x
x

0
1
1
1
x
x
x
x
x
x

1
1
1
1
x
x
x
x
x
x

1
0
1
1
x
x
x
x
x
x

1
0
1
0
x
x
x
x
x
x

1
0
1
1
x
x
x
x
x
x

1
0
1
1
x
x
x
x
x
x

0 LED a, b, c, d, e f,
.
, 2.15
, g,
.

0 9.

2.18 7

34

 10
15, BCD,
, x
2.15.
a, b, , g,
7 , ,
.

A 7 ,
A1A0 A
1 0
00
01
11
10
01
10
00

2.19,
11

A3A2
A3A2
,



00
00
0
0 .
01

11

01

10

A1A0
A3A2

01

00

11

10

11

10

10

A1A0
A3A2

00

00

01

0
x

11

10

11

10

0
x

A1A0
01

11

00
01

10

A3A2

01

11

11

10

10

01

00

00

A3A2

01
11

A1A0

00

00

01

11

10

x 35

(a)
(b)

(c)

(d)

(e)
A1A0
A3A2

00

(f)

00

01

01
11
10

11

10

0
x

2.19
7

2.19 (g)
36

 7
()
:

.
, .
A3

A2

A1

A0

A 3 A 2 A1
aFMC

bFMC

gFMC

continuare 2.20 BCD 7

(
(

)(

a FMC = A3 + A 2 + A1 + A0 A 2 + A1 + A0 ;
bFMC = A 2 + A1 + A0 A 2 + A1 + A0 ;

)(

(2.23)
37

)(

g FMC = A3 + A 2 + A1 A2 + A1 + A0 ,

BCD 7
2.20.
2.3 :
1.
6-
,
2,16:
2.16 .

2
3
4
5

7
8
9
10

, ,

,
,
-
-
, ,

,
,
-
-

2
3
4
2
3
4
2
3
4
2

:
a)
;
38

b)
;
c)
;
d)
DNC Circuit
Maker.
1.
.

2.4 :
1.

DDC;
2. DDC;
3.

DDC;
4. BCD 7
;
5.

BCD 7 ;
2.5
1. Anatol Alexei Cursul de prelegeri Electronica digital,
sub form de manuscris;
2. Gheorge Toace, Dan Nicula Electronica digital,
Editura tehnic, Bucureti, 2005;
3. John Wakerly Circuite digitale: principii i practice
folosite n proiectare, Teora, Bucureti, 2002;
4. Mihaela Lupea, Andreea Mihi Logici clasice i circuite
logice Editura albastr, Cluj-Napoca, 2008;
5. I. Spnulescu, S. Spnulescu Circuite integrale digitale i
sisteme cu microprocesoare Editura Victor, Bucureti,
1996.
39

 nr.3


3.1 :
,
.
3.2 :

intrri
funcionale

3.1.
X1
.
.
.
XnT
(TT)Q

regim normal de funcionare

ieirea
direct

ieirea
invers

3.1 .

.
,
.

40

 :
a)
b)
c)
d)
e)
a)
b)

.
RS .
D - .
T - (
).
JK - .
Bistabile complexe
.
.

.

. ,
. 3.2
.

D
CTQ

3.2 T

:
a)
.
:
41

a.1. C
a.2. C
b)
.
:
b.1. C
b.2. C
3.3

,
C -

,
C -

,
C -

,
C -

3.3
:
a) .
b) .
:
a)
.
b) master-slave
, .

42

3.2.1. SR
SR (CBB-SR)
.
1.
CBB-SR
, "master-slave" (-).

3.2.1.1 SR
SR,
- latch
(), NOR NAND
.
SR
NOR
SR NOR
3.4
3.1, n

n+1
.
3. CBB-SR ,
NOR
Sn
Rn
Qn+1
0
0
Qn
0
1
0
1
0
1
43

R
S
P1

a)

b)

3.4 CBB-SR , NOR

Q
3.4, :

Q n +1 =Sn +
R n +Q n =Sn +R n Q n .

(3.1)
3.1,
:
Q n +1 = Sn + R n Q n .
(3.2)
3.2
3.5.
,
3.1, :
SR
Qn n n 00

01

11

10

1
Sn

3.5 CBB-SR NOR

44

- SnRn = 00, Qn+1=Qn (

), Qn
SnRn = 00 ;
- SnRn=01(10), Qn+1=0(1) Qn
()
0(1).
- SnRn=11, ()
0-,
(inadmisibil)

:
Q n +1 = Q n +1 = 0 .
(2.3)
- SnRn=11
(

3.1
3.5, "x",
.
3.2.
S (SET) R (RESET) latch- SR
: , .
, SnRn=10,
Sn
, Qn+1=1.
, SnRn=01 Rn
: Qn+1=0.
3.2
3.1.
SR
NAND
SR
NAND

3.6,
R
S
3.2.
P

P2

45

a)

b)

Figura 3.6 CBB-SR , NAND

3.2 CBB-SR ,
NAND
Sn
Rn
Qn+1
1
1
0
0

1
0
1
0

Qn
0
1
x

3.6 :
Q n +1 =S n
R n Q n
=S n +R n Q n ,
(3.4)

. 3.2,
SR NOR .
Qn+1
3.7.
Sn R n

00

01

11

10

Qn

Sn

R nQn

46

 3.7 CBB-SR ,
NAND
,
CBB-SR :
-
,
;
- ,
.
Exemplu: Tranziia 1100 ,
Q, Q CBB 3.6
. , SnRn=11,
Q
0, Q= =0,
() P1, P2. SnRn=00
() P1 ,
Q ,
- 0 Q.
,
()P2,

.
3.2.1.2 SR
SR
(), 3 4,
( 3.8 i 3.9).

CBB-SR

,
3.6 a.
CLK =1 , () 3 4
S R CBB47

SR , () 1 2.
, CLK =1 , SnRn=00 ,
3.1, Qn+1=Qn
.
CLK =0 , () 3 4
S R , SR,
CBB-SR ,
3.1.

CLK =0 ,
S R ,
. S R
() 3 4 ,
. - ,
() CLK S R .

CLK R

S
3

4
R

a)

CLK
R

b)

3.8 CBB-SR , NOR

3

S
1

S CLK R
Q
48

a)

b)

3.9 CBB-SR , NAND

3.8 , impulsul
de tact fiind de aceast dat activ pe palierul superior (1
) .

3.2.1.3 SR Master-Slave
3.10, SR
Master-Slave SR

NAND (.
3.9).
3.11 a), CLK CLK -
3.11 b) c).
S CLK R
SM

RM
M

QM

SS RS
S

49

QS
Q

 3.10 CBB-SR-MS

(1)-(2), . b c 3.9,
(3M, 4M) (3S, 4S)
, MASTER
SLAVE.
(2)-(3), CLK=1 3M, 4M
, MASTER;
3S, 4S ( CLK =0 ), SLAVE
MASTER.
(3)-(4)
(1)-(2) MASTER
SLAVE.
, (4), 3M, 4M
CLK
(MASTER
) 3S,
R
S
4S MASTER

SLAVE.

3M
4M MASTER
CBB-SR
(3) (

MASTE
CLK), SLAVE (

R
) 1M CBB-SR
(4)
(

sincron
MASTE
2M
CLK).
R
asincron

CLK
3S

Pori
transfer

4S

1S

2S

CBB-SR
SLAVE
asincron

CBB-SR
SLAVE
sincron
50

a)

CLK

b)

"1
"
"0"

(2
)
(1
)

(3
)
(4
)

(1
)
(2
)

(4
)
(3
)

CLK

"1"
c)
"0"

t
51

 3.11 CBB-SR-MS: a) ; b), c)

, CBBSR-MS,
(3)-(4).


, CBB-SR-MS
(.
3.1 3.2).
, CBB-SR-MS

(care s comute pe tranziia pozitiv a impulsului de tact).
3.2.2 D
D
, Master-Slave.
3.2.2.1 D
D, 3.12,
CBB-SR ( 3.4,
3.1 3.6,
3.2),
.
D

52

 3.12 D
, 3.1
2 3 D n = S n = R n , 3.3.
3.3 CBB D
Qn
x
x

Dn = S n = Rn

1
0

Qn+1
1
0

(. 3.3),
.
3.2.2.2 D
CBB D
3.13 3.14
SR,
3.8 3.9.

CLK

Q
53

a)
b)
Figura 3.13 CBB-D palierul inferior
al CLK
D
CLK
S

a)

CLK

b)

3.14 CBB-D de palierul

superior al CLK
CBB-SR ,
CLK,
D palierului
activ ( CLK = 0 3.13 i
CLK=1 3.14), palierului respectiv
. palierului activ
CLK
.


,
CLK. ,
D, DELAY=.
54


3.15
latch- D 2 , din
structura circuitului integrat CDB 472, 3.4
latch-.
D

E (CLK)

Q0

Q0

3.15 latch- D
CI - CDB 472
3.4 latch- D
3.15

E
D
Qn+1
Qn +1

1
0
0
1

1
1
1
0

0
x
Qn
Qn

D
, : latch,
RAM, ...
3.2.3 T
T D
(reactii) 55

unui circuit, 3.16.

T

CLK
CLK

Q
Q

a)

b) -

3.16 T
3.5 T
Tn
Qn+1
0
Qn
1
Qn
, 3.5,
;
Q n +1 = Q n Tn + Q n Tn = Q n T

(3.5)

T 2.20
propiu-zis ( SR D),

(, avnd un comportament definit att de
intrare ct i de starea n care se afl.).
, ,
.
56

3.2.4 JK

D

SR.

()reacii SR.
3.2.4.1 JK
JK , 3.17,
SR
(reacii).
J

3.17 JK
3.17
:
Sn = J n Qn

(3.6)
(3.7)

R n = K nQn ;
Qn +1 = K n Qn + ( J n Qn + Qn ) = ( K n Qn )( J n Qn + Qn ) =
= ( K n + Qn )( J n Qn + Qn ) = K n J n Qn + K n Qn + J n Qn ;
Q n +1 = J n Qn + K n Q n

(3.8)
57

 . 3.9 CBB-SR
, 3.1 3.6.
3.6 CBB-JK
Jn
Kn
Sn
Rn
Qn+1
0
0
0
0
Qn
0
1
0
Qn
0
Qn
1
0
0
1
Qn
Qn
1
1
Qn
Jn=Kn=1, Q n +1 = Q n ,
0 1 .
3.2.4.2 JK
CBB-JK , 3.18,

3.7.
CL
K

3.18 JK
58

 3.7
JK
Jn
Kn
CLK
Qn+1
0
0
Qn
01

1
0
1
01

0
1
0
01

1
1
Qn
01

x
x
0
Qn

0
1
1
01

0
1
0
01

J K
T , Jn=Kn=Tn=1,
CLK.
1.2
1.

SR

;
2. D
;
3. JK

, J
K i ;
4. T
;
5. Circuit Maker;
6. .
1.3
1. ;
59

2.
3.
4.
1.
2.
3.
4.
5.

ale
;
;
JK.
1.4
Anatol Alexei Cursul de prelegeri Electronica digital, sub
form de manuscris;
Gheorge Toace, Dan Nicula Electronica digital, Editura
tehnic, Bucureti, 2005;
John Wakerly Circuite digitale: principii i practice folosite
n proiectare, Teora, Bucureti, 2002;
Mihaela Lupea, Andreea Mihi Logici clasice i circuite
logice Editura albastr, Cluj-Napoca, 2008;
I. Spnulescu, S. Spnulescu Circuite integrale digitale i
sisteme cu microprocesoare Editura Victor, Bucureti, 1996.

60

 nr.4

4.1 :


.
4.2 :


. ,
,
,

.
4.2.1

:
1. (
):
a)
,
;
b)

.
2. ():
a) (coninutul)
;
b)
;
61

c) ,
.
3. :
a)
b)

Mn 2n-1,
(4.1)
n ;
Cn=2n-1,

(4.2)

Cn - .
4. :
a) ():
Mn = 2n-1;
(4.3)
b)
,
Mn < 2n-1;
(4.4)
5. :
a)

;
b) 1 2

;
c)
, .
4.2.2

4.1 a).
n cascad a bistabililor de tip JK
T, 4.1.
62

Q1

Q0
CBB0

1
J
CKin

CBB2

1
Q

CK

CK
K

CBB1

Q2

CBB3

1
Q

CK

CK
R

Q3

Reset

4.1
Q0, Q1, Q2, Q3 ,
.
R Reset,
, 0000.
JK 1 ,

.

.

4.2.
CKin
Q0
Q1
Q2
Q3
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
7
1
2
8
16
0
3
4
5
6
9
10
11
12
13
14
15

4.2

63

Numrtorul este modulo 15, ,

0000 1111. basculeaz
.

, ,
.
,
, .
4.1
a)
b)

Nr.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Nr.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Q0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Q1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

Q2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

Q3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

4.2.3
4.3.

64

Q1

Q0
CBB0

1
J
CKin

CBB2

1
Q

CK

CK
K

CBB1

Q2

CK
R

Reset

4.3
Numrtorul este modulo 7,
, 111 000. basculeaz

4.4.

4.4

4.2.4
( 4.5)
()
(). T JK
D-MS.

U/nD
(UP/nDOWN).
,
4.6.
- U/nD = 1 Qk Ck+1,
65

 ;
- U/nD = 0 Q k
.

Ck+1,

4.5

4.6 2:1
4.2.5


o .
,
, JK, CLK .

,
.
66


4.7:
CBB0

1
K
CKin

CK
J

CBB2

CBB1
K

CK
R

CBB3
K

CK
R

CK
R

Q
Reset

Q0

Q1

Q2

Q3

4.7
J K 1
(
). 2 2
, Q0 1
0, .
4 4
Q1 Q0,
8 8
Q2 Q1 Q0.


, .( n cazul
numrtorului binar sincron de tip serie porile logice de tip I
utilizate vor fi toate cu 2 intrri, ca n schema logic anterioar.)

(porti)

, 4.8,
.

67

CBB0

1
K
CKin

CK
J R

CBB2

CBB1

CK
Q

CBB3
K

CK
R Q

CK
R Q

R Q
Reset

Q0

Q1

Q2

Q3

4.8

,
.
4.2.6

, Count-Up
( ) Count-Down ( ).
(Carry)
( mprumut) (Borrow),
( 4.9).

4.9
4.2.7 modulo p
p 2n-1

. : 2n-1 p.
68

 ,
((2n-1) p).
,
.
: modulo 5.
2n-1 5 n = 3, 3
. :
23 5 = 8 5 = 3.

JK .

,
JK 3
4.4.
( 4.2
( 4.3) JK .
6 ( 4.5)
(4.5).
.
4.2
4.3
JK
JK
J
0
0
1
1

K Qt Qt+1
0 0 0
1 1
1 0 0
1 0
0 0 1
1 1
1 0 1
1 0

Qt
0
0
1
1

Qt+1
0
1
0
1

J
0
1
X
X

K
X
X
1
0

4.4
69

Nr
0
1
2
3
4
5

tn

tn+1

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0

J2
0
0
0
1
x
x

K2 J1 K1 J0
x 0 x 1
x 1 x x
x x 0 1
x x 1 x
0 0 x 1
1 0 x x

K0
x
1
x
1
x
1

4.5
J2
Q0
Q2Q1
00
01
11
10

K2

J1

K1

J0

K0

0
0
x
x

0
1
x
x

x
x
x
0

x
x
x
1

0
x
x
0

1
x
x
0

x
0
x
x

x
1
x
x

1
1
1
1

x
x
x
x

x
x
x
x

1
1
1
1

(4.5)

modulo 5
4.10:

70

CBB0

1
K
CKin

CBB2

CBB1
K

CK

CK

J R Q

CK
R Q

J R Q
Reset

Q0

Q1

Q2

4.10
4.3

4.6:
. :
1.
C.
2. .
3.
.
4.

.
5.
.
6.

.
7.
,
.
8. Circuit Maker
.
71

9. .
4.6
.

10

dir. inv. dir. inv. dir. inv. dir. inv. dir. inv.
.
14 13 12
14 9 12 1 1
10 1 3 14
C
RS JK RS JK RS JK RS JK RS JK
. inv. dir. inv. dir. inv. dir. inv. dir. inv. dir.
.

I- I SAU- SAU I- I SAU- SAU I SAU

NU NU NU NU NU NU NU N U NU NU

- 2 3 4 2 3 4 2 3 4 2
.
4.4
1. ;
2. ;
3.
;
4. ;
5.
;
4.5
72

1. Anatol Alexei Cursul de prelegeri Electronica digital, sub

form de manuscris;
2. Gheorge Toace, Dan Nicula Electronica digital, Editura
tehnic, Bucureti, 2005;
3. John Wakerly Circuite digitale: principii i practice folosite
n proiectare, Teora, Bucureti, 2002;
4. Mihaela Lupea, Andreea Mihi Logici clasice i circuite
logice Editura albastr, Cluj-Napoca, 2008;
5. I. Spnulescu, S. Spnulescu Circuite integrale digitale i
sisteme cu microprocesoare Editura Victor, Bucureti, 1996.

73