Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar

Cpr E 305 Lab Verilog Synthesis Handbook

Vignesh Vijayakumar
December 9, 2004 (Fall)
Lab TA: Ganesh Subramanian

Page 1 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar

Table of Contents


Quad I nput NOR Gate.................................................................................................. 3
D Flip Flop using NOR Gates........................................................................................ 4
2:1 Mux using Gates .................................................................................................... 5
4:1 Mux using 2:1 Muxes............................................................................................. 6
Full Adder..................................................................................................................... 7
8:1 Mux using 4:1 & 2:1 Muxes ................................................................................... 8
Octal to Binary Encoder ............................................................................................. 10
4 Bit Comparator........................................................................................................ 11
4x4 Multiplier............................................................................................................. 12
4 Bit Serial I n Parallel Out Register........................................................................... 14
Serial Adder FSM........................................................................................................ 15
Sequence Detector FSM............................................................................................. 17
Single Cycle CPU........................................................................................................ 19
Multi Cycle CPU.......................................................................................................... 33

Page 2 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Quad I nput NOR Gate

Lab Session: 1

Verilog Code:

module quadinpNOR4 (In0, In1, In2, In3, Out);

input In0, In1, In2, In3;
output Out;
assign Out = ~(In0 | In1 | In2 | In3);

endmodule

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Page 3 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
D Flip Flop using NOR Gates

Lab Session: 1

Verilog Code:

module DFFNOR (Clk, D, Q, Qbar);

input Clk, D;
output Q, Qbar;
wire w0, w1, w2, w3, w4, w5, w6;

quadinpNOR4 RESULTA(w0, w1, 1'b0, 1'b0, w3);
quadinpNOR4 RESULTB(w3, Clk, 1'b0, 1'b0, w1);
quadinpNOR4 RESULTC(w1, w0, Clk, 1'b0, w4);
quadinpNOR4 RESULTD(w4, D, 1'b0, 1'b0, w0);
quadinpNOR4 RESULTE(w1, w5, 1'b0, 1'b0, w6);
quadinpNOR4 RESULTF(w6, w4, 1'b0, 1'b0, w5);

assign Q = w6;
assign Qbar = w5;

endmodule

module quadinpNOR4 (In0, In1, In2, In3, Out);

input In0, In1, In2, In3;
output Out;
assign Out = ~(In0 | In1 | In2 | In3);

endmodule

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Page 4 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
2:1 Mux using Gates

Lab Session: 2

Verilog Code:

module mux21 (A, X0, X1, X);

input A, X0, X1;
output X;
assign X = ((A & X1) | (~A & X0));

endmodule

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Page 5 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
4:1 Mux using 2:1 Muxes

Lab Session: 2

Verilog Code:

module mux41 (D0, D1, D2, D3, S0, S1, Q);

input D0, D1, D2, D3, S0, S1;
output Q;
wire w0, w1;

mux21 RESULTA(S0, D0, D1, w0);
mux21 RESULTB(S0, D2, D3, w1);
mux21 RESULTC(S1, w0, w1, Q);

endmodule

module mux21 (A, X0, X1, X);

input A, X0, X1;
output X;
assign X = ((A & X1) | (~A & X0));

endmodule

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Page 6 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Full Adder

Lab Session: 2

Verilog Code:

module fulladder (A, B, CIN, COUT, SUM);

input A, B, CIN;
output COUT, SUM;

assign COUT = ((B & CIN) | (A & CIN) | (A & B));
assign SUM = (A ^ (B ^ CIN));

endmodule

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Page 7 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
8:1 Mux using 4:1 & 2:1 Muxes

Lab Session: 3

Verilog Code:

module mux81 (D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2, Q);

input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
output Q;
wire w0, w1;

mux41 RESULTA(S0, S1, D0, D1, D2, D3, w0);
mux41 RESULTB(S0, S1, D4, D5, D6, D7, w1);
mux21 RESULTC(S2, w0, w1, Q);

endmodule

module mux41 (D0, D1, D2, D3, S0, S1, Q);

input D0, D1, D2, D3, S0, S1;
output Q;
wire w0, w1;

mux21 RESULTA(S0, D0, D1, w0);
mux21 RESULTB(S0, D2, D3, w1);
mux21 RESULTC(S1, w0, w1, Q);

endmodule

module mux21 (A, X0, X1, X);

input A, X0, X1;
output X;
assign X = ((A & X1) | (~A & X0));

endmodule



















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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
8:1 Mux using 4:1 & 2:1 Muxes

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Page 9 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Octal to Binary Encoder

Lab Session: 3

Verilog Code:

module oct2binenc (In, Out);

input [7:0] In;
output [2:0] Out;
assign Out[0] = (In[4] | In[5] | In[6] | In[7]);
assign Out[1] = (In[2] | In[3] | In[6] | In[7]);
assign Out[2] = (In[1] | In[3] | In[5] | In[7]);

endmodule

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Page 10 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
4 Bit Comparator

Lab Session: 3

Verilog Code:

module fourbitcomp (A, B, Out);

input [3:0] A, B;
output [4:0] Out;
wire [3:0] C, S;

fulladder RESULT0(A[0], 1'b1^B[0], 1'b1, C[0], S[0]);
fulladder RESULT1(A[1], 1'b1^B[1], C[0], C[1], S[1]);
fulladder RESULT2(A[2], 1'b1^B[2], C[1], C[2], S[2]);
fulladder RESULT3(A[3], 1'b1^B[3], C[2], C[3], S[3]);

assign Out[0] = S[3]; //done
assign Out[1] = ~S[3]; //done
assign Out[2] = ~Out[1]; //done
assign Out[3] = ~(S[3] | Out[4]); //done
assign Out[4] = ~(S[0] | S[1] | S[2] | S[3] | (C[2]^C[3])); //done

endmodule

module fulladder (A, B, CIN, COUT, SUM);

input A, B, CIN;
output COUT, SUM;

assign COUT = ((B & CIN) | (A & CIN) | (A & B));
assign SUM = (A ^ (B ^ CIN));

endmodule

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
4x4 Multiplier

Lab Session: 3

Verilog Code:

module mult44 (A,B,P);

input [3:0] B;
input [3:0] A;
output [7:0] P;
wire [19:0] S;
wire dummy;
wire [18:0] C;

fulladder ROW11(1'b0,(A[0] & B[0]), 1'b0, C[0], S[0]);
fulladder ROW12(1'b0,(A[1] & B[0]), 1'b0, C[1], S[1]);
fulladder ROW13(1'b0,(A[2] & B[0]), 1'b0, C[2], S[2]);
fulladder ROW14(1'b0,(A[3] & B[0]), 1'b0, C[3], S[3]);

fulladder ROW21(S[1],(A[0] & B[1]), C[0], C[4], S[4]);
fulladder ROW22(S[2],(A[1] & B[1]), C[1], C[5], S[5]);
fulladder ROW23(S[3],(A[2] & B[1]), C[2], C[6], S[6]);
fulladder ROW24(1'b0,(A[3] & B[1]), C[3], C[7], S[7]);

fulladder ROW31(S[5],(A[0] & B[2]), C[4], C[8], S[8]);
fulladder ROW32(S[6],(A[1] & B[2]), C[5], C[9], S[9]);
fulladder ROW33(S[7],(A[2] & B[2]), C[6], C[10], S[10]);
fulladder ROW34(1'b0,(A[3] & B[2]), C[7], C[11], S[11]);

fulladder ROW41(S[9],(A[0] & B[3]), C[8], C[12], S[12]);
fulladder ROW42(S[10],(A[1] & B[3]), C[9], C[13], S[13]);
fulladder ROW43(S[11],(A[2] & B[3]), C[10], C[14], S[14]);
fulladder ROW44(1'b0,(A[3] & B[3]), C[11], C[15], S[15]);

fulladder ROW51(S[13], C[12], 1'b0, C[16], S[16]);
fulladder ROW52(S[14], C[13], C[16], C[17], S[17]);
fulladder ROW53(S[15], C[14], C[17], C[18], S[18]);
fulladder ROW54(1'b0, C[15], C[18],dummy , S[19]);

assign P[0] = S[0];
assign P[1] = S[4];
assign P[2] = S[8];
assign P[3] = S[12];
assign P[4] = S[16];
assign P[5] = S[17];
assign P[6] = S[18];
assign P[7] = S[19];

endmodule

module fulladder (A, B, CIN, COUT, SUM);

input A, B, CIN;
output COUT, SUM;

assign COUT = ((B & CIN) | (A & CIN) | (A & B));
assign SUM = (A ^ (B ^ CIN));

endmodule


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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
4x4 Multiplier

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Page 13 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
4 Bit Serial In Parallel Out Register

Lab Session: 5

Verilog Code:

module fourbitsinpoutreg (Clk, in, Out);

input Clk, in;
output [3:0] Out;
wire ground;

DFFNOR RES1(Clk, in, Out[0], ground);
DFFNOR RES2(Clk, Out[0], Out[1], ground);
DFFNOR RES3(Clk, Out[1], Out[2], ground);
DFFNOR RES4(Clk, Out[2], Out[3], ground);

endmodule

module DFFNOR (Clk, D, Q, Qbar);

input Clk, D;
output Q, Qbar;
wire w0, w1, w2, w3, w4, w5, w6;

quadinpNOR4 RESULTA(w0, w1, 1'b0, 1'b0, w3);
quadinpNOR4 RESULTB(w3, Clk, 1'b0, 1'b0, w1);
quadinpNOR4 RESULTC(w1, w0, Clk, 1'b0, w4);
quadinpNOR4 RESULTD(w4, D, 1'b0, 1'b0, w0);
quadinpNOR4 RESULTE(w1, w5, 1'b0, 1'b0, w6);
quadinpNOR4 RESULTF(w6, w4, 1'b0, 1'b0, w5);

assign Q = w6;
assign Qbar = w5;

endmodule

module quadinpNOR4 (In0, In1, In2, In3, Out);

input In0, In1, In2, In3;
output Out;
assign Out = ~(In0 | In1 | In2 | In3);

endmodule

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Serial Adder FSM

Lab Session: 5

Verilog Code:

module serialadder(Clk, In, In2, Out);

input Clk, In, In2;
output Out;

parameter C0 = 1'b0;
parameter C1 = 1'b1;

reg state, nextstate, Out;

always @ (posedge Clk)
begin
state <= nextstate;
end

always @ (In or In2 or state)
begin
case({state, In, In2})
3'b000: begin
nextstate = C0;
Out = 1'b0;
end
3'b001: begin
nextstate = C0;
Out = 1'b1;
end
3'b010: begin
nextstate = C0;
Out = 1'b1;
end
3'b011: begin
nextstate = C1;
Out = 1'b0;
end
3'b100: begin
nextstate = C0;
Out = 1'b1;
end
3'b101: begin
nextstate = C1;
Out = 1'b0;
end
3'b110: begin
nextstate = C1;
Out = 1'b0;
end
3'b111: begin
nextstate = C1;
Out = 1'b1;
end
endcase
end

endmodule


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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Serial Adder FSM

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Page 16 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Sequence Detector FSM

Lab Session: 5

Verilog Code:

module sequencedetector(Reset, Clk, In, out);

input Reset, Clk, In;
output out;

parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;

reg out;
reg[1:0] state, nextstate;

always@ (posedge Clk or posedge Reset)
begin
if(Reset == 1'b1)
state <= A;
else
state <= nextstate;
end

always@ (In or state)
begin
case({state, In})
//State A
3'b000:
begin
nextstate = B;
out = 1'b0;
end
3'b001:
begin
nextstate = A;
out = 1'b0;
end
//State B
3'b010:
begin
nextstate = B;
out = 1'b0;
end
3'b011:
begin
nextstate = C;
out = 1'b0;
end
//State C
3'b100:
begin
nextstate = D;
out = 1'b0;
end
3'b101:
begin
nextstate = A;
out = 1'b0;
end
//State D
3'b110:

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
begin
nextstate = B;
out = 1'b0;
end
3'b111:
begin
nextstate = C;
out = 1'b1;
end

endcase
end
endmodule

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Page 18 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
Single Cycle CPU

Lab Session: 8

Verilog Code:

module cpu(cycle, pc, inst, alu_out, mem_out, clock,
jump, regdst, aluop, alusrc, branch, memread,
memwrite, regwrite, memtoreg, zero);

// input/output
input clock;
output[31:0] cycle, pc, inst, alu_out, mem_out;
output jump, regdst, alusrc, branch, memread, memwrite, regwrite,
memtoreg;
output[1:0] aluop;
output zero;

// for debug
reg[31:0] cycle = 32'b0;
always @ (posedge clock)
cycle = cycle + 1;

/*
* "global" variables
*/

// control variables
wire jump, regdst, alusrc, branch, memread, memwrite, regwrite,
memtoreg;

// register address and data
wire[4:0] reg_a, reg_b, reg_c;
wire[31:0] val_a, val_b, val_c;

// ALU-related variables
wire[1:0] aluop;
wire[3:0] alu_con;
wire zero;

// other variables
reg[31:0] pc = 32'b0;
wire[31:0] branch_target;
wire[31:0] jump_target;
wire[31:0] imm_value;

/*
* inst fetch
*/

// update pc
wire[31:0] pc_plus_4 = pc + 4;

wire branch_taken = branch & zero;

wire jump_taken = jump & zero;

wire[31:0] next_pc = ~jump_taken ? (branch_taken ? branch_target :
pc_plus_4) : jump_target;

always @ (posedge clock) begin
pc <= next_pc;

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
end

// inst memory
// Instantiate your instruction memory here
Imem IMEMRESULT(pc>>2, inst);

/*
* Decode, register file (reg read and writeback)
*/

// Decode control signals
wire[31:0] rom_out;
assign
{jump,regdst,alusrc,memtoreg,regwrite,memread,memwrite,branch,aluo
p} = rom_out[9:0];

// Instantiate your microcode control unit here
MCCtrl MCCTRLRESULT(inst[31:26], rom_out[9:0]);

// ALU control block
ALUCtrl ALUCTRLRESULT(aluop, inst[5:0], alu_con);

// get register numbers
// Decode instruction to get register number locations here
assign reg_a = inst[25:21];
assign reg_b = inst[20:16];
assign reg_c = inst[15:11];

// get immediate value
// Decode instruction to get the immediate value here
SignExtend SIGNEXTENDRESULT(inst[15:0], imm_value);

// Register file: read and writeback
// Instantiate your register file here
reg32bit REG32BITRESULT(clock, regwrite, reg_a, reg_b, regdst ?
reg_c : reg_b, val_c, val_a, val_b);

// main ALU
// Instantiate your ALU here
MIPSALU MIPSALURESULT(alu_con, val_a, alusrc ? imm_value : val_b,
alu_out, zero);

// branch target adder
// Instantiate the adder for the branch target here
assign branch_target = pc_plus_4 + (imm_value << 2);

// jump target adder
assign jump_target = imm_value << 2;

/*
* Memory read/write
*/

// use alu_out as memory address
// Instantiate your data memory module here
DMem DMEMRESULT(memread, memwrite, alu_out, val_b, mem_out);

assign val_c = memtoreg ? mem_out : alu_out;


endmodule

module cputestbench;
reg clk;

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
wire[31:0] cycle, pc, inst, alu_out, mem_out;
wire jump, regdst, alusrc, branch, memread, memwrite, regwrite,
memtoreg;
wire[1:0] aluop;
wire zero;
cpu cpu1(cycle, pc, inst, alu_out, mem_out, clk, jump, regdst,
aluop, alusrc, branch, memread, memwrite, regwrite, memtoreg,
zero);

initial begin
clk=1'b0;
forever
#10 clk=~clk;
end

initial begin
cpu1.IMEMRESULT.Instrns[0]=32'h20030008;
cpu1.IMEMRESULT.Instrns[1]=32'h20040001;
cpu1.IMEMRESULT.Instrns[2]=32'h2005ffff;
cpu1.IMEMRESULT.Instrns[3]=32'h10600005;
cpu1.IMEMRESULT.Instrns[4]=32'h00852020;
cpu1.IMEMRESULT.Instrns[5]=32'h00852822;
cpu1.IMEMRESULT.Instrns[6]=32'h2063ffff;
cpu1.IMEMRESULT.Instrns[7]=32'h08000003;
cpu1.IMEMRESULT.Instrns[8]=32'ha00400ff;

cpu1.REG32BITRESULT.Regs[0] = 32'd0; // Added by TA

end

always @(posedge clk) begin
$display("PC: %d",pc);
$display("Cycle: %d",cycle);
$display("Instruction: %h",inst);
$display("ALU Result: %d",alu_out);
$display("ALU Inputs A: %d, B: %d",cpu1.val_a,cpu1.val_b);
$display("ALU Source: %d",alusrc);
// Added by TA
$display("$3: %d ; $4: %d ; $5:
%d",cpu1.REG32BITRESULT.Regs[3],cpu1.REG32BITRESULT.Regs[4],
cpu1.REG32BITRESULT.Regs[5]);
$display("Immediate: %d",cpu1.imm_value);
$display("");
end
initial begin
#4000 $stop;
end

endmodule

module DMem (MemRead, MemWrite, Address, WrData, RdData);
input MemRead, MemWrite;
input [31:0] Address, WrData;
output [31:0] RdData;
reg[31:0] Mem[511:0];
reg [31:0] RdData;

always@ (MemRead or MemWrite or Address or WrData)
begin
if(MemRead == 1'b1)
RdData = Mem[Address];
if(MemWrite == 1'b1)
Mem[Address] = WrData;
end

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
endmodule

module ALUCtrl (ALUOp, FuncCode, ALUCtl);

input[1:0] ALUOp;
input[5:0] FuncCode;
output[3:0] ALUCtl;
reg[3:0] ALUCtl;

always @(ALUOp or FuncCode)
begin
case (ALUOp)
2'd0: ALUCtl = 4'd2;
2'd1: ALUCtl = 4'd6;
2'd2: begin
case (FuncCode)
6'd32: ALUCtl = 4'd2; // add
6'd34: ALUCtl = 4'd6; //subtract
6'd36: ALUCtl = 4'd0; // and
6'd37: ALUCtl = 4'd1; // or
6'd39: ALUCtl = 4'd12; // nor
6'd42: ALUCtl = 4'd7; // slt
default: ALUCtl = 4'd15; //dont do it
endcase
end
default: ALUCtl = 4'd15; // should not happen
endcase
end

endmodule

module Imem(InstrAddr, InstrOut);

input [31:0] InstrAddr;
output[31:0] InstrOut;
reg[31:0]Instrns[511:0]; //can be 1023:0 or whatever
assign InstrOut = Instrns[InstrAddr];

endmodule

module MCCtrl (FuncCode, out);

input[5:0] FuncCode;
output[9:0] out;
reg jump, regdst, alusrc, branch, memread, memwrite, regwrite,
memtoreg, aluop1, aluop0;
wire X;

always @(FuncCode)
begin
case (FuncCode)
6'd0: //r-format
begin
jump = 1'b0;
regdst = 1'b1;
alusrc = 1'b0;
memtoreg = 1'b0;
regwrite = 1'b1;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b1;
aluop0 = 1'b0;


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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
end
6'd35: //load word
begin
jump = 1'b0;
regdst = 1'b0;
alusrc = 1'b1;
memtoreg = 1'b1;
regwrite = 1'b1;
memread = 1'b1;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;
end
6'd43: //store word
begin
jump = 1'b0;
regdst = X;
alusrc = 1'b1;
memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;
memwrite = 1'b1;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;

end
6'd4: //beq
begin
jump = 1'b0;
regdst = X;
alusrc = 1'b0;
memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b1;
aluop1 = 1'b0;
aluop0 = 1'b1;

end
6'd8: //add immediate
begin
jump = 1'b0;
regdst = 0;
alusrc = 1'b1;
memtoreg = 0;
regwrite = 1'b1;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;

end
6'd2: //jump
begin
jump = 1'b1;
regdst = X;
alusrc = 1'b0;
memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b1;

end
default:
begin
jump = 1'b0;
regdst = X;
alusrc = X;
memtoreg = X;
regwrite = X;
memread = X;
memwrite = X;
branch = X;
aluop1 = 1'b1;
aluop0 = 1'b0;
end
endcase
end
assign out[9:0] =
{jump,regdst,alusrc,memtoreg,regwrite,memread,memwrite,branch,aluop1,alu
op0};
endmodule

module MIPSALU (ALUctl, A, B, ALUOut, Zero);

input [3:0] ALUctl;
input [31:0] A,B;
output [31:0] ALUOut;
output Zero;
reg [31:0] ALUOut;

assign Zero = (ALUOut == 0); //Zero is true if ALUOut is 0

always @ (ALUctl or A or B)
begin //reevaluate if these change
case (ALUctl)
4'd0: ALUOut = A & B;
4'd1: ALUOut = A | B;
4'd2: ALUOut = A + B;
4'd6: ALUOut = A - B;
4'd7: ALUOut = A < B ? 32'd1 : 32'd0;
4'd12: ALUOut = ~(A | B); // result is nor
default: ALUOut = 4'd0; //nothing
endcase
end
endmodule

module registerfile (Clock, WriteAddr, DataIn, WriteEnable, ReadAddrA, R
eadAddrB, Out1, Out2, OQ1, OQ2, OQ3, OQ4);

input [1:0] WriteAddr, ReadAddrA, ReadAddrB;
input [3:0] DataIn;
input Clock, WriteEnable;

output [3:0] Out1, Out2;
output [3:0] OQ1, OQ2, OQ3, OQ4;
wire [3:0] two2fourdecoderoutput, Q0, Q1, Q2, Q3, DataOutA,
DataOutB;

two2fourdecoder TWO2FOURDECODERRESULT(WriteAddr[0], WriteAddr[1],
two2fourdecoderoutput);

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PIPO PIPORESULTA(Clock, WriteEnable & two2fourdecoderoutput[0],
DataIn, Q0);
PIPO PIPORESULTB(Clock, WriteEnable & two2fourdecoderoutput[1],
DataIn, Q1);
PIPO PIPORESULTC(Clock, WriteEnable & two2fourdecoderoutput[2],
DataIn, Q2);
PIPO PIPORESULTD(Clock, WriteEnable & two2fourdecoderoutput[3],
DataIn, Q3);

mux41 MUX41RESULTA(Q0[0], Q1[0], Q2[0], Q3[0], ReadAddrA,
DataOutA[0]);
mux41 MUX41RESULTB(Q0[1], Q1[1], Q2[1], Q3[1], ReadAddrA,
DataOutA[1]);
mux41 MUX41RESULTC(Q0[2], Q1[2], Q2[2], Q3[2], ReadAddrA,
DataOutA[2]);
mux41 MUX41RESULTD(Q0[3], Q1[3], Q2[3], Q3[3], ReadAddrA,
DataOutA[3]);

mux41 MUX41RESULTE(Q0[0], Q1[0], Q2[0], Q3[0], ReadAddrB,
DataOutB[0]);
mux41 MUX41RESULTF(Q0[1], Q1[1], Q2[1], Q3[1], ReadAddrB,
DataOutB[1]);
mux41 MUX41RESULTG(Q0[2], Q1[2], Q2[2], Q3[2], ReadAddrB,
DataOutB[2]);
mux41 MUX41RESULTH(Q0[3], Q1[3], Q2[3], Q3[3], ReadAddrB,
DataOutB[3]);

assign Out1 = DataOutA; //four bit data output
assign Out2 = DataOutB; //four bit data output
assign OQ1 = Q0;
assign OQ2 = Q1;
assign OQ3 = Q2;
assign OQ4 = Q3;

endmodule

module two2fourdecoder (A, B, O);

input A, B;
output [3:0] O;

assign O[0] = ~A & ~B;
assign O[1] = A & ~B;
assign O[2] = ~A & B;
assign O[3] = A & B;

endmodule

module PIPO(Clk, En, D, Q);

input En, Clk;
input [3:0] D;
output [3:0] Q;

DFF D1(Clk & En, D[0], Q[0], );
DFF D2(Clk & En, D[1], Q[1], );
DFF D3(Clk & En, D[2], Q[2], );
DFF D4(Clk & En, D[3], Q[3], );

endmodule

module mux21 (A, X0, X1, X);


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input A, X0, X1;
output X;
assign X = ((A & X1) | (~A & X0));

endmodule

module mux41 (D0, D1, D2, D3, S, Q);

input D0, D1, D2, D3;
input [1:0] S;
output Q;
wire [1:0] w;

mux21 RESULTA(S[0], D0, D1, w[0]);
mux21 RESULTB(S[0], D2, D3, w[1]);
mux21 RESULTC(S[1], w[0], w[1], Q);

endmodule

module SignExtend(Inp,Outp); //uses temporary op

input[15:0] Inp;
output[31:0] Outp;

assign Outp = (Inp[15] == 1'b1) ?
({16'hFFFF,Inp}):({16'h0000,Inp});

endmodule

module reg32bit(Clock, WriteEnable, ReadAddrA, ReadAddrB, WriteAddr,
DataIn, DataOutA, DataOutB);

input Clock, WriteEnable;
input [4:0] ReadAddrA, ReadAddrB, WriteAddr;
input [31:0] DataIn;
output [31:0] DataOutA, DataOutB;
reg [31:0] Regs[31:0];

always@(posedge Clock) begin
if(WriteEnable == 1'b1)
Regs[WriteAddr] <= DataIn;
end

assign DataOutA = Regs[ReadAddrA];
assign DataOutB = Regs[ReadAddrB];

endmodule

Simulation Output:

# PC: 0
# Cycle: 0
# Instruction: 20030008
# ALU Result: 8
# ALU Inputs A: 0, B: x
# ALU Source: 1
# $3: x ; $4: x ; $5: x
# Immediate: 8
#
# PC: 4
# Cycle: 1
# Instruction: 20040001
# ALU Result: 1
# ALU Inputs A: 0, B: x

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# ALU Source: 1
# $3: 8 ; $4: x ; $5: x
# Immediate: 1
#
# PC: 8
# Cycle: 2
# Instruction: 2005ffff
# ALU Result: 4294967295
# ALU Inputs A: 0, B: x
# ALU Source: 1
# $3: 8 ; $4: 1 ; $5: x
# Immediate: 4294967295
#
# PC: 12
# Cycle: 3
# Instruction: 10600005
# ALU Result: 8
# ALU Inputs A: 8, B: 0
# ALU Source: 0
# $3: 8 ; $4: 1 ; $5: 4294967295
# Immediate: 5
#
# PC: 16
# Cycle: 4
# Instruction: 00852020
# ALU Result: 0
# ALU Inputs A: 1, B: 4294967295
# ALU Source: 0
# $3: 8 ; $4: 1 ; $5: 4294967295
# Immediate: 8224
#
# PC: 20
# Cycle: 5
# Instruction: 00852822
# ALU Result: 1
# ALU Inputs A: 0, B: 4294967295
# ALU Source: 0
# $3: 8 ; $4: 0 ; $5: 4294967295
# Immediate: 10274
#
# PC: 24
# Cycle: 6
# Instruction: 2063ffff
# ALU Result: 7
# ALU Inputs A: 8, B: 8
# ALU Source: 1
# $3: 8 ; $4: 0 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 7
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 7 ; $4: 0 ; $5: 1
# Immediate: 3
#
# PC: 12
# Cycle: 8
# Instruction: 10600005
# ALU Result: 7
# ALU Inputs A: 7, B: 0
# ALU Source: 0

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# $3: 7 ; $4: 0 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 9
# Instruction: 00852020
# ALU Result: 1
# ALU Inputs A: 0, B: 1
# ALU Source: 0
# $3: 7 ; $4: 0 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 10
# Instruction: 00852822
# ALU Result: 0
# ALU Inputs A: 1, B: 1
# ALU Source: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 11
# Instruction: 2063ffff
# ALU Result: 6
# ALU Inputs A: 7, B: 7
# ALU Source: 1
# $3: 7 ; $4: 1 ; $5: 0
# Immediate: 4294967295
#
# PC: 28
# Cycle: 12
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 6 ; $4: 1 ; $5: 0
# Immediate: 3
#
# PC: 12
# Cycle: 13
# Instruction: 10600005
# ALU Result: 6
# ALU Inputs A: 6, B: 0
# ALU Source: 0
# $3: 6 ; $4: 1 ; $5: 0
# Immediate: 5
#
# PC: 16
# Cycle: 14
# Instruction: 00852020
# ALU Result: 1
# ALU Inputs A: 1, B: 0
# ALU Source: 0
# $3: 6 ; $4: 1 ; $5: 0
# Immediate: 8224
#
# PC: 20
# Cycle: 15
# Instruction: 00852822
# ALU Result: 1
# ALU Inputs A: 1, B: 0
# ALU Source: 0
# $3: 6 ; $4: 1 ; $5: 0

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# Immediate: 10274
#
# PC: 24
# Cycle: 16
# Instruction: 2063ffff
# ALU Result: 5
# ALU Inputs A: 6, B: 6
# ALU Source: 1
# $3: 6 ; $4: 1 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 17
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 5 ; $4: 1 ; $5: 1
# Immediate: 3
#
# PC: 12
# Cycle: 18
# Instruction: 10600005
# ALU Result: 5
# ALU Inputs A: 5, B: 0
# ALU Source: 0
# $3: 5 ; $4: 1 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 19
# Instruction: 00852020
# ALU Result: 2
# ALU Inputs A: 1, B: 1
# ALU Source: 0
# $3: 5 ; $4: 1 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 20
# Instruction: 00852822
# ALU Result: 1
# ALU Inputs A: 2, B: 1
# ALU Source: 0
# $3: 5 ; $4: 2 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 21
# Instruction: 2063ffff
# ALU Result: 4
# ALU Inputs A: 5, B: 5
# ALU Source: 1
# $3: 5 ; $4: 2 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 22
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 4 ; $4: 2 ; $5: 1
# Immediate: 3

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#
# PC: 12
# Cycle: 23
# Instruction: 10600005
# ALU Result: 4
# ALU Inputs A: 4, B: 0
# ALU Source: 0
# $3: 4 ; $4: 2 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 24
# Instruction: 00852020
# ALU Result: 3
# ALU Inputs A: 2, B: 1
# ALU Source: 0
# $3: 4 ; $4: 2 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 25
# Instruction: 00852822
# ALU Result: 2
# ALU Inputs A: 3, B: 1
# ALU Source: 0
# $3: 4 ; $4: 3 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 26
# Instruction: 2063ffff
# ALU Result: 3
# ALU Inputs A: 4, B: 4
# ALU Source: 1
# $3: 4 ; $4: 3 ; $5: 2
# Immediate: 4294967295
#
# PC: 28
# Cycle: 27
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 3 ; $4: 3 ; $5: 2
# Immediate: 3
#
# PC: 12
# Cycle: 28
# Instruction: 10600005
# ALU Result: 3
# ALU Inputs A: 3, B: 0
# ALU Source: 0
# $3: 3 ; $4: 3 ; $5: 2
# Immediate: 5
#
# PC: 16
# Cycle: 29
# Instruction: 00852020
# ALU Result: 5
# ALU Inputs A: 3, B: 2
# ALU Source: 0
# $3: 3 ; $4: 3 ; $5: 2
# Immediate: 8224
#

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# PC: 20
# Cycle: 30
# Instruction: 00852822
# ALU Result: 3
# ALU Inputs A: 5, B: 2
# ALU Source: 0
# $3: 3 ; $4: 5 ; $5: 2
# Immediate: 10274
#
# PC: 24
# Cycle: 31
# Instruction: 2063ffff
# ALU Result: 2
# ALU Inputs A: 3, B: 3
# ALU Source: 1
# $3: 3 ; $4: 5 ; $5: 3
# Immediate: 4294967295
#
# PC: 28
# Cycle: 32
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 2 ; $4: 5 ; $5: 3
# Immediate: 3
#
# PC: 12
# Cycle: 33
# Instruction: 10600005
# ALU Result: 2
# ALU Inputs A: 2, B: 0
# ALU Source: 0
# $3: 2 ; $4: 5 ; $5: 3
# Immediate: 5
#
# PC: 16
# Cycle: 34
# Instruction: 00852020
# ALU Result: 8
# ALU Inputs A: 5, B: 3
# ALU Source: 0
# $3: 2 ; $4: 5 ; $5: 3
# Immediate: 8224
#
# PC: 20
# Cycle: 35
# Instruction: 00852822
# ALU Result: 5
# ALU Inputs A: 8, B: 3
# ALU Source: 0
# $3: 2 ; $4: 8 ; $5: 3
# Immediate: 10274
#
# PC: 24
# Cycle: 36
# Instruction: 2063ffff
# ALU Result: 1
# ALU Inputs A: 2, B: 2
# ALU Source: 1
# $3: 2 ; $4: 8 ; $5: 5
# Immediate: 4294967295
#
# PC: 28

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# Cycle: 37
# Instruction: 08000003
# ALU Result: 0
# ALU Inputs A: 0, B: 0
# ALU Source: 0
# $3: 1 ; $4: 8 ; $5: 5
# Immediate: 3
#
# PC: 12
# Cycle: 38
# Instruction: 10600005
# ALU Result: 1
# ALU Inputs A: 1, B: 0
# ALU Source: 0
# $3: 1 ; $4: 8 ; $5: 5
# Immediate: 5
#
# PC: 16
# Cycle: 39
# Instruction: 00852020
# ALU Result: 13
# ALU Inputs A: 8, B: 5
# ALU Source: 0
# $3: 1 ; $4: 8 ; $5: 5
# Immediate: 8224
#
# PC: 20
# Cycle: 40
# Instruction: 00852822
# ALU Result: 8
# ALU Inputs A: 13, B: 5
# ALU Source: 0
# $3: 1 ; $4: 13 ; $5: 5
# Immediate: 10274

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Multi Cycle CPU

Lab Session: 9

Verilog Code:

module cpu(cycle, pc, inst, aluout, mem_data_reg_out, clock, instaddr,
A, B);

// input/output
input clock;
output[31:0] cycle, pc, inst, mem_data_reg_out, aluout, A, B,
instaddr;

// for debug
reg[31:0] cycle = 32'b0;

initial begin
cycle = 0;
end
always @ (posedge clock) begin
cycle = cycle + 1;
end

/*
* "global" variables
*/

// control and ALU-related variables
wire zero, pcwrite, pcwritecond, regdst, alusrca, memread, iord,
irwrite, memwrite, regwrite, memtoreg;
wire [1:0] pcsource, aluop, alusrcb;
wire[3:0] alu_con;

// register address and data
wire[4:0] reg_a, reg_b;
wire[31:0] val_a, val_b;
reg [31:0] aluout, mem_data_reg_out;

// other variables
wire[31:0] branch_target;
wire[31:0] imm_value;
wire[31:0] jump_addr;
wire[31:0] alu_rslt;
wire[31:0] memdata;
reg[31:0] pc, inst, A, B;

/*
* inst fetch
*/

//jump!
assign jump_addr = {pc[31:28], (inst[25:0])<<2};

wire[31:0]instaddr = iord ? aluout : pc;

//Instantiate your data memory module here
DMem DMEMRESULT(memread, memwrite, instaddr, B, memdata);

// Register file: read and writeback
// Instantiate your register file here
reg32bit REG32BITRESULT(clock, regwrite, inst[25:21], inst[20:16],

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regdst ? inst[15:11] : inst[20:16], memtoreg ? mem_data_reg_out :
aluout, val_a, val_b);

// get immediate value
// Decode instruction to get the immediate value here
SignExtend SIGNEXTENDRESULT(inst[15:0], imm_value);

//cases for mux that chooses between B, 4, immediate, immediate
shifted
reg[31:0] alu_b;

always @(alusrcb)
begin
case (alusrcb)
2'd0: alu_b = B;
2'd1: alu_b = 4;
2'd2: alu_b = imm_value;
2'd3: alu_b = (imm_value << 2);
endcase
end

// Instantiate your FSM control unit here
controlFSM control(clock, inst[31:26], pcwritecond, pcwrite, iord,
memread, memwrite, memtoreg, irwrite, pcsource, aluop, alusrcb,
alusrca, regwrite, regdst);

// ALU control block
ALUCtrl ALUCTRLRESULT(aluop, inst[5:0], alu_con);

// Instantiate your ALU here
MIPSALU MIPSALURESULT(alu_con, alusrca ? A : pc, alu_b, alu_rslt,
zero);

//update pc
always @ (posedge clock)
begin
A <= val_a;
B <= val_b;
aluout <= alu_rslt;

if ((pcwritecond & zero) | pcwrite)
case(pcsource)
2'd0: pc <= alu_rslt;
2'd1: pc <= aluout;
2'd2: pc <= jump_addr;
endcase
end

always @ (negedge clock)
begin
if(irwrite)
inst <= memdata;
mem_data_reg_out <= memdata;
end

endmodule

module cputestbench;
reg clk;
wire[31:0] cycle, pc, inst, aluout, mem_data_reg_out, A, B,
instaddr;
wire regdst, alusrca, alusrcb, branch, memread, memwrite,
regwrite, memtoreg, zero;
wire[1:0] aluop;

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cpu cpu1(cycle, pc, inst, aluout, mem_data_reg_out, clk, instaddr,
A, B);

initial begin
clk=1'b0;
cpu1.control.State = 4'b0000;
forever
#10 clk=~clk;
end

initial begin
cpu1.pc = 32'd0;
cpu1.DMEMRESULT.Mem[0]=32'h2003000A;
cpu1.DMEMRESULT.Mem[4]=32'h20040001;
cpu1.DMEMRESULT.Mem[8]=32'h2005ffff;
cpu1.DMEMRESULT.Mem[12]=32'h10600005;
cpu1.DMEMRESULT.Mem[16]=32'h00852020;
cpu1.DMEMRESULT.Mem[20]=32'h00852822;
cpu1.DMEMRESULT.Mem[24]=32'h2063ffff;
cpu1.DMEMRESULT.Mem[28]=32'h08000003;
cpu1.DMEMRESULT.Mem[32]=32'ha00400ff;

cpu1.REG32BITRESULT.Regs[0] = 32'd0; // Added by TA

end

always @(posedge clk) begin
$display("PC: %d",pc);
$display("Cycle: %d",cycle);
$display("Instruction: %h",inst);
$display("Address: %h",instaddr);
$display("ALU Result: %d",aluout);
$display("Registers A: %d, B: %d",A,B);
$display("$3: %d ; $4: %d ; $5:%d",
cpu1.REG32BITRESULT.Regs[3], cpu1.REG32BITRESULT.Regs[4],
cpu1.REG32BITRESULT.Regs[5]);
$display("Immediate: %d", cpu1.imm_value);
$display("");
end
initial begin
#4000 $stop;
end

endmodule

module controlFSM(Clock, Op, PCWriteCond, PCWrite, IorD, MemRead,
MemWrite,
MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite,
RegDst);

input Clock;
input [5:0] Op;

output PCWriteCond, PCWrite, IorD, MemRead, MemWrite;
output MemtoReg, IRWrite;
output ALUSrcA, RegWrite, RegDst;
output [1:0] ALUSrcB, ALUOp, PCSource;

reg PCWriteCond, PCWrite, IorD, MemRead, MemWrite;
reg MemtoReg, IRWrite;
reg ALUSrcA, RegWrite, RegDst;
reg [1:0] ALUSrcB, ALUOp, PCSource;

parameter Inst_Fetch = 4'b0000;

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parameter Inst_Decode = 4'b0001;
parameter Mem_Address = 4'b0010;
parameter Mem_AccessL = 4'b0011;
parameter Mem_Read = 4'b0100;
parameter Mem_AccessS = 4'b0101;
parameter Execution = 4'b0110;
parameter R_Type = 4'b0111;
parameter Branch = 4'b1000;
parameter Jump = 4'b1001;
parameter Addi = 4'b1010;
parameter Addi_Comp = 4'b1011;

reg[3:0] State;
reg[3:0] Next_State;

initial
begin
State <= Inst_Fetch;
end

always @ (Next_State)
begin

State <= Next_State;
end

always @ (posedge Clock)
begin
case({State})
4'b0000: begin //Instruction Fetch
PCWriteCond = 1'b0;
MemRead = 1'b1;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b1;
ALUSrcB = 2'b01;
ALUOp = 2'b00;
PCWrite = 1'b1;
PCSource = 2'b00;
Next_State = Inst_Decode;
end
4'b0001: begin //Instruction Decode/Register Fetch
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b11;
ALUOp = 2'b00;
PCSource = 2'b00;

case (Op)
6'd8: Next_State = Addi; //Add Immediate
6'b000000: Next_State = Execution;//R-
Type

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6'b110001: Next_State = Mem_Address;//LW
6'b101011: Next_State = Mem_Address;//SW
6'b000100: Next_State = Branch;//BEQ
6'b000010: Next_State = Jump;//Jump
endcase

end

4'b0010: begin //Memory address computation
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b1;
IorD = 1'b0;
IRWrite = 1'b1;
ALUSrcB = 2'b10;
ALUOp = 2'b00;
PCSource = 2'b00;

if (Op == 6'b110001) Next_State =
Mem_AccessL;//LW
else if (Op == 6'b101011) Next_State =
Mem_AccessS;//SW
end
4'b0011: begin //Memory Access Load Word
MemRead = 1'b1;
IorD = 1'b1;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Mem_Read;
end
4'b0100: begin //Memory Read completion step
RegDst = 1'b1;
RegWrite = 1'b1;
MemtoReg = 1'b0;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Inst_Fetch;
end
4'b0101: begin //Memory Access Store Word

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MemWrite = 1'b1;
IorD = 1'b1;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Inst_Fetch;
end
4'b0110: begin //Execution
ALUSrcA = 1'b1;
ALUSrcB = 2'b00;
ALUOp = 2'b10;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
PCSource = 2'b00;

Next_State = R_Type;
end
4'b0111: begin //R-Type Completion
RegDst = 1'b1;
RegWrite = 1'b1;
MemtoReg = 1'b0;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Inst_Fetch;
end
4'b1000: begin //Branch Completion
ALUSrcA = 1'b1;
ALUSrcB = 2'b00;
ALUOp = 2'b01;
PCWriteCond = 1'b1;
PCSource = 2'b01;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
PCWrite = 1'b0;

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Next_State = Inst_Fetch;
end
4'b1001: begin //Jump Completion
PCWriteCond = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
MemtoReg = 1'b0;
RegWrite = 1'b0;
RegDst = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCWrite = 1'b1;
PCSource = 2'b10;

Next_State = Inst_Fetch;
end

4'b1010: begin //Add Immediate
RegDst = 1'b0;
RegWrite = 1'b0;
MemtoReg = 1'b0;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
ALUSrcA = 1'b1;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b10;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Addi_Comp;
end

4'b1011: begin //Add Immediate Complete
RegDst = 1'b0;
RegWrite = 1'b1;
MemtoReg = 1'b0;
PCWriteCond = 1'b0;
PCWrite = 1'b0;
MemRead = 1'b0;
MemWrite = 1'b0;
ALUSrcA = 1'b0;
IorD = 1'b0;
IRWrite = 1'b0;
ALUSrcB = 2'b00;
ALUOp = 2'b00;
PCSource = 2'b00;

Next_State = Inst_Fetch;
end
endcase

end

endmodule

module DMem (MemRead, MemWrite, Address, WrData, RdData);
input MemRead, MemWrite;

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input [31:0] Address, WrData;
output [31:0] RdData;
reg[31:0] Mem[511:0];
reg [31:0] RdData;

always@ (MemRead or MemWrite or Address or WrData)
begin
if(MemRead == 1'b1)
RdData = Mem[Address];
if(MemWrite == 1'b1)
Mem[Address] = WrData;
end
endmodule

module ALUCtrl (ALUOp, FuncCode, ALUCtl);

input[1:0] ALUOp;
input[5:0] FuncCode;
output[3:0] ALUCtl;
reg[3:0] ALUCtl;

always @(ALUOp or FuncCode)
begin
case (ALUOp)
2'd0: ALUCtl = 4'd2;
2'd1: ALUCtl = 4'd6;
2'd2: begin
case (FuncCode)
6'd32: ALUCtl = 4'd2; // add
6'd34: ALUCtl = 4'd6; //subtract
6'd36: ALUCtl = 4'd0; // and
6'd37: ALUCtl = 4'd1; // or
6'd39: ALUCtl = 4'd12; // nor
6'd42: ALUCtl = 4'd7; // slt
default: ALUCtl = 4'd15; //dont do it
endcase
end
default: ALUCtl = 4'd15; // should not happen
endcase
end

endmodule

module MCCtrl (FuncCode, out);

input[5:0] FuncCode;
output[9:0] out;
reg jump, regdst, alusrc, branch, memread, memwrite, regwrite,
memtoreg, aluop1, aluop0;
wire X;

always @(FuncCode)
begin
case (FuncCode)
6'd0: //r-format
begin
jump = 1'b0;
regdst = 1'b1;
alusrc = 1'b0;
memtoreg = 1'b0;
regwrite = 1'b1;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b0;

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aluop1 = 1'b1;
aluop0 = 1'b0;

end
6'd35: //load word
begin
jump = 1'b0;
regdst = 1'b0;
alusrc = 1'b1;
memtoreg = 1'b1;
regwrite = 1'b1;
memread = 1'b1;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;
end
6'd43: //store word
begin
jump = 1'b0;
regdst = X;
alusrc = 1'b1;
memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;
memwrite = 1'b1;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;

end
6'd4: //beq
begin
jump = 1'b0;
regdst = X;
alusrc = 1'b0;
memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b1;
aluop1 = 1'b0;
aluop0 = 1'b1;

end
6'd8: //add immediate
begin
jump = 1'b0;
regdst = 0;
alusrc = 1'b1;
memtoreg = 0;
regwrite = 1'b1;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b0;

end
6'd2: //jump
begin
jump = 1'b1;
regdst = X;
alusrc = 1'b0;

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memtoreg = X;
regwrite = 1'b0;
memread = 1'b0;
memwrite = 1'b0;
branch = 1'b0;
aluop1 = 1'b0;
aluop0 = 1'b1;

end
default:
begin
jump = 1'b0;
regdst = X;
alusrc = X;
memtoreg = X;
regwrite = X;
memread = X;
memwrite = X;
branch = X;
aluop1 = 1'b1;
aluop0 = 1'b0;
end
endcase
end
assign out[9:0] =
{jump,regdst,alusrc,memtoreg,regwrite,memread,memwrite,branch,aluop1,alu
op0};
endmodule

module MIPSALU (ALUctl, A, B, ALUOut, Zero);

input [3:0] ALUctl;
input [31:0] A,B;
output [31:0] ALUOut;
output Zero;
reg [31:0] ALUOut;

assign Zero = (ALUOut == 0); //Zero is true if ALUOut is 0

always @ (ALUctl or A or B)
begin //reevaluate if these change
case (ALUctl)
4'd0: ALUOut = A & B;
4'd1: ALUOut = A | B;
4'd2: ALUOut = A + B;
4'd6: ALUOut = A - B;
4'd7: ALUOut = A < B ? 32'd1 : 32'd0;
4'd12: ALUOut = ~(A | B); // result is nor
default: ALUOut = 4'd0; //nothing
endcase
end
endmodule

module registerfile (Clock, WriteAddr, DataIn, WriteEnable, ReadAddrA, R
eadAddrB, Out1, Out2, OQ1, OQ2, OQ3, OQ4);

input [1:0] WriteAddr, ReadAddrA, ReadAddrB;
input [3:0] DataIn;
input Clock, WriteEnable;

output [3:0] Out1, Out2;
output [3:0] OQ1, OQ2, OQ3, OQ4;
wire [3:0] two2fourdecoderoutput, Q0, Q1, Q2, Q3, DataOutA,
DataOutB;

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two2fourdecoder TWO2FOURDECODERRESULT(WriteAddr[0], WriteAddr[1],
two2fourdecoderoutput);

PIPO PIPORESULTA(Clock, WriteEnable & two2fourdecoderoutput[0],
DataIn, Q0);
PIPO PIPORESULTB(Clock, WriteEnable & two2fourdecoderoutput[1],
DataIn, Q1);
PIPO PIPORESULTC(Clock, WriteEnable & two2fourdecoderoutput[2],
DataIn, Q2);
PIPO PIPORESULTD(Clock, WriteEnable & two2fourdecoderoutput[3],
DataIn, Q3);

mux41 MUX41RESULTA(Q0[0], Q1[0], Q2[0], Q3[0], ReadAddrA,
DataOutA[0]);
mux41 MUX41RESULTB(Q0[1], Q1[1], Q2[1], Q3[1], ReadAddrA,
DataOutA[1]);
mux41 MUX41RESULTC(Q0[2], Q1[2], Q2[2], Q3[2], ReadAddrA,
DataOutA[2]);
mux41 MUX41RESULTD(Q0[3], Q1[3], Q2[3], Q3[3], ReadAddrA,
DataOutA[3]);

mux41 MUX41RESULTE(Q0[0], Q1[0], Q2[0], Q3[0], ReadAddrB,
DataOutB[0]);
mux41 MUX41RESULTF(Q0[1], Q1[1], Q2[1], Q3[1], ReadAddrB,
DataOutB[1]);
mux41 MUX41RESULTG(Q0[2], Q1[2], Q2[2], Q3[2], ReadAddrB,
DataOutB[2]);
mux41 MUX41RESULTH(Q0[3], Q1[3], Q2[3], Q3[3], ReadAddrB,
DataOutB[3]);

assign Out1 = DataOutA; //four bit data output
assign Out2 = DataOutB; //four bit data output
assign OQ1 = Q0;
assign OQ2 = Q1;
assign OQ3 = Q2;
assign OQ4 = Q3;

endmodule

module two2fourdecoder (A, B, O);

input A, B;
output [3:0] O;

assign O[0] = ~A & ~B;
assign O[1] = A & ~B;
assign O[2] = ~A & B;
assign O[3] = A & B;

endmodule

module PIPO(Clk, En, D, Q);

input En, Clk;
input [3:0] D;
output [3:0] Q;

DFF D1(Clk & En, D[0], Q[0], );
DFF D2(Clk & En, D[1], Q[1], );
DFF D3(Clk & En, D[2], Q[2], );
DFF D4(Clk & En, D[3], Q[3], );

endmodule

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module mux21 (A, X0, X1, X);

input A, X0, X1;
output X;
assign X = ((A & X1) | (~A & X0));

endmodule

module mux41 (D0, D1, D2, D3, S, Q);

input D0, D1, D2, D3;
input [1:0] S;
output Q;
wire [1:0] w;

mux21 RESULTA(S[0], D0, D1, w[0]);
mux21 RESULTB(S[0], D2, D3, w[1]);
mux21 RESULTC(S[1], w[0], w[1], Q);

endmodule

module SignExtend(Inp,Outp); //uses temporary op

input[15:0] Inp;
output[31:0] Outp;

assign Outp = (Inp[15] == 1'b1) ?
({16'hFFFF,Inp}):({16'h0000,Inp});

endmodule

module reg32bit(Clock, WriteEnable, ReadAddrA, ReadAddrB, WriteAddr,
DataIn, DataOutA, DataOutB);

input Clock, WriteEnable;
input [4:0] ReadAddrA, ReadAddrB, WriteAddr;
input [31:0] DataIn;
output [31:0] DataOutA, DataOutB;
reg [31:0] Regs[31:0];

always@(posedge Clock) begin
if(WriteEnable == 1'b1)
Regs[WriteAddr] <= DataIn;
end

assign DataOutA = Regs[ReadAddrA];
assign DataOutB = Regs[ReadAddrB];

endmodule

Simulation Output:

# PC: 0
# Cycle: 0
# Instruction: xxxxxxxx
# Address: xxxxxxxx
# ALU Result: x
# Registers A: x, B: x
# $3: x ; $4: x ; $5: x
# Immediate: x
#
# PC: 0
# Cycle: 1

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Instruction: 2003000a
# Address: 00000000
# ALU Result: x
# Registers A: x, B: x
# $3: x ; $4: x ; $5: x
# Immediate: 10
#
# PC: 4
# Cycle: 2
# Instruction: 2003000a
# Address: 00000004
# ALU Result: 4
# Registers A: 0, B: x
# $3: x ; $4: x ; $5: x
# Immediate: 10
#
# PC: 4
# Cycle: 3
# Instruction: 2003000a
# Address: 00000004
# ALU Result: 44
# Registers A: 0, B: x
# $3: x ; $4: x ; $5: x
# Immediate: 10
#
# PC: 4
# Cycle: 4
# Instruction: 2003000a
# Address: 00000004
# ALU Result: 10
# Registers A: 0, B: x
# $3: x ; $4: x ; $5: x
# Immediate: 10
#
# PC: 4
# Cycle: 5
# Instruction: 20040001
# Address: 00000004
# ALU Result: x
# Registers A: 0, B: x
# $3: 10 ; $4: x ; $5: x
# Immediate: 1
#
# PC: 8
# Cycle: 6
# Instruction: 20040001
# Address: 00000008
# ALU Result: 8
# Registers A: 0, B: x
# $3: 10 ; $4: x ; $5: x
# Immediate: 1
#
# PC: 8
# Cycle: 7
# Instruction: 20040001
# Address: 00000008
# ALU Result: 12
# Registers A: 0, B: x
# $3: 10 ; $4: x ; $5: x
# Immediate: 1
#
# PC: 8
# Cycle: 8
# Instruction: 20040001

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Address: 00000008
# ALU Result: 1
# Registers A: 0, B: x
# $3: 10 ; $4: x ; $5: x
# Immediate: 1
#
# PC: 8
# Cycle: 9
# Instruction: 2005ffff
# Address: 00000008
# ALU Result: x
# Registers A: 0, B: x
# $3: 10 ; $4: 1 ; $5: x
# Immediate: 4294967295
#
# PC: 12
# Cycle: 10
# Instruction: 2005ffff
# Address: 0000000c
# ALU Result: 12
# Registers A: 0, B: x
# $3: 10 ; $4: 1 ; $5: x
# Immediate: 4294967295
#
# PC: 12
# Cycle: 11
# Instruction: 2005ffff
# Address: 0000000c
# ALU Result: 8
# Registers A: 0, B: x
# $3: 10 ; $4: 1 ; $5: x
# Immediate: 4294967295
#
# PC: 12
# Cycle: 12
# Instruction: 2005ffff
# Address: 0000000c
# ALU Result: 4294967295
# Registers A: 0, B: x
# $3: 10 ; $4: 1 ; $5: x
# Immediate: 4294967295
#
# PC: 12
# Cycle: 13
# Instruction: 10600005
# Address: 0000000c
# ALU Result: x
# Registers A: 0, B: x
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 5
#
# PC: 16
# Cycle: 14
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 10, B: 0
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 5
#
# PC: 16
# Cycle: 15
# Instruction: 10600005
# Address: 00000010

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# ALU Result: 36
# Registers A: 10, B: 0
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 5
#
# PC: 16
# Cycle: 16
# Instruction: 00852020
# Address: 00000010
# ALU Result: 10
# Registers A: 10, B: 0
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 8224
#
# PC: 20
# Cycle: 17
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 1, B: 4294967295
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 8224
#
# PC: 20
# Cycle: 18
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 1, B: 4294967295
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 8224
#
# PC: 20
# Cycle: 19
# Instruction: 00852020
# Address: 00000014
# ALU Result: 0
# Registers A: 1, B: 4294967295
# $3: 10 ; $4: 1 ; $5:4294967295
# Immediate: 8224
#
# PC: 20
# Cycle: 20
# Instruction: 00852822
# Address: 00000014
# ALU Result: 19
# Registers A: 1, B: 4294967295
# $3: 10 ; $4: 0 ; $5:4294967295
# Immediate: 10274
#
# PC: 24
# Cycle: 21
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 0, B: 4294967295
# $3: 10 ; $4: 0 ; $5:4294967295
# Immediate: 10274
#
# PC: 24
# Cycle: 22
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Registers A: 0, B: 4294967295
# $3: 10 ; $4: 0 ; $5:4294967295
# Immediate: 10274
#
# PC: 24
# Cycle: 23
# Instruction: 00852822
# Address: 00000018
# ALU Result: 1
# Registers A: 0, B: 4294967295
# $3: 10 ; $4: 0 ; $5:4294967295
# Immediate: 10274
#
# PC: 24
# Cycle: 24
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 23
# Registers A: 0, B: 4294967295
# $3: 10 ; $4: 0 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 25
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 10, B: 10
# $3: 10 ; $4: 0 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 26
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 10, B: 10
# $3: 10 ; $4: 0 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 27
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 9
# Registers A: 10, B: 10
# $3: 10 ; $4: 0 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 28
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 38
# Registers A: 10, B: 10
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 29
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0

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# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 30
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 3
#
# PC: 12
# Cycle: 31
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 32
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 9, B: 0
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 33
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 9, B: 0
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 34
# Instruction: 00852020
# Address: 00000010
# ALU Result: 9
# Registers A: 9, B: 0
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 35
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 0, B: 1
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 36
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 0, B: 1
# $3: 9 ; $4: 0 ; $5: 1

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# Immediate: 8224
#
# PC: 20
# Cycle: 37
# Instruction: 00852020
# Address: 00000014
# ALU Result: 1
# Registers A: 0, B: 1
# $3: 9 ; $4: 0 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 38
# Instruction: 00852822
# Address: 00000014
# ALU Result: 21
# Registers A: 0, B: 1
# $3: 9 ; $4: 1 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 39
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 1, B: 1
# $3: 9 ; $4: 1 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 40
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 1, B: 1
# $3: 9 ; $4: 1 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 41
# Instruction: 00852822
# Address: 00000018
# ALU Result: 0
# Registers A: 1, B: 1
# $3: 9 ; $4: 1 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 42
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 25
# Registers A: 1, B: 1
# $3: 9 ; $4: 1 ; $5: 0
# Immediate: 4294967295
#
# PC: 28
# Cycle: 43
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 9, B: 9
# $3: 9 ; $4: 1 ; $5: 0
# Immediate: 4294967295

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#
# PC: 28
# Cycle: 44
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 9, B: 9
# $3: 9 ; $4: 1 ; $5: 0
# Immediate: 4294967295
#
# PC: 28
# Cycle: 45
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 8
# Registers A: 9, B: 9
# $3: 9 ; $4: 1 ; $5: 0
# Immediate: 4294967295
#
# PC: 28
# Cycle: 46
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 37
# Registers A: 9, B: 9
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 3
#
# PC: 32
# Cycle: 47
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 3
#
# PC: 32
# Cycle: 48
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 3
#
# PC: 12
# Cycle: 49
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 5
#
# PC: 16
# Cycle: 50
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 8, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 5
#

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# PC: 16
# Cycle: 51
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 8, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 5
#
# PC: 16
# Cycle: 52
# Instruction: 00852020
# Address: 00000010
# ALU Result: 8
# Registers A: 8, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 8224
#
# PC: 20
# Cycle: 53
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 8224
#
# PC: 20
# Cycle: 54
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 8224
#
# PC: 20
# Cycle: 55
# Instruction: 00852020
# Address: 00000014
# ALU Result: 1
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 8224
#
# PC: 20
# Cycle: 56
# Instruction: 00852822
# Address: 00000014
# ALU Result: 20
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 10274
#
# PC: 24
# Cycle: 57
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 10274
#
# PC: 24

Page 52 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Cycle: 58
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 10274
#
# PC: 24
# Cycle: 59
# Instruction: 00852822
# Address: 00000018
# ALU Result: 1
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 0
# Immediate: 10274
#
# PC: 24
# Cycle: 60
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 24
# Registers A: 1, B: 0
# $3: 8 ; $4: 1 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 61
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 8, B: 8
# $3: 8 ; $4: 1 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 62
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 8, B: 8
# $3: 8 ; $4: 1 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 63
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 7
# Registers A: 8, B: 8
# $3: 8 ; $4: 1 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 64
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 36
# Registers A: 8, B: 8
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 65

Page 53 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 66
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 3
#
# PC: 12
# Cycle: 67
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 68
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 7, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 69
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 7, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 70
# Instruction: 00852020
# Address: 00000010
# ALU Result: 7
# Registers A: 7, B: 0
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 71
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 1, B: 1
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 72
# Instruction: 00852020

Page 54 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Address: 00000014
# ALU Result: 32916
# Registers A: 1, B: 1
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 73
# Instruction: 00852020
# Address: 00000014
# ALU Result: 2
# Registers A: 1, B: 1
# $3: 7 ; $4: 1 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 74
# Instruction: 00852822
# Address: 00000014
# ALU Result: 21
# Registers A: 1, B: 1
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 75
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 2, B: 1
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 76
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 2, B: 1
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 77
# Instruction: 00852822
# Address: 00000018
# ALU Result: 1
# Registers A: 2, B: 1
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 78
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 25
# Registers A: 2, B: 1
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 79
# Instruction: 2063ffff
# Address: 0000001c

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# ALU Result: 28
# Registers A: 7, B: 7
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 80
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 7, B: 7
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 81
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 6
# Registers A: 7, B: 7
# $3: 7 ; $4: 2 ; $5: 1
# Immediate: 4294967295
#
# PC: 28
# Cycle: 82
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 35
# Registers A: 7, B: 7
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 83
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 3
#
# PC: 32
# Cycle: 84
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 3
#
# PC: 12
# Cycle: 85
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 86
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16

Page 56 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Registers A: 6, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 87
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 6, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 5
#
# PC: 16
# Cycle: 88
# Instruction: 00852020
# Address: 00000010
# ALU Result: 6
# Registers A: 6, B: 0
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 89
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 2, B: 1
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 90
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 2, B: 1
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 91
# Instruction: 00852020
# Address: 00000014
# ALU Result: 3
# Registers A: 2, B: 1
# $3: 6 ; $4: 2 ; $5: 1
# Immediate: 8224
#
# PC: 20
# Cycle: 92
# Instruction: 00852822
# Address: 00000014
# ALU Result: 21
# Registers A: 2, B: 1
# $3: 6 ; $4: 3 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 93
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 3, B: 1

Page 57 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# $3: 6 ; $4: 3 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 94
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 3, B: 1
# $3: 6 ; $4: 3 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 95
# Instruction: 00852822
# Address: 00000018
# ALU Result: 2
# Registers A: 3, B: 1
# $3: 6 ; $4: 3 ; $5: 1
# Immediate: 10274
#
# PC: 24
# Cycle: 96
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 25
# Registers A: 3, B: 1
# $3: 6 ; $4: 3 ; $5: 2
# Immediate: 4294967295
#
# PC: 28
# Cycle: 97
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 6, B: 6
# $3: 6 ; $4: 3 ; $5: 2
# Immediate: 4294967295
#
# PC: 28
# Cycle: 98
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 6, B: 6
# $3: 6 ; $4: 3 ; $5: 2
# Immediate: 4294967295
#
# PC: 28
# Cycle: 99
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 5
# Registers A: 6, B: 6
# $3: 6 ; $4: 3 ; $5: 2
# Immediate: 4294967295
#
# PC: 28
# Cycle: 100
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 34
# Registers A: 6, B: 6
# $3: 5 ; $4: 3 ; $5: 2

Page 58 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Immediate: 3
#
# PC: 32
# Cycle: 101
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 3
#
# PC: 32
# Cycle: 102
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 3
#
# PC: 12
# Cycle: 103
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 5
#
# PC: 16
# Cycle: 104
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 5, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 5
#
# PC: 16
# Cycle: 105
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 5, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 5
#
# PC: 16
# Cycle: 106
# Instruction: 00852020
# Address: 00000010
# ALU Result: 5
# Registers A: 5, B: 0
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 8224
#
# PC: 20
# Cycle: 107
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 3, B: 2
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 8224

Page 59 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
#
# PC: 20
# Cycle: 108
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 3, B: 2
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 8224
#
# PC: 20
# Cycle: 109
# Instruction: 00852020
# Address: 00000014
# ALU Result: 5
# Registers A: 3, B: 2
# $3: 5 ; $4: 3 ; $5: 2
# Immediate: 8224
#
# PC: 20
# Cycle: 110
# Instruction: 00852822
# Address: 00000014
# ALU Result: 22
# Registers A: 3, B: 2
# $3: 5 ; $4: 5 ; $5: 2
# Immediate: 10274
#
# PC: 24
# Cycle: 111
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 5, B: 2
# $3: 5 ; $4: 5 ; $5: 2
# Immediate: 10274
#
# PC: 24
# Cycle: 112
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 5, B: 2
# $3: 5 ; $4: 5 ; $5: 2
# Immediate: 10274
#
# PC: 24
# Cycle: 113
# Instruction: 00852822
# Address: 00000018
# ALU Result: 3
# Registers A: 5, B: 2
# $3: 5 ; $4: 5 ; $5: 2
# Immediate: 10274
#
# PC: 24
# Cycle: 114
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 26
# Registers A: 5, B: 2
# $3: 5 ; $4: 5 ; $5: 3
# Immediate: 4294967295
#

Page 60 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# PC: 28
# Cycle: 115
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 5, B: 5
# $3: 5 ; $4: 5 ; $5: 3
# Immediate: 4294967295
#
# PC: 28
# Cycle: 116
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 5, B: 5
# $3: 5 ; $4: 5 ; $5: 3
# Immediate: 4294967295
#
# PC: 28
# Cycle: 117
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 4
# Registers A: 5, B: 5
# $3: 5 ; $4: 5 ; $5: 3
# Immediate: 4294967295
#
# PC: 28
# Cycle: 118
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 33
# Registers A: 5, B: 5
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 3
#
# PC: 32
# Cycle: 119
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 3
#
# PC: 32
# Cycle: 120
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 3
#
# PC: 12
# Cycle: 121
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 5
#
# PC: 16

Page 61 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Cycle: 122
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 4, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 5
#
# PC: 16
# Cycle: 123
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 4, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 5
#
# PC: 16
# Cycle: 124
# Instruction: 00852020
# Address: 00000010
# ALU Result: 4
# Registers A: 4, B: 0
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 8224
#
# PC: 20
# Cycle: 125
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 5, B: 3
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 8224
#
# PC: 20
# Cycle: 126
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 5, B: 3
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 8224
#
# PC: 20
# Cycle: 127
# Instruction: 00852020
# Address: 00000014
# ALU Result: 8
# Registers A: 5, B: 3
# $3: 4 ; $4: 5 ; $5: 3
# Immediate: 8224
#
# PC: 20
# Cycle: 128
# Instruction: 00852822
# Address: 00000014
# ALU Result: 23
# Registers A: 5, B: 3
# $3: 4 ; $4: 8 ; $5: 3
# Immediate: 10274
#
# PC: 24
# Cycle: 129

Page 62 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 8, B: 3
# $3: 4 ; $4: 8 ; $5: 3
# Immediate: 10274
#
# PC: 24
# Cycle: 130
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 8, B: 3
# $3: 4 ; $4: 8 ; $5: 3
# Immediate: 10274
#
# PC: 24
# Cycle: 131
# Instruction: 00852822
# Address: 00000018
# ALU Result: 5
# Registers A: 8, B: 3
# $3: 4 ; $4: 8 ; $5: 3
# Immediate: 10274
#
# PC: 24
# Cycle: 132
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 27
# Registers A: 8, B: 3
# $3: 4 ; $4: 8 ; $5: 5
# Immediate: 4294967295
#
# PC: 28
# Cycle: 133
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 4, B: 4
# $3: 4 ; $4: 8 ; $5: 5
# Immediate: 4294967295
#
# PC: 28
# Cycle: 134
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 4, B: 4
# $3: 4 ; $4: 8 ; $5: 5
# Immediate: 4294967295
#
# PC: 28
# Cycle: 135
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 3
# Registers A: 4, B: 4
# $3: 4 ; $4: 8 ; $5: 5
# Immediate: 4294967295
#
# PC: 28
# Cycle: 136
# Instruction: 08000003

Page 63 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Address: 0000001c
# ALU Result: 32
# Registers A: 4, B: 4
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 3
#
# PC: 32
# Cycle: 137
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 3
#
# PC: 32
# Cycle: 138
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 3
#
# PC: 12
# Cycle: 139
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 5
#
# PC: 16
# Cycle: 140
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 3, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 5
#
# PC: 16
# Cycle: 141
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 3, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 5
#
# PC: 16
# Cycle: 142
# Instruction: 00852020
# Address: 00000010
# ALU Result: 3
# Registers A: 3, B: 0
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 8224
#
# PC: 20
# Cycle: 143
# Instruction: 00852020
# Address: 00000014

Page 64 of 67
Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# ALU Result: 20
# Registers A: 8, B: 5
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 8224
#
# PC: 20
# Cycle: 144
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 8, B: 5
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 8224
#
# PC: 20
# Cycle: 145
# Instruction: 00852020
# Address: 00000014
# ALU Result: 13
# Registers A: 8, B: 5
# $3: 3 ; $4: 8 ; $5: 5
# Immediate: 8224
#
# PC: 20
# Cycle: 146
# Instruction: 00852822
# Address: 00000014
# ALU Result: 25
# Registers A: 8, B: 5
# $3: 3 ; $4: 13 ; $5: 5
# Immediate: 10274
#
# PC: 24
# Cycle: 147
# Instruction: 00852822
# Address: 00000018
# ALU Result: 24
# Registers A: 13, B: 5
# $3: 3 ; $4: 13 ; $5: 5
# Immediate: 10274
#
# PC: 24
# Cycle: 148
# Instruction: 00852822
# Address: 00000018
# ALU Result: 41120
# Registers A: 13, B: 5
# $3: 3 ; $4: 13 ; $5: 5
# Immediate: 10274
#
# PC: 24
# Cycle: 149
# Instruction: 00852822
# Address: 00000018
# ALU Result: 8
# Registers A: 13, B: 5
# $3: 3 ; $4: 13 ; $5: 5
# Immediate: 10274
#
# PC: 24
# Cycle: 150
# Instruction: 2063ffff
# Address: 00000018
# ALU Result: 29

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# Registers A: 13, B: 5
# $3: 3 ; $4: 13 ; $5: 8
# Immediate: 4294967295
#
# PC: 28
# Cycle: 151
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 28
# Registers A: 3, B: 3
# $3: 3 ; $4: 13 ; $5: 8
# Immediate: 4294967295
#
# PC: 28
# Cycle: 152
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 24
# Registers A: 3, B: 3
# $3: 3 ; $4: 13 ; $5: 8
# Immediate: 4294967295
#
# PC: 28
# Cycle: 153
# Instruction: 2063ffff
# Address: 0000001c
# ALU Result: 2
# Registers A: 3, B: 3
# $3: 3 ; $4: 13 ; $5: 8
# Immediate: 4294967295
#
# PC: 28
# Cycle: 154
# Instruction: 08000003
# Address: 0000001c
# ALU Result: 31
# Registers A: 3, B: 3
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 3
#
# PC: 32
# Cycle: 155
# Instruction: 08000003
# Address: 00000020
# ALU Result: 32
# Registers A: 0, B: 0
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 3
#
# PC: 32
# Cycle: 156
# Instruction: 08000003
# Address: 00000020
# ALU Result: 44
# Registers A: 0, B: 0
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 3
#
# PC: 12
# Cycle: 157
# Instruction: 10600005
# Address: 0000000c
# ALU Result: 32
# Registers A: 0, B: 0

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Cpr E 305 Lab Verilog Synthesis Handbook Vignesh Vijayakumar
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 5
#
# PC: 16
# Cycle: 158
# Instruction: 10600005
# Address: 00000010
# ALU Result: 16
# Registers A: 2, B: 0
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 5
#
# PC: 16
# Cycle: 159
# Instruction: 10600005
# Address: 00000010
# ALU Result: 36
# Registers A: 2, B: 0
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 5
#
# PC: 16
# Cycle: 160
# Instruction: 00852020
# Address: 00000010
# ALU Result: 2
# Registers A: 2, B: 0
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 8224
#
# PC: 20
# Cycle: 161
# Instruction: 00852020
# Address: 00000014
# ALU Result: 20
# Registers A: 13, B: 8
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 8224
#
# PC: 20
# Cycle: 162
# Instruction: 00852020
# Address: 00000014
# ALU Result: 32916
# Registers A: 13, B: 8
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 8224
#
# PC: 20
# Cycle: 163
# Instruction: 00852020
# Address: 00000014
# ALU Result: 21
# Registers A: 13, B: 8
# $3: 2 ; $4: 13 ; $5: 8
# Immediate: 8224


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