Copyright (c) 2011 Hiroshige Goto All rights reserved.

2 Instructions
ARM Cortex-A7 Core Block Diagram
L1 Instruction Cache
(2-way set associative)
With Pre-Decoder
Instruction Fetch
Instruction Decode
S
h
i
f
t
L1 Data
Cache
1

S
t
a
g
e
3

S
t
a
g
e
s
Branch Prediction
Global History Buffer
8-entry Branch-Target
Address Cache (BTAC)
8-entry Return Stack
64 bits
1st Decoder 2nd Decoder
Issue
1

S
t
a
g
e
A
L
U
I
n
t
e
g
e
r
M
u
l
t
i
p
l
y
F
l
o
a
t
i
n
g

P
o
i
n
t
/
N
E
O
N
(
6
4
-
b
i
t
)
D
u
a
l

I
s
s
u
e
L
o
a
d
/
S
t
o
r
e
(
6
4
-
b
i
t

p
a
t
h
)
BHT conditional
prediction
Loop end prediction
Instruction Queue
Instruction Queue
Instruction Queue
WriteBack
2
-
4

S
t
a
g
e
s
I
n
t
e
r
r
u
p
t
C
o
n
t
r
o
l
l
e
r
S
n
o
o
p

C
o
n
t
r
o
l

U
n
i
t
T
i
m
e
r
s
L
2

C
a
c
h
e
C
o
n
t
r
o
l
l
e
r
B
u
s

I
n
t
e
r
f
a
c
e
A
M
B
A
4
1
2
8
-
b
i
t