HSC configuration in S7 200

-Swapnil
High speed Counter
CPU 221 and CPU 222 support 4 High-Speed Counters
(HSC0, HSC3, HSC4, and C5)
CPU 221 and CPU 222 do not support HSC1 and HSC2.
CPU 224, CPU224XP, and CPU 226 support 6 High-Speed Counters
(HSC0 to HSC5)

The High-Speed Counter Definition (HDEF) instruction selects the
operating mode of a specific high-speed counter (HSCx).

High Speed Counter MODES
SMB47 Configure and control HSC1
HSC1_Reset_Level: SM47.0 HSC1 active level control for counter reset:
0=active high; 1=active low
HSC1_Start_Level : SM47.1 HSC1 active level control for counter start:
0=active high; 1=active low
HSC1_Rate : SM47.2 HSC1 counting rate selector:
0=4x (quadrature rate); 1=1x
HSC1_Dir : SM47.3 HSC1 counting direction control:
0=count down; 1=count up
HSC1_Dir_Update: SM47.4 HSC1 update the counting direction:
0=no update; 1=update direction


HSC1 Registers ( high-speed counter 1 )

HSC1_PV_Update :SM47.5 HSC1 update preset value:
0=no update; 1=update preset
HSC1_CV_Update :SM47.6 HSC1 update current value:
0=no update; 1=update current value
HSC1_Enable :SM47.7 HSC1 enable:
0=disable; 1=enable
HSC1_CV :SMD48 HSC1 new current value
HSC1_PV :SMD52 HSC1 new preset value
Always_On SM0.0 Always ON
First_Scan_On SM0.1 ON for the first scan cycle only
1. Open main
subroutine
2. Cal Subroutine
SBR_0
HDEF: HSC Counter no. 1
Mode: 9
SMD 52: Preset Value
Attach: Interrupt 0 event 13
SMD48: Current Value
SMD47: move C0 to SMD47
Actual counter value of Encoder in VD40 is as follows
Thank you