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HPID
R/W FIFOs
HPIA
Increment
HPIC
Access
type
HD[31:0]/HD[15:0]
HDS1, HDS2
HR/W
HAS
HCNTL0
HCNTL1
(optional)
HINT
HRDY
HPI
Host
Data
Address
ALE
R/W
IRQ
Ready
HCS
Chip select
DSP
H
P
I

D
M
A

l
o
g
i
c
HHWIL
(if needed)
Data strobes
Switched
central
resource
C64x+
megamodule
External
memory
I/F
Other
peripherals
EDMA3
Internal
memory

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Address or I/O
Read/Write
Chip select
Data strobe
A
Data/address
Interrupt
Ready
HCNTL[1:0]
HR/W
HCS
HDS1
HDS2
HD[31:0]
HINT
HRDY
HPI
Host
Address latch enable HAS
No connect HHWIL
Logic high
2
32
DSP

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Address or I/O
Read/Write
Chip select
Data strobe
A
Data/address
Interrupt
Ready
HCNTL[1:0]
HR/W
HCS
HDS1
HDS2
HD[31:0]
HINT
HRDY
HPI Host
Logic high HAS
No connect HHWIL
Logic high
2
32
DSP
Read/Write
Chip select
Data strobe
A
Data/address
Interrupt
Ready
HCNTL[1:0]
HR/W
HCS
HDS1
HDS2
HD[15:0]
HINT
HRDY
HPI
DSP
Host
Address latch enable HAS
HHWIL
Logic
high
HD[31:16]
No
connect
2
16
16

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Read/Write
Chip select
Data strobe
A
Data
Interrupt
Ready
HCNTL[1:0]
HR/W
HCS
HDS1
HDS2
HD[15:0]
HINT
HRDY
HPI
DSP
Host
HAS
HHWIL
Logic high
Logic high
Address
or I/O
HD[31:16] No connect
2
16
16

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HDS1
HDS2
HCS
HRDY
Internal
HSTRB
Internal
HRDY

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Data 2 Data 1
HCS
HAS
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
A
HHWIL
Internal
HPI latches
control information
Host latches
data
HPI latches
control information
Host latches
data

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HCS
HAS
HSTRB
HR/W
HCNTL[1:0]
HRDY
A
HHWIL
Data 1 Data 2 HD[15:0]
Internal
HPI latches
control information
HPI latches
data
HPI latches
control information
HPI latches
data

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Data 2 Data 1
HCS
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
A
HHWIL
Internal
HPI latches
control information
Host latches
data
HPI latches
control information
Host latches
data

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HCS
HSTRB
HRDY
A
HR/W
HCNTL[1:0]
HHWIL
Data 1 Data 2 HD[15:0]
Internal
HPI latches
control information
HPI latches
data
HPI latches
control information
HPI latches
data

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Data 1
HCS
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
HHWIL
Internal
Valid
00
Valid

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1st halfword
00 or 10 00 or 10
2nd halfword
Internal
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HSTRB
HCS
HCNTL[1:0]
HR/W
HHWIL
Internal
HSTRB
HD[15:0]
HRDY
1st halfword 2nd halfword 1st halfword 2nd halfword
11 11 10 10
HPIA write HPID read
HCS
Internal
HRDY
HD[15:0]
HR/W
HCNTL[1:0]
HHWIL
10 10 01 01 01
1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword
HSTRB
HPIA write HPID+ reads

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1st halfword 2nd halfword

00 00
Internal
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HSTRB
10 10 11 11
1st halfword 2nd halfword 2nd halfword 1st halfword
Internal
HSTRB
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HPIA write HPID write
10 10 01 01 01
1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword
Internal
HSTRB
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HPIA write HPID+ writes

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10 10 01 01 01
1st halfword 2nd halfword 1st halfword 2nd halfword 1st halfword
Internal
HSTRB
HD[15:0]
HRDY
HHWIL
HR/W
HCNTL[1:0]
HCS
HPIA write HPID+ writes

00 or 10
HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS

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11 10
HPIA Write HPID Read
HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS
10 01 01 01
HPIA Write HPID+ Reads
HD[31:0]
HRDY
HCS
A
HCNTL[1:0]
HR/W
Internal
HSTRB

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00 HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS
10 11
HPIA Write HPID Write
HRDY
HR/W
Internal
HSTRB
HCS
HCNTL[1:0]
HD[31:0]

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10
01 01 01
HPIA Write HPID+ Writes
HCNTL[1:0]
HD[31:0]
HRDY
HR/W
Internal
HSTRB
HCS
A
10
01
01
01
HPIA Write HPID+ Writes
HD[31:0]
HRDY
Internal
HSTRB
HCS
A
HCNTL[1:0]
HR/W

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DSPINT=0
DSPINT=1
CPU writes 1
to DSPINT bit
Interrupt
pending
Host writes 0
to DSPINT bit
No interrupt/
interrupt
cleared
Host writes 0 or 1
to DSPINT bit
CPU writes 0
to DSPINT bit
CPU writes 0 or 1
to DSPINT bit
Host writes 1
to DSPINT bit
(interrupt generated
to CPU)
(A)

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HINT bit=0
HINT signal
is high
is low
HINT signal
HINT bit=1
CPU writes 1
to HINT bit
Host writes 1
to HINT bit Interrupt
active
CPU writes 0
to HINT bit
No interrupt/
interrupt
cleared
Host writes 0 or 1
to HINT bit
CPU writes 0 or 1
to HINT bit
Host writes 0
to HINT bit

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Write FIFO
control logic
Host write
pointer
HPI DMA
read pointer
Write FIFO
Host
writes
Read FIFO
reads
Host
control logic
Read FIFO
Host read
pointer
HPI DMA
write pointer
HPI
DMA
logic
Switched
central
Burst
writes
reads
Burst
resource
DSP
internal/
external
memory

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