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Substrate bounce in mixed-

mode CMOS IC’s

Bram Nauta
http://icd.el.utwente.nl
b.nauta@el.utwente.nl

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contents
• substrate noise in CMOS
• problems in analog
• strategy for analog
• examples
• conclusion

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substrate noise in CMOS

substrate is low-Ohmic! 10mΩcm

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• digital Vss is tied to substrate: Vssd=Vsub
• digital logic draws peak currents
• PCB ground is not available on-chip (due to L bondwire)

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substrate voltage

G,
9VXE =/
GW

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problems in analog:

in band
• coupling sampling
out band

demodualtion

• guardrings dont help

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example : current mirror

VT modulation

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• connect Vssa to substrate

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Cascodes must also follow the substrate

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strategy for analog
• Connect analog Vss to dirty substrate
• NMOS: for DC current sources
• PMOS: for signal handling
• Use differential signals
• Use shielding for non-substrate related signals

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Vssa=substrate=Vssd
analog signals referred to outside cean PCB ground

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Examples
OTA

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What about the N-well connection?

for signals referred to clean (PCB) ground


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shielding

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bandgap: wrt analog PCB ground

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bandgap: wrt analog PCB ground

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bandgap: wrt dirty substrate

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bandgap: wrt dirty substrate

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bandgap: experimental results

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current controlled oscillator:

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opamp

signals referred to clean PCB ground


Vss=substrate=dirty
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simplified model:

• Inoise must be delivered by (non-linear) gm stage


• Vnoise=Inoise/gm at input

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• compensation
• linearisation

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opamp testchip:

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experimental results:

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conclusions
• connect analog Vss to dirty substrate
• analog signals referred to clean PCB ground
• NMOS as DC current source
• PMOS for signal handling
• Differential signals
• Watch out for the well connection
• shielding
• Compensation
• Linearisation

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