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Code No: D0601
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech II SEMESTER EXAMINATIONS APRIL/MAY-2013
ADVANCED COMPUTER ARCHITECTURE
(DIGITAL SYSTEMS & COMPUTER ELECTRONICS)
Time: 3hours Max.Marks:60
Answer any five questions
All questions carry equal marks
- - -

1.a) Categorize the types of operations and explain each with an example.
b) Explain the three most common uses of displacement addressing.

2.a) What is Branch prediction? Explain the common techniques to predict branching
b) What is instruction cycle? Explain the sub-cycles of instruction cycle with a neat
diagram.

3.a) Draw the timing diagram of bus read operation and explain.
b) Explain in brief about the transaction processing benchmarks.

4. Discuss in detail about practical issues in interconnection networks.

5.a) Explain the concept of multiprocessor cache coherence.
b) Discuss in detail about the snooping protocols.

6. Explain in detail about directory based cache coherence protocol.

7.a) Explain the problems involved in parallel processing
b) Write in detail about horizontal and vertical instruction formats.

8.a) Discuss about the purpose of segmentation.
b) Explain the role of cache memory in evaluating pipeline performance.

*****
R09
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