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VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER USING

BEHAVIORAL MODELLING

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity siso is

Port ( sin,clk,rst : in STD_LOGIC;

q: inout std_logic_vector(2 downto 0);

sout : out STD_LOGIC);

end siso;

architecture Behavioral of siso is

COMPONENT DFF

PORT (data,clock,rst:in std_logic;output:out std_logic);

end component;

begin

d0: dff port map(sin,clk,rst,q(0));

d1: dff port map(q(0),clk,rst,q(1));

d2: dff port map(q(1),clk,rst,q(2));

d3: dff port map(q(2),clk,rst,sout);

end Behavioral;
(a)

(b)

FIG4.2 RTL SCHEMATIC FOR SERIAL IN SERIAL OUT SHIFT REGISTER USING
BEHAVIORAL MODELLING
FIG4.3 WAVEFORM FOR SERIAL IN SERIAL OUT SHIFT REGISTER USING
BEHAVIORAL MODELLING