Formal Verification used to compare RTL at either same or different stages of design cycle which can

also be represented by equivalency checking based on some proven mathematical approaches. for
example, formality (Synopsys), conformal LEC (Cadence) and SpyGlass CDC (Atrenta) etc. Functional
Verification is used to check the RTL description w.r.t. its specification. Formal methods can be used for
functional verification as well. The functional verification mostly driven by inputs to verify output. For
example, ModelSim (Mentor), NC-Sim (Cadence), VCS (Synopsys) etc.

Functional verification is time-consuming and most of the time, it is difficult to cover all feasible states in
the design, whereas with the formal methods, it is easier to explore all the feasible states in the design. I
found that the formal tools provides more debug information for any issue in the design, so debugging is
easier.