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Final Project Digital Logic Design - EENG 2710

Caleb Smith
Design Specifications
Design a digital clock in the HH:MM:SS format. The hours will display from 0 to 23.
Design Approach
The design, at the top level, is composed of two mod-60 counters and a mod-24
counter, with the first mod-60 counter connected to the second mod-60 so that it counts once
as the first mod-60 would have counted 60, and the second mod-60 connected to the mod-24
so that it counts whenever the second mod-60 would have counted 60. The counters would
output to a number display.
Logic Diagram of the Top-Level Design






Implementation
Since counters were needed, the first step was to build a flip-flop to actually construct
the counters. The plan for the counters involved an edge-triggered JK flip-flop, which utilizes an
edge-triggered D flip-flop in its design. The D flip-flop is designed as follows, with a PRE and
CLR to set the flip-flops output to 1 and 0, respectively.
mod-60
counter
mod-60
counter
mod-24
counter
display display display

The edge-triggered D flip-flop was then used to make a negative-edge-triggered JK flip-
flop. The decision to use edge-triggered flip-flops was for the sake of being used in modulus
counters at later stages in the design. The nature of the modulus counters, in particular the
fact that the output reaching a certain value would reset the counter, could have caused
problems if the flip-flops/counters were active the whole time that they were receiving the
correct value from the clock. In addition, using edge-triggered parts allowed both for easier
testing and consistent times between each count, which is necessary for a clock.



Next, six of the JK flip-flops were placed in sequence. They all had a common CLR and
PRE signal (there is no foreseeable reason to want to set any given flip-flop to a value but not
the others, since this counter will be used in a clock), as well as a Count signal which will
function kind of like a gate; the counter will not count without it. The Count signal is attached
to both the J and K inputs of the JK flip-flop. This particular counter is asynchronous; instead of
a common clock signal, the first flip-flop in the sequence will receive a regular clock signal, and
the subsequent flip-flop will receive the output (Q) of the previous flip-flop. The outputs of each
flip-flop are also output of the counter itself, with the first outputting X0, the first bit value in
the 6-bit number (from 0 to 63). The counter is as shown below:
Another counter was made in the same fashion. This second counter had only 5 negative-edge-
triggered JK flip-flops, and therefore only counts up from 0 to 31.

The next step was to take the counters and make them reset when a certain value was
reached (60 for the 0-to-63 counter and 24 for the 0-to-31 counter), making modulo counters.
To accomplish this, the X0 through X5 outputs were connected to a NAND gate, with X5, X4,
and X3 passing through an AND gate first (for simplicitys sake), and X2, X1, and X0 passing
through an AND gate (after X1 and X0 pass through a NOT gate). The NAND gate, taking both
the signals from the previous two AND gates and the CLR signal will pass a value of 0 into the
CLR input of the clock when the counter outputs 111100 (60 in decimal), causing the counter
to clear and the count to start over. The mod-24 counter works basically the same, but with X4
and X3 going through an AND gate (without a NOT gate) and X2, X1, X0 going through NOT
gates and then an AND gate. The output of those two AND gates goes through a NAND gate
along with the CLR signal. This NAND gate sends an output of 0 to CLR when the counter
outputs 11000 (24 in decimal), resetting the counter. Mod-60 then mod-24 shown below.



The final step was to use the two kinds of clocks to build the clock. Two mod-60
counters were attached to displays for the minute and second counts, respectively. A mod-24
counter was attached to a display for the hour count. As a shortcut, and since the
specifications didnt specify, I used the 8-bit display provided in the program used to make the
layout the circuit. (The reason I used this display instead of the basic display is that this display
can take input and convert it to double-digit decimal numbers. It was a timesaver.)
Each of the mod-counters have a common Count, PRE, and CLR signals. The first mod-
60 counter takes a clock signal. The subsequent counters will receive an input based on the
output of the previous clock, much like CLR input in the mod-counters themselves. For the first
mod-60 counter, X0 and X1 (after passing through a NOT gate) and X2 go through an AND gate,
X3, X4, and X5 pass through an AND gate, and the output from those two AND gates is
connected to a NAND gate. This NAND gate is output to the CLK signal of the second mod-60
counter, and sends a 0 when the first mod-60 outputs 111100 and 1 otherwise, creating a
negative pulse and making the second mod-60 will only count when the first counts 60 and
resets . The exact same set of NOT, AND, and NAND gates are connected to the mod-24
counters CLK signal, again sending a 0 on the output of 111100 from the mod-60 and a 1
otherwise, and again enabling the mod-24 counter to count when the second mod-60 counts
and resets at 60. The clock is shown on the next page.



Timing Diagram(s) for the Clock
Minute counter (and display) counting on reset of second counter at 60.

Hour counter (and display) counting on reset of minute counter at 60.


Test Plan
The method of testing this clock is straightforward. Since there is no (foreseeable) need
to check for errors where inputs or outputs are concerned (like some particular line being stuck
at 0 or 1), it was decided that making sure each component used in the system design should be
sufficient.
For the lowest level component in the design, the edge-triggered D flip-flop, a test was
conducted to make sure that an input of 1 on the PRE input and 0 on the CLR input would
reset the flip-flops output to 0, and, when both PRE and CLR are high, the D value will be
propagated on an edge (in this case, the positive edge).

For the next level, the edge-triggered JK flip-flop, was tested in a similar manner. Since
the flip-flops would be used in a counter design where both the J and K inputs receive a 1 input
at all times, they were kept at 1. The flip-flop was first tested to see if a 1 on PRE and 0 on CLR
would clear the output, and then tested for the flip-flop switching from 0 to 1 and 1 to 0 on a
clock edge (the negative edge, by design).


The next level, the counters, was tested to make sure they actually counted, and that
they reset when they reach the maximum number. To make the testing easier and the timing
diagram more easily readable, a display was attached to the outputs. The timing diagram from
the 0 to 31 counter is shown below.

The timing diagram for 0 to 63 is shown below.


The next level, the modulo counters, were tested in the same manner. Tested to make
sure a 1 on PRE and 0 on CLR sets the counter to 0, and testing to make sure the counter
resets at the appropriate time. As with the tests for the plain counters, a display was
connected to the outputs for ease of testing and readiability. For the modulo 24 counter, a
timing diagram showing that the counter does reset the instant the counter reaches 24 is
shown below.

The timing diagram for the modulo 60 counter, showing that the counter resets when
the counter reaches 60, is shown below.


Conclusion
This design, while probably not the most resource efficient or elegant option, still
produces a working clock, as far as the conducted tests and runs are concerned. However, a
notable point of concern is that, due to time constraints (caused by badly managed time on my
part), the final version of the clock was not tested completely; it was not allowed to run for an
entire twenty-four hour period. As such, it is possible that the clock does not reset after
twenty-four hours. However, since modulo-24 counter was tested as an individual part, and it
was working, the clock was deemed acceptable enough for a short testing period.

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