KIN TRC MY TNH

V H IU HNH

CHNG 3: K THUT PIPELINING

3.1 K thut pipelining
3.2 Pht trin pipelining

3.1 K thut pipelining
3.1.1 Tun t Von Neumann v Pipeline
* Cu trc tun t:
+ Thc hin cc lnh mt cch tun t.
+ 5 khu :
- IF ( instruction Fetch ) : Nhn lnh
- ID( Instruction Decode ): Gii m lnh
- DF( Data Fetch ): Nhn d liu
- EX( Excution): Thc hin lnh
- DS( Data Save): Lu kt qu
+ V d:
- Gi s mi lnh thc hin trong mt chu k
- Mi khu thc hin trong thi gian /5
- Vi n lnh:
Tun t = * n
+ Hn ch
- Cc lnh c thc hin lin tip nhau
- Lnh trc thc hin xong mi n lnh sau
- Xut hin khong thi gian ri ( stall ) gia cc khu
K thut pipeline c a ra vn dng nhng stall ny, t tng tc
cho vi x l.


+ 5 khu ca mt lnh trong MIPS ( microprocess without interlocked pipeline
stages)
1. F ( Fetch ): Nhn lnh
2. D ( Decode ): Gii m lnh.
3. X ( Excution ) : Thc hin lnh
4. M ( Memory Acces ) : Truy cp b nh
5. W ( Result Write Back ) : Ghi kt qu

+ M hnh Pipeline l tng: Thng lng trung bnh l 1 CPI ( Clock cycle per
Instruction )












+ M hnh pipeline l tng : Tpipeline = + * (n-1)/m
- Tnh ton:
Thi gian thc thi 1 cng on l /5.
Thi gian thc thi 1 lnh l .
Thi gian thc thi 2 lnh l + /5.
Thi gian thc thi 3 lnh l + *2/5
.
Thi gian thc thi n lnh l + *(n-1)/5


* nh ngha Pipeline:

+ K thut thc hin lnh trong cc lnh c thc hin theo kiu gi u nhm
tn dng nhng khong thi gian ri ( Stalls ) gia cc cng on (
Stages ), qua lm tng tc thc hin lnh ca vi x l ( VXL ).
+ Trong trng hp khng c xung t c th tng tc vi x l ln 400%.

3.1.2: Xung t ( Hazard )
Xung t cu trc ( Structural Hazard )
Xung t d liu ( Data Hazard )
Xung t iu khin ( Control Hazard )
+ Xung t Cu Trc: Xy ra khi c 2 lnh cng c gng s dng cng 1 ngun
ti cng 1 thi im
- Khi 2 lnh cng ghi kt qu vo 1 thanh ghi:
ADD R1, R2, R3.
SUB R1, R4, R5.
- Khi c 2 lnh cng truy cp vo 1 nh ti cng mt thi im.
- Khi c 2 lnh cng yu cu mt s tnh ton s hc ( B cng, b nhn, b
chia ).
- Xung t xy ra khi vic np lnh v c d liu t b nh din ra cng lc.












- Nhng k hiu o chn vo tng trung cho chu k tr ( stall cycle ) s
c s dng nu ta s dng b nh n lu tr c lnh vo d liu.
- Khi c stage X v D u yu cu b cng, m ch c 1 b cng trong VXL







+ Xung t d liu:
- RAW ( Read After Write ) :
Instruction 1: ADD R2, R1, R3 R2 R1 + R3
Instruction 2: ADD R4, R2, R3 R4 R2 + R3






- WAR ( Write After Read) :
Instruction 1: ADD R1, R2, R3 R1 R2 + R3
Instruction 2: ADD R3, R4, R5 R3 R4 + R5







- WAW ( Write After Write ):
Instruction 1: ADD R2, R1, R3 R2 R1 + R3
Instruction 2: ADD R2, R4, R7 R2 R4 + R7



+ Xung t iu khin:

- Control Hazard xy ra khi c lnh r nhnh

- Khi lnh r nhnh c yu cu thc hin, con tr b m chng trnh (PC)
s chuyn ti a ch ch bng cch cng thm 4.

Nhy ti ng a ch r nhnh: r nhnh Taken

Trng hp ngc li gi l nhnh Untaken.

- Khi lnh i c r nhnh Taken th PC khng thay i nh bnh thng ti ht
khu M ( Memory Access ).

- Phng php n gin nht khc phc Control Hazard l gy tr kp thi
trn Pipeline pht hin nhnh n khu M, s dng gi tr mi ca PC.



















3.2 iu khin Pipeline

+ Xung t ( Hazard ) l mt yu t quan trng nh hng trc tip ti tc ca
VXL trong k thut Pipieline.

+ Mt s k thut gii quyt xung t ch yu:
- Chn tr
- T chc li cc lnh
- S dng ng d liu ni c bit
- Tomasulo
- nh biu

3.2.1: Chn tr

+ K thut chn tr c s dng kh hu hiu gii quyt cc xung t v cu
trc cng nh v d liu:

+ V d:









+ Xung t d liu xy ra khi lnh 1 cha lu kt qu vo R1 th lnh 2 thc
hin tr R1 cho R5 ( RAW ).






+ Chn tr:










+ K thut chn tr ny kh n nh, tuy nhin vn cn cha tn dng c nhiu
chu k nhn ri ca my, do hiu sut cha cao.

3.2.2: T chc li cc lnh.

K thut ny i hi trnh dch phi d on c s ph thuc d liu gia
cc lnh, qua thay i trt t thc hin lnh.

3.2.3: S dng ng d liu ni c bit.

Gi tr ca bin s c cp nhp rt sm nh s dng ng d liu ni
c bit. iu ny lm gim s chu k nhn ri trong Pipeline v tng tc ca
Vi x l.