library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity fifo is
port(
CLR : in std_logic;
CLRptr : in std_logic;
RDinc : in std_logic;
WRinc : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
DATA : in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0)
);
end entity;

--}} End of automatically maintained section

architecture fifo_arch of fifo is

type fifo_array_type is array (7 downto 0) of std_logic_vector (3 downto 0);

defining a array matrix

signal fifo_array : fifo_array_type;

signal WR_PTR : INTEGER range 0 to 7;
signal RD_PTR : INTEGER range 0 to 7;

begin

process (CLR, CLK)

begin
if CLR = '1' then
for INDEX in 7 downto 0 loop
fifo_array(INDEX) <= (others => '0');
Resets all values to 0 words
end loop;
elsif rising_edge(CLK) then
if WR = '1' then
fifo_array(WR_PTR) <= DATA;
end if;
end if;
end process;
Data is stored in arra which is defined

process (CLR, CLK)

variable PTR : INTEGER range 0 to 8;
read write access
begin
if CLR = '1' or CLRptr = '1' then
WR_PTR <= 0;
RD_PTR <= 0;
PTR := 0;
elsif rising_edge(CLK) then
if WRinc = '1' and PTR < 8 then
 if WR_PTR < 7 then
WR_PTR <= WR_PTR + 1;
elsif WR_PTR = 7 then
WR_PTR <= 0;
end if;
PTR := PTR + 1;
elsif RDinc = '1' and PTR > 0 then
if RD_PTR<7 then
RD_PTR <= RD_PTR + 1;
elsif RD_PTR = 7 then
RD_PTR <= 0;
end if;
PTR := PTR - 1;
end if;
end if;

end process;

Q <= fifo_array(RD_PTR) when RD = '1' else (others => 'Z');

end architecture;