All Logic Gates (Gate Level modelling)

module all_logic_gate_level(or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out,x,y);
input x,y;
output or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out;
or g1(or_out,x,y);
and g2(and_out,x,y);
xor g3(xor_out,x,y);
not g4(not_out,x);
nand g5(nand_out,x,y);
nor g6(nor_out,x,y);
xnor g7(xnor_out,x,y);
endmodule
All Logic Gates (Dataflow modelling)
module all_logic_dataflow(or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out,x,y);
input x,y;
output or_out,and_out,xor_out,not_out,nand_out,nor_out,xnor_out;
assign or_out = x|y;
assign and_out = x&y;
assign xor_out = x^y;
assign not_out = ~x;
assign nand_out = ~(x&y);
assign nor_out = ~ (x|y);
assign xnor_out = ~(x^y);
endmodule
OR Gate (Behaviour Modelling )
module or_behav(y,a,b);
output y;
input a,b;
reg y;
always @ (a or b)
begin
if (a == 0)
begin
if (b == 0)
y = 1 'b 0;
else
y = 1 'b 1;
end
else
y = 1 'b1;
end
endmodule

Half Adder Gate Level Modelling

module half_adder_gate (sum,carry,x,y);
output sum,carry;
input x,y;
xor (sum,x,y);
and (carry,x,y);
endmodule
Half Adder Dataflow Modelling
module half_adder_dataflow (sum,carry,x,y);
output sum,carry;
input x,y;
assign sum = x^y;
assign carry = x&y;
endmodule
Full Adder Dataflow Modelling
module full_adder_dataflow(a,b,c, sum, carry);
input a,b,c;
output sum, carry;
assign sum = a ^b ^c;
assign carry = (a & b) | (b&c) | (c &a);
endmodule
Full Adder Gate Level Modelling
module full_adder_gate(a,b,c, sum, carry);
input a,b,c;
output sum, carry;
wire [3:1]w;
xor g1(sum, a,b,c);
and g2(w[1],a,b);
and g3(w[2],b,c);
and g4(w[3],c,a);
or g5(carry, w1,w2,w3);
endmodule
Half Subtractor Gate Level Modelling
module half_sub_gate (difference,barrow,x,y);
output difference,barrow;
input x,y;
wire w;
not g0(w,x);
xor g1(difference,x,y);
and g2(barrow,x,y);// and g2(barrow,~(x),y);
endmodule
Half Subtractor Dataflow Modelling
module half_sub_dataflow (difference,barrow,x,y);
output difference,barrow;
input x,y;
assign difference = x^y;

assign barrow = (~x)&y;

endmodule
Full Subtractor Dataflow Modelling
module full_sub_dataflow (difference,barrow,x,y,z);
output difference,barrow;
input x,y,z;
assign difference = x^y^z;
assign barrow = ( ( (~(x))&y) | (y & z) | ((~(x)) & z));
endmodule
Full Subtractor Gate Level Modelling
module full_sub_gate (difference,barrow,x,y,z);
output difference,barrow;
input x,y,z;
wire [3:0]w;
xor g1(difference,x,y,z);
not g2(w[0],x);
assign barrow = ( ( (~(x))&y) | (y & z) | ((~(x)) & z));
endmodule
4x1 Multiplexer Gate Level Modelling
module mux_4X1_gate(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
wire [3:0]w;
and g0(w[0],d,~sel[0],~sel[1]);
and g1(w[1],d,sel[0],~sel[1]);
and g2(w[2],d,~sel[0],sel[1]);
and g3(w[3],d,sel[0],sel[1]);
or g4(y,w[0],w[1],w[2],w[3]);
endmodule
4x1 Multiplexer Dataflow Modelling
module mux_4X1_dataflow(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
assign y = (d & ~sel[0]& ~sel[1])|(d & sel[0] & ~sel[1])| (d & ~sel[0] & sel[1])| (d & sel[0] & sel[1]);
endmodule
4x1 Multiplexer Behaviour (CASE) Modelling
module mux_4X1_behav_case(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
reg y;
always @(d or sel)
begin
case (sel)

2'b00:y=d[0];
2'b01:y=d[0];
2'b10:y=d[0];
2'b11:y=d[0];
default:y=1'bx;
endcase
end
endmodule
4x1 Multiplexer Behaviour (IF) Modelling
module mux_4X1_behav_if(d,sel,y);
input [3:0]d;
input [1:0]sel;
output y;
reg y;
always @(d or sel)
begin
if (sel==00)
y=d[0];
else if (sel==01)
y=d[1];
else if (sel==10)
y=d[2];
else
y=d[3];
end
endmodule

1X4 De-Multiplexer Gate Level Modelling

module demux_1X4_gate(din, sel, dout);
input din;
input [1:0]sel;
output [3:0]dout;
and g0(dout[0],din,~sel[0],~sel[1]);
and g1(dout[1],din,sel[0],~sel[1]);
and g2(dout[2],din,~sel[0],sel[1]);
and g3(dout[3],din,sel[0],sel[1]);
endmodule
1X4 De-Multiplexer Behaviour Level Modelling
module demux_1X4_behav_if(din, sel, dout);
input din;
input [1:0] sel;
output [3:0] dout;
reg [3:0] dout;
always @ (din or sel)
begin
if(~din)
dout=4'b0000;

else
if (sel==00)
dout=4'b0001;
else if (sel==01)
dout=4'b0010;
else if (sel==10)
dout=4'b0100;
else
dout=4'b1000;
end
endmodule
1X4 De-Multiplexer Behaviour Level Modelling
module demux_1X4_behav_case(din, sel, dout);
input din;
input [1:0] sel;
output [3:0] dout;
reg [3:0] dout;
always @ (din or sel)
case(sel)
2'b00: dout[0]=din;
2'b01: dout[1]=din;
2'b10: dout[2]=din;
2'b11: dout[3]=din;
endcase
endmodule
1X4 De-Multiplexer Dataflow Modelling
module demux_1X4_dataflow(din, sel, dout);
input din;
input [1:0]sel;
output [3:0]dout;
assign dout[0]=(~sel[0] & ~sel[1] & din);
assign dout[1]=(sel[0] & ~sel[1] & din);
assign dout[2]=(~sel[0] & sel[1] & din);
assign dout[3]=(sel[0] & sel[1] & din);
endmodule
4X2 Encoder Behaviour (CASE) Modelling
module encoder_4x2_behav_case (y,x);
output [0:3] y;
input [0:3] x;
reg [0:1] y;
always @ (x)
case (x)
4'b0001: y = 11;
4'b0010: y = 10;
4'b0100: y = 01;
4'b1000: y = 00;
//default : y=2'bzz;
default : $display ("Invalid Input");

endcase
endmodule
4- Bit Comparator
module compare(a, b, aeqb, agtb, altb);
input [3:0] a, b;
output aeqb, agtb, altb;
reg aeqb, agtb, altb;
always @ (a or b)
begin
if (a==b)
aeqb=1'b1;
else if (a>b)
agtb=1'b1;
else
altb=1'b1;
end
endmodule

module adder(a, b, ci, sum);

input [7:0] a;
input [7:0] b;
input
ci;
output [7:0] sum;
assign sum = a + b + ci;
endmodule

module addsub (
input [7:0] dataa,
input [7:0] datab,
input add_sub,
// if this is 1, add; else subtract
input clk,
output reg [8:0] result);
always @ (posedge clk)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule

module dff(data,clk,reset,q,qb);
input data, clk, reset ;
output q,qb;
reg q,qb;
always @ ( posedge clk or posedge reset )
begin
if (reset)
begin
q <= 1'b0;
qb <= 1'b1;
end
else
begin
q <= data;
qb<= ~data;
end
end
endmodule

module dff_behav(q,qbar,d,clk,clr);
output q,qbar;
input d,clk,clr;
reg q,qbar;
always @ (clr or posedge clk)
begin
if (~clr)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
q = d;
assign qbar = ~q;
end
end
endmodule
module dff_gate (q,qbar,d,clk,clr);
output q,qbar;
input d,clk,clr;
wire temp1,temp2,temp3,temp4,high;
assign high = 1'b1;
nand na0 (temp1,d,clk);
nand na1 (temp2,~d,clk);
nand na2 (temp3,qbar,temp1);
nand na3 (temp4,q,temp2);
and a0 (q,temp3,clr);
and a1 (qbar,temp4,high);
endmodule
module srff_behav (q,qbar,s,r,clk,clr);
output q,qbar;
input s,r,clk,clr;
reg q,qbar;
always @ (posedge clk or clr)
if (clr)
begin
if (clk)
begin
if (s ==0)
begin
if(r ==0)
begin
q = q;
qbar = qbar;
end
else
begin
q = 0;
qbar = 1;
end
end
else
begin
if (r ==0)
begin
q = 1;

qbar = 0;
end
else
begin

end
end
end
else
begin

q = 1'bz;
qbar = 1'bz;

end

q = 1'b0;
qbar = 1'b1;

end
endmodule

module srff_gate (q,qbar,s,r,clk,clr);

output q,qbar;
input s,r,clk,clr;
wire a,b,c,d,high;
assign high = 1'b1;
nand na0(a,s,clk);
nand na1(b,r,clk);
nand na2(c,qbar,a);
nand na3(d,q,b);
and a0 (q,c,clr);
and a1 (qbar,d,high);
endmodule

module jkff_behav (q,qbar,j,k,clk,reset);

output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (posedge clk or posedge reset)
if (reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1;
qbar = 1'b0;
end
else if (j ==1 && k ==1)

begin
q = ~q;
qbar = ~qbar;
end
else
begin
q = 1'bz;
qbar = 1'bz;
end
end
endmodule

module tff_behav (q,qbar,t,clk,reset);

output q,qbar;
input t,clk,reset;
reg q,qbar;
always @ (reset or posedge clk)
if (reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
q = t^q;
qbar = ~q;
end
endmodule

//Counter Design
module counter(clk, reset,result); //,ena
input clk, reset;
output [3:0]result;
reg [3:0] result;
always @(negedge clk or posedge reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule

//Mod-10 Counter Design

module counter_ten(out,clk,reset);
output [3:0]out;
input clk, reset;
reg [3:0] out;
always @(posedge clk or posedge reset)
begin
if(clk)

if(reset)
out <=4'b0000;
else
if (out==4'b1001)
out<=0;
else
out<=out+1;
end
endmodule

//Up/Down Counter Design

module counter_up_down(out,clk,reset,control);
output [3:0]out;
input clk, reset,control;
reg [3:0] out;
always @(negedge clk or posedge reset)
if(reset)
out <=4'b0000;
else
if (control)
out<=out+1;
else
out<=out-1;
endmodule

module SISO(clk, sr_in,sr_out);

input clk;
input sr_in;
output sr_out;
reg [3:0]sr;
always@(negedge clk)
begin
sr[0] <= sr_in;
sr[1] <= sr[0];
sr[2] <= sr[1];
sr[3] <= sr[2];
end
assign sr_out = sr[3];
endmodule

module PISO(clk, pr_in,sr_out,cntrl);

input clk,cntrl;
input [3:0]pr_in;
output sr_out;
reg [3:0]sr;
always@(negedge clk)

begin
if(cntrl)
begin
sr[0] <= pr_in[0];
sr[1] <= pr_in[1];
sr[2] <= pr_in[2];
sr[3] <= pr_in[3];
end
else
begin
sr[0] <= pr_in[0];
sr[1] <= sr[0];
sr[2] <= sr[1];
sr[3] <= sr[2];
end
end
assign sr_out = sr[3];
endmodule

module PIPO(clk, pr_in,pr_out);

input clk;
input [3:0]pr_in;
output [3:0]pr_out;
reg [3:0]pr_out;
always@(negedge clk)
begin
pr_out[0] <= pr_in[0];
pr_out[1] <= pr_in[1];
pr_out[2] <= pr_in[2];
pr_out[3] <= pr_in[3];
end
endmodule

module SIPO(clk, sr_in,pr_out);

input clk;
input sr_in;
output reg[3:0]pr_out;
always@(negedge clk)
begin
pr_out[0] <= sr_in; // non blocking assignment execute same time
pr_out[1] <= pr_out[0];
pr_out[2] <= pr_out[1];
pr_out[3] <= pr_out[2];
end
endmodule