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Lab3:Design a MIPS 32-bit Single-Cycle CPU

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Lab3:Design a MIPS 32-bit Single-Cycle CPU


I.

Requirement:

II.

III.

Design a simple 32-bit MIPS Single-Cycle CPU can implements these instructions: LW,
SW, J, JR, BNE, XORI, ADD, SUB, and SLT.

All instructrions can be handled in one cycle.


Design is based on available module : regfile, alu, instrmem, and datamem.
Instruction set: 3 formats
1. R-format:
ADD, SUB, SLT, JR.
Meaning:
o ADD
rd,
rs,
rt;
Reg[rd] = Reg[rs] + Reg[rt].
o SUB
rd,
rs,
rt;
Reg[rd] = Reg[rs] + Reg[rt].
o SLT
rd,
rs,
rt;
If (Reg[rs] <Reg[rt]) Reg[rd] =1
Else
Reg[rd] =0.
o JR rs;
PC = Reg[rs].
Form:
Opcode
Rs
Rt
Rd
Shamt
function
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
2. I- format:
LW, SW, BNE, XORI
Meaning:
o LW
rt,
imm16(rs);
Reg[rt] = Mem[ Reg[rs] + Sign_ext(Imm16)].
o SW
rt,
imm16(rs);
Mem[ Reg[rs] + Sign_ext(Imm16)] = Reg[rt].
o BNE
rs,
rt,
imm16;
If(Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(imm16)<<2
Else
PC = PC + 4.
o XORI
rt,
rs,
imm16;
Reg[rt] = Reg[rs] XOR Zero_ext(Imm16).
Form:
Opcode
Rs
Rt
Immediate
6 bits
5 bits
5 bits
16 bits
3. J-format:
J
Meaning:
o J target;
PC = { PC[31:28], target, 00}.
Form:
Opcode
Target address
6 bits
26 bits
Design:
-

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Block diagram:

Lab3:Design a MIPS 32-bit Single-Cycle CPU

We must design 5 parts:


Extended,
Shift left 2 bits
Branch : Mux2to 1 32 bits and 5 bits;
ALU adder;
ALU control;
Control;
PC register
1. Extended
Block diagram:

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Meaning: it is used to help part Immediate of I-format instruction (16bit) become


addresses or number 32 bits. Whether the extension is 1 or 0 depends on the Signal
SignEx of Control Block.

Lab3:Design a MIPS 32-bit Single-Cycle CPU


-

Verilog code:

1 module
extended(out, in, Signed);
2
output
[31:0]out;
3
input
[15:0]in;
4
input
Signed;
5
assign
out[15:0]=in;
6
and
and16(out[16],out[15],Signed);
7
and
and17(out[17],out[15],Signed);
8
and
and18(out[18],out[15],Signed);
9
and
and19(out[19],out[15],Signed);
10
and
and20(out[20],out[15],Signed);
11
and
and21(out[21],out[15],Signed);
12
and
and22(out[22],out[15],Signed);
13
and
and23(out[23],out[15],Signed);
14
and
and24(out[24],out[15],Signed);
15
and
and25(out[25],out[15],Signed);
16
and
and26(out[26],out[15],Signed);
17
and
and27(out[27],out[15],Signed);
18
and
and28(out[28],out[15],Signed);
19
and
and29(out[29],out[15],Signed);
20
and
and30(out[30],out[15],Signed);
21
and
and31(out[31],out[15],Signed);
22 endmodule
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Simulate on Quartus:

Lab3:Design a MIPS 32-bit Single-Cycle CPU

2.

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Shift left 2 bits:


We build 2 block shift left because of different size of input and output.
a) Shift left 2 bit for 32 bits:
Block diagram:

Lab3:Design a MIPS 32-bit Single-Cycle CPU

Meaning: Since instructions in MIPS are stored as words (1 word = 4 bytes) and
memory of MIPS is addressed by bytes, with all Branch instruction, values must
multiply 4 before sended to PC register ( or shift left 2bits).
Verligog code:

1 module
shift_left2(out, in);
2
output
[31:0]out;
3
input
[31:0]in;
4
assign out = { in[29:0], 2'b0 };
5 endmodule
-

Simulate on Quartus:

b) Shift left 2 bit for 28 bits:


Block diagram

Verilog code:

1 module shift_left2_jump(out, in);


2
output [27:0] out;
3
input [25:0] in;
4
assign out = { in, 2'b0 };
5 endmodule
-

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Simulate on Quartus:

Lab3:Design a MIPS 32-bit Single-Cycle CPU

3.

Muxer:
-

Meaning: this block is used to select 1 signal from 2 signals input through by using
signal from Control block.
a) Mux2 to 1:
Block diagram

1 module
2 output
3 input
4 input
5 wire
6 not
7 and
8
9 or
10 endmodule

mux2to1(out,in1,in2,sel);// bo chon kenh 2 - 1


out;
sel;
in1,in2;
[1:0]temp;
NOT1(n_sel,sel);
AND1(temp[0],in1,n_sel),
AND2(temp[1],in2,sel);
OR1(out,temp[0],temp[1]);

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Verilog code:

Simulate on Quartus

Lab3:Design a MIPS 32-bit Single-Cycle CPU

1 module
2 output
3 input
4 input
5 mux2to1
6 mux2to1
7 mux2to1
8 mux2to1
9 mux2to1
10 endmodule

mux2to1_5bits(out,in1,in2,sel);
[4:0]out;
sel;
[4:0]in1,in2;
mux0(out[0],in1[0],in2[0],sel);
mux1(out[1],in1[1],in2[1],sel);
mux2(out[2],in1[2],in2[2],sel);
mux3(out[3],in1[3],in2[3],sel);
mux4(out[4],in1[4],in2[4],sel);

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b) Mux 2 to 1 5 bits:
Verilog code:

Simulate on Quartus

Lab3:Design a MIPS 32-bit Single-Cycle CPU

c)
-

Mux 2 to 1 32 bits:
Verilog code:

1 module
mux2to1_32bits(out,in1,in2,sel);
2 output
[31:0]out;
3 input
sel;
4 input
[31:0]in1,in2;
5 mux2to1_5bits mux0(out[4:0],in1[4:0],in2[4:0],sel);
6 mux2to1_5bits mux1(out[9:5],in1[9:5],in2[9:5],sel);
7 mux2to1_5bits mux2(out[14:10],in1[14:10],in2[14:10],sel);
8 mux2to1_5bits mux3(out[19:15],in1[19:15],in2[19:15],sel);
9 mux2to1_5bits mux4(out[24:20],in1[24:20],in2[24:20],sel);
10 mux2to1_5bits mux5(out[29:25],in1[29:25],in2[29:25],sel);
11 mux2to1
mux6(out[30],in1[30],in2[30],sel);
12 mux2to1
mux7(out[31],in1[31],in2[31],sel);
13 endmodule

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Lab3:Design a MIPS 32-bit Single-Cycle CPU


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Simulate on Quartus

Lab3:Design a MIPS 32-bit Single-Cycle CPU


4.

Adder:
-

Block diagram

Meaning: this block is only used by Branch instructions to calculate the next
instruction to put in PC register.
Verilog code:

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10
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31

//adder 1 bit//
module
add1bit(sum,c_out,A,B,c_in);
output
sum,c_out;
input
A,B,c_in;
wire [2:0]temp;
and
and1(tem1,A,B);
or
or1(tem2,A,B);
and
and2(tem3,tem2,c_in);
or
or2(c_out,tem3,tem1);
xor
xor1(sum,A,B,c_in);
endmodule
//adder 32 bit//
module ADDCPU(sum,c_out,A,B,overflow);
output [31:0]sum;
output c_out,overflow;
input [31:0]A,B;
wire [30:0]carry;
add1bit add0(sum[0],carry[0],A[0],B[0],1'b0);
add1bit add1(sum[1],carry[1],A[1],B[1],carry[0]);
add1bit add2(sum[2],carry[2],A[2],B[2],carry[1]);
add1bit add3(sum[3],carry[3],A[3],B[3],carry[2]);
add1bit add4(sum[4],carry[4],A[4],B[4],carry[3]);
add1bit add5(sum[5],carry[5],A[5],B[5],carry[4]);
add1bit add6(sum[6],carry[6],A[6],B[6],carry[5]);
add1bit add7(sum[7],carry[7],A[7],B[7],carry[6]);
add1bit add8(sum[8],carry[8],A[8],B[8],carry[7]);
add1bit add9(sum[9],carry[9],A[9],B[9],carry[8]);
add1bit add10(sum[10],carry[10],A[10],B[10],carry[9]);
add1bit add11(sum[11],carry[11],A[11],B[11],carry[10]);
add1bit add12(sum[12],carry[12],A[12],B[12],carry[11]);

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Lab3:Design a MIPS 32-bit Single-Cycle CPU

32 add1bit add13(sum[13],carry[13],A[13],B[13],carry[12]);
33 add1bit add14(sum[14],carry[14],A[14],B[14],carry[13]);
34 add1bit add15(sum[15],carry[15],A[15],B[15],carry[14]);
35 add1bit add16(sum[16],carry[16],A[16],B[16],carry[15]);
36 add1bit add17(sum[17],carry[17],A[17],B[17],carry[16]);
37 add1bit add18(sum[18],carry[18],A[18],B[18],carry[17]);
38 add1bit add19(sum[19],carry[19],A[19],B[19],carry[18]);
39 add1bit add20(sum[20],carry[20],A[20],B[20],carry[19]);
40 add1bit add21(sum[21],carry[21],A[21],B[21],carry[20]);
41 add1bit add22(sum[22],carry[22],A[22],B[22],carry[21]);
42 add1bit add23(sum[23],carry[23],A[23],B[23],carry[22]);
43 add1bit add24(sum[24],carry[24],A[24],B[24],carry[23]);
44 add1bit add25(sum[25],carry[25],A[25],B[25],carry[24]);
45 add1bit add26(sum[26],carry[26],A[26],B[26],carry[25]);
46 add1bit add27(sum[27],carry[27],A[27],B[27],carry[26]);
47 add1bit add28(sum[28],carry[28],A[28],B[28],carry[27]);
48 add1bit add29(sum[29],carry[29],A[29],B[29],carry[28]);
49 add1bit add30(sum[30],carry[30],A[30],B[30],carry[29]);
50 add1bit add31(sum[31],c_out,A[31],B[31],carry[30]);
51 xor (overflow,c_out,carry[30]);
52 endmodule
-

5.

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Simulate on Quartus

ALU control:
Block diagram

Lab3:Design a MIPS 32-bit Single-Cycle CPU

Meaning: transforming ALUop signal from Control Block and 6 function bits of
instructions into ALUcontrol signal to order ALU do 4 operands: ADD, SUB, XOR and
SLT.
Truth table:

opcode ALUOp Operation

funct

ALU
function

ALU
control

lw

load word

XXXXXX

add

sw

store word

XXXXXX

add

XORI

Xor
immediately

XXXXXX

Xor

bne

Branch not
equal

XXXXXX

subtract

R-type

add

add

subtract

subtract

jr

non

set-on-lessthan

set-on-lessthan

Verilog code:

1 //alu control//
2 module ALUcontrol(ALUctr,jumpreg,funct,ALUop);

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Lab3:Design a MIPS 32-bit Single-Cycle CPU


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output
output
input
input
wire
wire
wire
not

[1:0]ALUctr;
jumpreg;
[5:0]funct;
[1:0]ALUop;
[1:0]n_ALUop;
[5:0]n_funct;
[9:0]temp;
not0(n_ALUop[0],ALUop[0]),
not1(n_ALUop[1],ALUop[1]),
not2(n_funct[0],funct[0]),
not3(n_funct[1],funct[1]),
not4(n_funct[2],funct[2]);
//ALUctr[0]
and
and0(temp[0],ALUop[0],ALUop[1]),
and1(temp[1],n_ALUop[0],ALUop[1],n_funct[0],funct[1]),
and2(temp[2],n_funct[2],funct[3],n_funct[4],funct[5]),
and3(temp[3],temp[1],temp[2]);
or
or0(ALUctr[0],temp[0],temp[3]);
//ALUctr[1]
and
and4(temp[4],n_ALUop[0],ALUop[1]),
and5(temp[5],n_ALUop[0],ALUop[1],n_funct[0],funct[1]),
and6(temp[6],n_funct[2],n_funct[4],funct[5]),
and7(temp[7],temp[5],temp[6]);
or
or1(ALUctr[1],temp[4],temp[7]);
//jumpreg
and
and8(temp[8],n_ALUop[0],ALUop[1],n_funct[0],n_funct[1]),
and9(temp[9],n_funct[2],funct[3],n_funct[4],n_funct[5]);
or
or2(jumpreg,temp[8],temp[9]);
endmodule

6.

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Control:
-

Simulate on Quartus

Block diagram

Lab3:Design a MIPS 32-bit Single-Cycle CPU

Instruction
Input

Output

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Opcode
Op5
Op4
Op3
Op2
Op1
Op0
Jump
RegDst
ALUScr
MemtoReg
RegWrite
MemRead
MemWrite

Meaning: decode Opcode of instructions into 10 signals to action of other blocks in


Chips.
RegDst:
choose write register for RegisterFile.
RegDst = 0: Rt is write register, I-format.
RegDst = 1: Rd is write register, R-format.
Jump:
enable jump action.
Branch:
enable BNE action.
MemRead: enable read data in data memory.
MemWrite enable write data in Data Memory.
ALUSrc:
choose input for ALU block.
ALUSrc = 0: input is data of register read 2.
ALUSrc = 1: input is value 32 bits which is extended with sign or unsign.
RegWrite: enable write data in write register.
MemtoReg: Choose write data of Register File from ALU result or data in memory.
MemtoReg = 0: choose ALU result .
MemtoReg = 1: choose data in DataMemory.
SignZero: extended zero or extended sign
SignZero = 0: extended sign.
SignZero = 1: extended zero.
ALUop:
choose type of operand for ALU: LW and SW(00), BNE(01), R-format
(10) and XORI (11).
Truth table
R-format
0
0
0
0
0
0
0
1
0
0
1
0
0

LW
1
0
0
0
1
1
0
0
1
1
1
1
0

SW
1
0
1
0
1
1
0
X
1
X
0
0
1

BNE
0
0
0
1
0
1
0
X
0
X
0
0
0

Jump
0
0
0
0
1
0
1
X
X
X
0
0
0

XORI
0
0
1
1
1
0
0
0
1
0
1
0
0

Lab3:Design a MIPS 32-bit Single-Cycle CPU


Branch
ALUop
SignZero

0
10
x

0
00
0

0
00
0

1
01
0

X
XX
x

0
11
1

Verilog code:

1 //Control//
2 module
control(ALUOp, RegDst, Branch, MemtoReg, MemRead,
MemWrite, ALUSrc, RegWrite, Jump, SignEx, Opcode);
3 output [1:0] ALUOp;
4 output RegDst, Branch, MemtoReg, MemRead, MemWrite, ALUSrc,
RegWrite, Jump, SignEx;
5 input [5:0] Opcode;
6
7 wire [5:0] n_Opcode;
8 wire
tmp_RegDst,tmp_MemtoReg,tmp_MemRead,tmp_MemWrite,tmp_Branch,tmp_
Jump;
9 wire [5:0]tmp_ALUSrc,tmp_RegWrite,tmp_SignEx;
10 wire [3:0] tmp_ALUOp0, tmp_ALUOp1;
11
12 not #50 not0(n_Opcode[0], Opcode[0]),
13
not1(n_Opcode[1], Opcode[1]),
14
not2(n_Opcode[2], Opcode[2]),
15
not3(n_Opcode[3], Opcode[3]),
16
not4(n_Opcode[4], Opcode[4]),
17
not5(n_Opcode[5], Opcode[5]);
18 //RegDst
19 and #50 and0(tmp_RegDst, n_Opcode[0], n_Opcode[1],
n_Opcode[2], n_Opcode[3]),
20
and1(RegDst,tmp_RegDst, n_Opcode[4],
n_Opcode[5]);
21 //ALUSrc
22 and #50 and2(tmp_ALUSrc[0], Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),
23
and3(tmp_ALUSrc[1], tmp_ALUSrc[0], n_Opcode[4],
Opcode[5]),
24
and4(tmp_ALUSrc[2], Opcode[0], Opcode[1],
n_Opcode[2], Opcode[3]),
25
and5(tmp_ALUSrc[3], tmp_ALUSrc[2], n_Opcode[4],
Opcode[5]),
26
and6(tmp_ALUSrc[4], n_Opcode[0], Opcode[1],
Opcode[2], Opcode[3]),
27
and7(tmp_ALUSrc[5], tmp_ALUSrc[4], n_Opcode[4],
n_Opcode[5]);
28 or #50
or0(ALUSrc,
tmp_ALUSrc[1],tmp_ALUSrc[3],tmp_ALUSrc[5]);
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Lab3:Design a MIPS 32-bit Single-Cycle CPU

29 //MemtoReg
30 and #50 and8(tmp_MemtoReg, Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),
31
and9(MemtoReg, tmp_MemtoReg, n_Opcode[4],
Opcode[5]);
32 //RegWrite
33 and #50 and10(tmp_RegWrite[0], n_Opcode[0], n_Opcode[1],
n_Opcode[2], n_Opcode[3]),
34
and11(tmp_RegWrite[1], tmp_RegWrite[0],
n_Opcode[4],n_Opcode[5]),
35
and12(tmp_RegWrite[2], Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),
36
and13(tmp_RegWrite[3], tmp_RegWrite[2],
n_Opcode[4],Opcode[5]),
37
and14(tmp_RegWrite[4], n_Opcode[0], Opcode[1],
Opcode[2], Opcode[3]),
38
and15(tmp_RegWrite[5], tmp_RegWrite[4],
n_Opcode[4],n_Opcode[5]);
39 or #50
or1(RegWrite, tmp_RegWrite[1], tmp_RegWrite[3],
tmp_RegWrite[5]);
40 //MemWrite
41 and #50 and16(tmp_MemWrite, Opcode[0], Opcode[1],
n_Opcode[2], Opcode[3]),
42
and17(MemWrite, tmp_MemWrite, n_Opcode[4],
Opcode[5]);
43 //MemRead
44 and #50
and18(tmp_MemRead, Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),
45
and19(MemRead, tmp_MemRead, n_Opcode[4],
Opcode[5]);
46 //Branch
47 and #50 and20(tmp_Branch, Opcode[0], n_Opcode[1],
Opcode[2], n_Opcode[3]),
48
and21(Branch, tmp_Branch, n_Opcode[4],
n_Opcode[5]);
49 //Jump
50 and #50 and22(tmp_Jump, n_Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),
51
and23(Jump, tmp_Jump, n_Opcode[4], n_Opcode[5]);
52 //SignEx
53 and #50 and24(tmp_SignEx[0], Opcode[0], n_Opcode[1],
Opcode[2], n_Opcode[3]),
54
and25(tmp_SignEx[1], tmp_SignEx[0], n_Opcode[4],
n_Opcode[5]),
55
and26(tmp_SignEx[2], Opcode[0], Opcode[1],
n_Opcode[2], n_Opcode[3]),

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Lab3:Design a MIPS 32-bit Single-Cycle CPU

56
and27(tmp_SignEx[3], tmp_SignEx[2], n_Opcode[4],
Opcode[5]),
57
and28(tmp_SignEx[4], Opcode[0], Opcode[1],
n_Opcode[2], Opcode[3]),
58
and29(tmp_SignEx[5], tmp_SignEx[4], n_Opcode[4],
Opcode[5]);
59 or #50 or2(SignEx, tmp_SignEx[1], tmp_SignEx[3],
tmp_SignEx[5]);
60 //ALUOp
61 and #50 and30(tmp_ALUOp1[0], n_Opcode[0], n_Opcode[1],
n_Opcode[2], n_Opcode[3]),
62
and31(tmp_ALUOp1[1], tmp_ALUOp1[0],
n_Opcode[4],n_Opcode[5]),
63
and32(tmp_ALUOp1[2], Opcode[0], n_Opcode[1],
Opcode[2], n_Opcode[3]),
64
and33(tmp_ALUOp1[3], tmp_ALUOp1[2],
n_Opcode[4],n_Opcode[5]);
65 or #50 or3(ALUOp[1], tmp_ALUOp1[1], tmp_ALUOp1[3]);
66 and #50 and34(tmp_ALUOp0[0], n_Opcode[0], n_Opcode[1],
n_Opcode[2], n_Opcode[3]),
67
and35(tmp_ALUOp0[1], tmp_ALUOp0[0],
n_Opcode[4],n_Opcode[5]),
68
and36(tmp_ALUOp0[2], n_Opcode[0], Opcode[1],
Opcode[2], Opcode[3]),
69
and37(tmp_ALUOp0[3], tmp_ALUOp0[2],
n_Opcode[4],n_Opcode[5]);
70 or #50 or4(ALUOp[0], tmp_ALUOp0[1], tmp_ALUOp0[3]);
71 endmodule
-

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Simulate on Quartus

Lab3:Design a MIPS 32-bit Single-Cycle CPU

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Lab3:Design a MIPS 32-bit Single-Cycle CPU


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Program Counter:
Meaning: PC register points to the next instruction.
Verilog code:

module D_FF (q, d, reset, clk);


output q;
input d, reset, clk;
reg q; // Indicate that q is stateholding
always @(posedge clk or posedge reset)
if (reset)
q = 0;
// On reset, set to 0
else
q = d; // Otherwise out = d
endmodule
//PCregister//
module PC_Register(PCout,PCin,reset,clk);
output [31:0] PCout;
input [31:0] PCin;
input reset,clk;
D_FF dff0(PCout[0],PCin[0],reset,clk);
D_FF dff1(PCout[1],PCin[1],reset,clk);
D_FF dff2(PCout[2],PCin[2],reset,clk);
D_FF dff3(PCout[3],PCin[3],reset,clk);
D_FF dff4(PCout[4],PCin[4],reset,clk);
D_FF dff5(PCout[5],PCin[5],reset,clk);
D_FF dff6(PCout[6],PCin[6],reset,clk);
D_FF dff7(PCout[7],PCin[7],reset,clk);
D_FF dff8(PCout[8],PCin[8],reset,clk);
D_FF dff9(PCout[9],PCin[9],reset,clk);
D_FF dff10(PCout[10],PCin[10],reset,clk);
D_FF dff11(PCout[11],PCin[11],reset,clk);
D_FF dff12(PCout[12],PCin[12],reset,clk);
D_FF dff13(PCout[13],PCin[13],reset,clk);
D_FF dff14(PCout[14],PCin[14],reset,clk);
D_FF dff15(PCout[15],PCin[15],reset,clk);
D_FF dff16(PCout[16],PCin[16],reset,clk);
D_FF dff17(PCout[17],PCin[17],reset,clk);
D_FF dff18(PCout[18],PCin[18],reset,clk);
D_FF dff19(PCout[19],PCin[19],reset,clk);
D_FF dff20(PCout[20],PCin[20],reset,clk);
D_FF dff21(PCout[21],PCin[21],reset,clk);
D_FF dff22(PCout[22],PCin[22],reset,clk);
D_FF dff23(PCout[23],PCin[23],reset,clk);
D_FF dff24(PCout[24],PCin[24],reset,clk);
D_FF dff25(PCout[25],PCin[25],reset,clk);
D_FF dff26(PCout[26],PCin[26],reset,clk);

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Lab3:Design a MIPS 32-bit Single-Cycle CPU

44 D_FF dff27(PCout[27],PCin[27],reset,clk);
45 D_FF dff28(PCout[28],PCin[28],reset,clk);
46 D_FF dff29(PCout[29],PCin[29],reset,clk);
47 D_FF dff30(PCout[30],PCin[30],reset,clk);
48 D_FF dff31(PCout[31],PCin[31],reset,clk);
49 endmodule

8.

1
2
3
4

Simulate on Quartus:

Verilog code:

Main:

//-------------main module--------//
module cpu(clk,reset);
input
clk,reset;

21 | P a g e

Lab3:Design a MIPS 32-bit Single-Cycle CPU


5
6
wire [31:0] PC, PCIn, PCIn1, PCIn2, PCIn3, PCplus4, Instruction,
ExImm, SL2Imm, JumpAdr, BranchAdr;
7
wire [31:0] ReadData1, ReadData2, RegWriteData, ALU2ndIn, ALUResult,
MemOutput;
8
wire [4:0] WriteRegister;
9
wire [1:0] ALUOp, ALUCtr;
10
wire CarryOut, zero, overflow, negative, nzero;
11
wire RegDst, Branch, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump,
SignEx, JumpReg, BranchSel;
12
wire Memclk, Regclk, PCInclk, PCclk;
13
14
15
16
assign PCclk = clk;
17
buf #10000 (Memclk, PCclk);
18
buf #1000 (Regclk, Memclk);
19
buf #10000 (PCInclk, PCclk);
20
21
PC_Register
PCInReg(PCIn, PCIn3, reset, PCInclk);
22
PC_Register
PCReg (PC, PCIn, reset, PCclk);
23
InstructionMem
InsMem(Instruction, PC);
24
regfile
Registers(ReadData1, ReadData2,
Instruction[25:21] ,Instruction[20:16], WriteRegister, RegWriteData,
RegWrite, reset, Regclk);
25
alu
ALU(ALUResult, zero, negative, overflow,
CarryOut, ReadData1, ALU2ndIn, ALUCtr);
26
dataMem
DataMem(MemOutput, ALUResult, ReadData2,
MemWrite, Memclk);
27
control
Ctrl(ALUOp, RegDst, Branch, MemtoReg, MemRead,
MemWrite, ALUSrc, RegWrite, Jump, SignEx, Instruction[31:26]);
28
ALUcontrol
ALUCtrl(ALUCtr, JumpReg, ALUOp, Instruction[5:0]);
29
extended
Ext(ExImm, Instruction[15:0], SignEx);
30
shift_left2
SL1(SL2Imm, ExImm);
31
shift_left2_jump SL2(JumpAdr[27:0], Instruction[25:0]);
32
AddCPU
Add1(PCplus4, PC, 32'h00000004);
33
AddCPU
Add2(BranchAdr, PCplus4, SL2Imm);
34
35
not #50 (nzero, zero);
36
and #50 (BranchSel, Branch, nzero);
37
assign JumpAdr[31:28] = PCplus4[31:28];
38
39
mux2to1_5bits
RegDstMux(WriteRegister, Instruction[20:16],
Instruction[15:11], RegDst);
40
mux2to1_32bits
ALUSrcMux(ALU2ndIn, ReadData2, ExImm, ALUSrc);
41
mux2to1_32bits
MemtoRegMux(RegWriteData, ALUResult, MemOutput,
MemtoReg);
42
mux2to1_32bits
BraSelMux(PCIn1, PCplus4, BranchAdr, BranchSel);
43
mux2to1_32bits
JumpMux(PCIn2, PCIn1, JumpAdr, Jump);
44
mux2to1_32bits
JumpRegMux(PCIn3, PCIn2, ReadData1, JumpReg);
45
46
47
endmodule

22 | P a g e

Simulate on Quartus

Lab3:Design a MIPS 32-bit Single-Cycle CPU

23 | P a g e

Lab3:Design a MIPS 32-bit Single-Cycle CPU


IV.

24 | P a g e

Simulating: