Tips on DRC and LVS (Cadence)

DRC:
1. To run DRC go to VerifyDRC
A new window will open:

Click OK and wait.

2. After DRC is done the CIW window will give the results:
If everything is OK you should see this:

If you have errors you will see them listed:

3. To find the errors go back to the layout editor. The errors are indicated with markers:

4. To find out which error means what go to VerifyMarkersExplain. Then go back to

your layout and click on a marker. A new window will list the location and type of error:

If your layout is big and you dont see all the markers use VerifyMarkersFind. Every
time you click on Apply you will move to a new error and the marker will be highlighted.
LVS:
1. Make sure your design is DRC clean
2. Save all cellviews.
3. Go to VerifyExtract and extract the layout. Check for errors in the CIW
window.
4. Go to VerifyLVS. You should see this window:

Fill the schematic and extracted fields with the name of the library, the name of the
cell and the view type (see the figure above). Some of the fields will be filled by default.
5. Click Run. Wait. After some time you should see this:

Succeeded means that LVS was completed. It still does NOT mean that your cell has
passed LVS.
6. Click Output in the LVS form to see the results. If you are lucky you will see this:

If you are less lucky you will have to proceed to Error Display.
In this particular case the well contact (NTAP) of the PMOS transistor in the inverter was
removed and LVS had to merge the well with the vdd! line in order to match the layout
and the schematic. (NOTE: Dont forget to put substrate and well contacts in each cell!)

The errors are also highlighted in the Extracted view.

Note however that most of the time the error explanations are not very obvious. The best
approach in general is to break up your design into many hierarchical levels and proceed
to a higher level only after all the lower-level cells have passed LVS.