Dsp programs:

1. Implementing a For Loop

2. Factorial of a number using For Loop
3. Generation of Sine Wave
4. Generation of Square wave
5. Generating a Triangular wave
6. Acquisition of signal from ADC
7. Delay routine
8. Initializing the event manager
9. GPIO
10.Interfacing an Led
11.Generation of PWM

1) Implementing a For Loop:

unsigned int k;
void main(void)
{
unsigned int i;
while(1)
{
for(i=0; i<100; i++)
k=i*i;
}
}

2) Factorial of a number using For Loop:

#include<stdio.h>
int main()
{
int input,i,result=1;
printf("please input a Integer: ");
scanf("%d",&input);
for(i=input;i>0;i--){
result=result*i;

}
printf("the factorial of %d is %d\n",input,result);
}

3) Generating a Triangular wave:

#include <stdio.h>
#include <math.h>
void main()
{
int *Triangle;
int i=0,j=0;
Triangle = (int*)0xC0000000;
while(1)
{
for(i=0;i<50;i++)
{
j=j+1;
*Triangle++ = j;
}
for(i=50;i>0;i--)
{
j=j-1;
*Triangle++ = j;
}
}
}
4) Generation of Square wave:
# include<stdio.h>
#include<math.h>
void main()
{
int *square;
int i;
square =(int*)0xC0000000;
while(1)
{
for(i=0;i<50;i++)
{
*square++=0x0000FFFF;
}

for(i=0;i<50;i++)
{
*square++=0x0;
}
}
}
5) Generation of Sine Wave
#include<stdio.h>
#include<math.h>
#define PI 3.14
void main()
{
const float sampf = 1024000.0;// Sampling frquency is fixed
const int inpf = 4000; // change the input frquency from 1khz to 8khz(1000 to
8000)
float sampt;
double teta;
short value,*sinout;
int i,count,nsamp,value1;
sinout = (short *)0xc0000000;
sampt = 1/sampf;
nsamp = sampf/inpf;
printf("\n Sampling Frequency is : %f",sampf);
printf("\n Sampling Time is :%f",sampt);
printf("\n Input Frequency is : %d",inpf);
printf("\n The number of Sample is : %d",nsamp);
for(i=0;i<400;i++)
*(sinout+i)=0;
for(count=0;count<nsamp;count++)
{
teta = (2 * PI * inpf * sampt * count);
printf("\nteta = %lf",teta);
value = sin(teta)*1024;
printf("\t sin %lf Value is : %d",teta,value);
value1 = value&0x0000FFFF;
*sinout++ = value1;
}
}

6) Acquisition of signal from ADC:

#include "F2812_example.h"

// Main include file

* Function: InitAdc()
*
* Description: Initializes the ADC on the F281x.
void InitAdc(void)
{
//--- Must follow the proper ADC power-up sequence
AdcRegs.ADCTRL3.all = 0x00C8;
// first power-up ref and bandgap circuits
// bit 15-8
0's: reserved
// bit 7
1:
ADCRFDN, reference power, 1=power on
// bit 6
1:
ADCBGDN, bandgap power, 1=power on
// bit 5
0:
ADCPWDN, main ADC power, 1=power on
// bit 4-1
0100: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
// bit 0
0:
SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
DelayUs(10000);
ADCPWDN
AdcRegs.ADCTRL3.bit.ADCPWDN = 1;
DelayUs(1000);

// Wait 10 ms before setting

// Set ADCPWDN=1 to power main ADC
// Wait 1 ms before using the ADC

//--- Configure the other ADC registers

AdcRegs.ADCMAXCONV.all = 0x0000;
// bit 15-7
0's: reserved
// bit 6-4
000: MAX_CONV2 value
// bit 3-0
0000: MAX_CONV1 value (0 means 1 conversion)
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;

// Convert Channel 0

AdcRegs.ADCTRL1.all = 0x0710;
// bit 15
0:
reserved
// bit 14
0:
RESET, 0=no action, 1=reset ADC
// bit 13-12 00: SUSMOD, 00=ignore emulation suspend
// bit 11-8
0111: ACQ_PS (Acquisition), 0111 = 8 x ADCCLK
// bit 7
0:
CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
// bit 6
0:
CONT_RUN, 0=start/stop mode, 1=continuous run
// bit 5
0:
SEQ_OVRD, 0=disabled, 1=enabled
// bit 4
1:
SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
// bit 3-0
0000: reserved

// bit 15
// bit 14
// bit 13
// bit 12
// bit 11
// bit 10
// bit 9
// bit 8
// bit 7

AdcRegs.ADCTRL2.all = 0x0900;
0:
EVB_SOC_SEQ, 0=no action
0:
RST_SEQ1, 0=no action
0:
SOC_SEQ1, 0=clear any pending SOCs
0:
reserved
1:
INT_ENA_SEQ1, 1=enable interrupt
0:
INT_MOD_SEQ1, 0=int on every SEQ1 conv
0:
reserved
1:
EVA_SOC_SEQ1, 1=SEQ1 start from EVA
0:
EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin

// bit 6
// bit 5
// bit 4
// bit 3
// bit 2
// bit 1
// bit 0

0:
0:
0:
0:
0:
0:
0:

RST_SEQ2, 0=no action

SOC_SEQ2, no effect in cascaded mode
reserved
INT_ENA_SEQ2, 0=int disabled
INT_MOD_SEQ2, 0=int on every other SEQ2 conv
reserved
EVB_SOC_SEQ2, 1=SEQ2 started by EVB

//--- Enable the ADC interrupt

PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
IER |= 0x0001;
PIE group

// Enable ADCINT in PIE group 1

// Enable INT1 in IER to enable

} // end InitAdc()

7) Delay Routine:
.def _DelayUs
.text
_DelayUs:
MOVB AH, #0
PUSH ST1
DelayUs1:

;Zero AH
;Save ST1 to preserve EALLOW setting
;Outer loop

;Service the watchdog in case it is active

EALLOW
MOVZ DP, #(WDKEY>>6)
MOV @WDKEY, #0x0055
MOV @WDKEY, #0x00AA
EDIS
;Proceed with the inner loop
RPT #138
;Inner loop
|| NOP
SUBB ACC,#1
BF DelayUs1, GT
;Finish up
POP ST1
LRETR

;Decrement outer loop counter

;Branch for outer loop

;Restore ST1
;Return

;end of function DelayUs()

**********************************************************************

.end
;end of file DelayUs.asm
8) Initializing the Event Manager:

**********************************************************************/
#include "F2812_example.h"
// Main include file

/**********************************************************************
* Function: InitEv()
*
* Description: Initializes the Event Managers on the F281x.
**********************************************************************/
void InitEv(void)
{
//------------------------------------------------------------//--- General Setup
//------------------------------------------------------------EvaRegs.EXTCONA.all = 0x0001;
// bit 15-4
0's: reserved
// bit 3
0:
EVSOCE, 0 = disable EV start of ADC conversion output
// bit 2
0:
QEPIE, 0 = disable CAP3_QEPI as index input
// bit 1
0:
QEPIQUAL, 0 = CAP3_QEPI qual disabled
// bit 0
1:
INDCOE, 1 = independent compare enable
EvbRegs.EXTCONB.all = 0x0001;
// bit 15-4
0's: reserved
// bit 3
0:
EVSOCE, 0 = disable EV start of ADC conversion output
// bit 2
0:
QEPIE, 0 = disable CAP6_QEPI as index input
// bit 1
0:
QEPIQUAL, 0 = CAP6_QEPI qual disabled
// bit 0
1:
INDCOE, 1 = independent compare enable
//--- Disable and clear all event manager interrupts
EvaRegs.EVAIMRA.all = 0x0000;
EvaRegs.EVAIMRB.all = 0x0000;
EvaRegs.EVAIMRC.all = 0x0000;
EvaRegs.EVAIFRA.all = 0xFFFF;
EvaRegs.EVAIFRB.all = 0xFFFF;
EvaRegs.EVAIFRC.all = 0xFFFF;

// Disable all EVA group A interrupts

// Disable all EVA group B interrupts
// Disable all EVA group C interrupts
// Clear all EVA group A interrupts
// Clear all EVA group B interrupts
// Clear all EVA group C interrupts

EvbRegs.EVBIMRA.all = 0x0000;
EvbRegs.EVBIMRB.all = 0x0000;
EvbRegs.EVBIMRC.all = 0x0000;
EvbRegs.EVBIFRA.all = 0xFFFF;

// Disable all EVB group A interrupts

// Disable all EVB group B interrupts
// Disable all EVB group C interrupts
// Clear all EVB group A interrupts

EvbRegs.EVBIFRB.all = 0xFFFF;
EvbRegs.EVBIFRC.all = 0xFFFF;

// Clear all EVB group B interrupts

// Clear all EVB group C interrupts

//--- Configure the GPTCONA register

EvaRegs.GPTCONA.all = 0x0400;
// bit 15
0:
reserved
// bit 14
0:
T2STAT, read-only
// bit 13
0:
T1STAT, read-only
// bit 12
0:
T2CTRIPE, 0=disable timer2 compare trip
// bit 11
0:
T1CTRIPE, 0=disable timer1 compare trip
// bit 10-9
10: T2TOADC, 10 = timer2 period flag starts ADC
// bit 8-7
00: T1TOADC, 00 = timer1 does not start ADC
// bit 6
0:
TCOMPOE, 0 = Hi-z all timer compare outputs
// bit 5
0:
T2COMPOE, 0 = timer2 compare HI-z'd
// bit 4
0:
T1COMPOE, 0 = timer1 compare HI-z'd
// bit 3-2
00: T2PIN, 00 = forced low
// bit 1-0
00: T1PIN, 00 = forced low

//------------------------------------------------------------//--- Configure Timer 2 to trigger the ADC at a 50 kHz rate

//------------------------------------------------------------EvaRegs.T2CON.all = 0x0000;
// Disable timer
EvaRegs.T2CNT = 0x0000;
// Clear timer counter
EvaRegs.T2PR = ADC_SAMPLE_PERIOD;
// Set timer period
EvaRegs.T2CON.all = 0xD040;
//enable timer
// bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend
// bit 13
0:
reserved
// bit 12-11 10: TMODEx, 10 = continuous-up count mode
// bit 10-8
000: TPSx, 000 = x/1 prescaler
// bit 7
0:
T2SWT1, 0 = use own TENABLE bit
// bit 6
1:
TENABLE, 1 = enable timer
// bit 5-4
00: TCLKS, 00 = HSPCLK is clock source
// bit 3-2
00: TCLD, 00 = reload compare reg on underflow
// bit 1
0:
TECMPR, 0 = enable timer compare
// bit 0
0:
SELT1PR, 0 = use own period register

//------------------------------------------------------------//--- Configure Timer 1 for 2 kHz symmetric PWM on PWM1 pin

//------------------------------------------------------------EvaRegs.T1CON.all = 0x0000;
// Disable timer
EvaRegs.T1CNT = 0x0000;
// Clear timer counter
EvaRegs.T1PR = PWM_HALF_PERIOD;
// Set timer period
EvaRegs.DBTCONA.all = 0x0000;
// Deadband units off

EvaRegs.CMPR1 = PWM_DUTY_CYCLE;

// Set PWM1 duty cycle

EvaRegs.ACTRA.all = 0x0002;
// PWM1 set for active high
// bit 15
0:
SVDIR, space vector dir is CCW (don't care)
// bit 14-12 000: D2-D0, basic space vector is 000 (dont' care)
// bit 11-10 00: CMP6ACTx, PWM6/GPIOA5 pin forced low
// bit 9-8
00: CMP5ACTx, PWM5/GPIOA4 pin forced low
// bit 7-6
00: CMP4ACTx, PWM4/GPIOA3 pin forced low
// bit 5-4
00: CMP3ACTx, PWM3/GPIOA2 pin forced low
// bit 3-2
00: CMP2ACTx, PWM2/GPIOA1 pin forced low
// bit 1-0
10: CMP1ACTx, PWM1/GPIOA0 pin active high
EvaRegs.COMCONA.all = 0x8221;
// Init COMCONA
// bit 15
1:
CENABLE, 1 = enable full compare operation
// bit 14-13 00: CLDx, 00 = reload CMPRx regs on timer 1 underflow
// bit 12
0:
SVENABLE, 0 = space vector disabled
// bit 11-10 00: ACTRLDx, 00 = reload ACTR on timer 1 underflow
// bit 9
1:
FCMPOE, 1 = enable PWM pins
// bit 8
0:
PDPINT, PDPINT status (read-only)
// bit 7
0:
FCMP3OE, compare 3 enable (1=enable)
// bit 6
0:
FCMP2OE, compare 2 enable (1=enable)
// bit 5
1:
FCMP1OE, compare 1 enable (1=enable)
// bit 4-3
00: reserved
// bit 2
0:
C3TRIPE, compare 3 trip enable (1=enable)
// bit 1
0:
C2TRIPE, compare 2 trip enable (1=enable)
// bit 0
1:
C1TRIPE, compare 1 trip enable (1=enable)
EvaRegs.T1CON.all = 0xC840;
// Init T1CON, enable timer
// bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend
// bit 13
0:
reserved
// bit 12-11 01: TMODEx, 01 = continous-up/down count mode
// bit 10-8
000: TPSx, 000 = x/1 prescaler
// bit 7
0:
T2SWT1, 0 = use own TENABLE bit
// bit 6
1:
TENABLE, 1 = enable timer
// bit 5-4
00: TCLKS, 00 = CPUCLK is clock source
// bit 3-2
00: TCLD, 00 = reload compare reg on underflow
// bit 1
0:
TECMPR, 0 = disable timer compare
// bit 0
0:
SELT1PR, 0 = use own period register

//------------------------------------------------------------//--- Setup Capture unit 1

//------------------------------------------------------------EvaRegs.CAPCONA.bit.CAPRES = 0;

// reset the capture units and registers

EvaRegs.CAPCONA.all = 0xA2C0;
// Init CAPCONA register
// bit 15
1:
CAPRES, 1 = no action
// bit 14-13 01: CAP12EN, 01 = enable CAP1 and CAP2, QEP disabled
// bit 12
0:
CAP3EN, 0 = disable CAP3
// bit 11
0:
reserved
// bit 10
0:
CAP3TSEL, CAP3 uses:
0=timer2, 1=timer1
// bit 9
1:
CAP12TSEL, CAP1 and CAP2 use: 0=timer2, 1=timer1
// bit 8
0:
CAP3TOADC, 0 = CAP3 does not start ADC
// bit 7-6
11: CAP1EDGE, 11 = CAP1 detects both rising and falling edges
// bit 5-4
00: CAP2EDGE, 00 = CAP2 no detection
// bit 3-2
00: CAP3EDGE, 00 = CAP3 no detection
// bit 1-0
00: reserved
EvaRegs.EVAIMRC.bit.CAP1INT = 1;
// Enable CAPINT1
PieCtrlRegs.PIEIER3.bit.INTx5 = 1; // Enable CAPINT1 in PIE group 3
IER |= 0x0004;
// Enable INT3 in IER to
enable PIE group 3
} // end InitEv()

//--- end of file -----------------------------------------------------

9) GPIO:
**********************************************************************/
#include "F2812_example.h"
// Main include file

/**********************************************************************
* Function: InitGpio()
*
* Description: Initializes the shared GPIO pins on the F281x.
**********************************************************************/
void InitGpio(void)
{
asm(" EALLOW");
// Enable EALLOW protected
register access
//--- Group A pins
GpioMuxRegs.GPAQUAL.all=0x0000;
GpioMuxRegs.GPADIR.all = 0x0000;
GpioMuxRegs.GPAMUX.bit.C3TRIP_GPIOA15 = 0;
GpioMuxRegs.GPAMUX.bit.C2TRIP_GPIOA14 = 0;
GpioMuxRegs.GPAMUX.bit.C1TRIP_GPIOA13 = 0;
GpioMuxRegs.GPAMUX.bit.TCLKINA_GPIOA12 = 0;
GpioMuxRegs.GPAMUX.bit.TDIRA_GPIOA11 = 0;

// Input qualifier disabled

// All group A GPIO are inputs
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function

GpioMuxRegs.GPAMUX.bit.CAP3QI1_GPIOA10 = 0;
GpioMuxRegs.GPAMUX.bit.CAP2Q2_GPIOA9 = 0;
GpioMuxRegs.GPAMUX.bit.CAP1Q1_GPIOA8 = 1;
GpioMuxRegs.GPAMUX.bit.T2PWM_GPIOA7 = 0;
GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 0;
GpioMuxRegs.GPAMUX.bit.PWM6_GPIOA5 = 0;
GpioMuxRegs.GPAMUX.bit.PWM5_GPIOA4 = 0;
GpioMuxRegs.GPAMUX.bit.PWM4_GPIOA3 = 0;
GpioMuxRegs.GPAMUX.bit.PWM3_GPIOA2 = 0;
GpioMuxRegs.GPAMUX.bit.PWM2_GPIOA1 = 0;
GpioMuxRegs.GPAMUX.bit.PWM1_GPIOA0 = 1;
//--- Group B pins
GpioMuxRegs.GPBQUAL.all = 0x0000;
GpioMuxRegs.GPBDIR.all = 0x0000;
GpioMuxRegs.GPBMUX.bit.C6TRIP_GPIOB15 = 0;
GpioMuxRegs.GPBMUX.bit.C5TRIP_GPIOB14 = 0;
GpioMuxRegs.GPBMUX.bit.C4TRIP_GPIOB13 = 0;
GpioMuxRegs.GPBMUX.bit.TCLKINB_GPIOB12 = 0;
GpioMuxRegs.GPBMUX.bit.TDIRB_GPIOB11 = 0;
GpioMuxRegs.GPBMUX.bit.CAP6QI2_GPIOB10 = 0;
GpioMuxRegs.GPBMUX.bit.CAP5Q2_GPIOB9 = 0;
GpioMuxRegs.GPBMUX.bit.CAP4Q1_GPIOB8 = 0;
GpioMuxRegs.GPBMUX.bit.T4PWM_GPIOB7 = 0;
GpioMuxRegs.GPBMUX.bit.T3PWM_GPIOB6 = 0;
GpioMuxRegs.GPBMUX.bit.PWM12_GPIOB5 = 0;
GpioMuxRegs.GPBMUX.bit.PWM11_GPIOB4 = 0;
GpioMuxRegs.GPBMUX.bit.PWM10_GPIOB3 = 0;
GpioMuxRegs.GPBMUX.bit.PWM9_GPIOB2 = 0;
GpioMuxRegs.GPBMUX.bit.PWM8_GPIOB1 = 0;
GpioMuxRegs.GPBMUX.bit.PWM7_GPIOB0 = 0;
//--- Group D pins
GpioMuxRegs.GPDQUAL.all=0x0000;
GpioMuxRegs.GPDDIR.all = 0x0000;

// 0: select GPIO function

// 0: select GPIO function
// 1: select periph function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 1: select periph function

// Input qualifier disabled

// All group B GPIO are inputs
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function

// Input qualifier disabled

// All group D GPIO are inputs

GpioMuxRegs.GPDMUX.bit.T4CTRIP_SOCB_GPIOD6 = 0; // 0: select GPIO function

GpioMuxRegs.GPDMUX.bit.T3CTRIP_PDPB_GPIOD5 = 0; // 0: select GPIO function
GpioMuxRegs.GPDMUX.bit.T2CTRIP_SOCA_GPIOD1 = 0; // 0: select GPIO function
GpioMuxRegs.GPDMUX.bit.T1CTRIP_PDPA_GPIOD0 = 0; // 0: select GPIO function
//--- Group E pins
GpioMuxRegs.GPEQUAL.all=0x0000;
GpioMuxRegs.GPEDIR.all = 0x0000;

// Input qualifier disabled

// All group E GPIO are inputs

GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2 = 0; // 0: select GPIO function

GpioMuxRegs.GPEMUX.bit.XINT2_ADCSOC_GPIOE1 = 0; // 0: select GPIO function
GpioMuxRegs.GPEMUX.bit.XINT1_XBIO_GPIOE0 = 0; // 0: select GPIO function
//--- Group F pins
GpioMuxRegs.GPFDIR.all = 0x0000;
GpioMuxRegs.GPFMUX.bit.XF_GPIOF14
= 0;
GpioMuxRegs.GPFMUX.bit.MDRA_GPIOF13 = 0;

// All group F GPIO are inputs

// 0: select GPIO function
// 0: select GPIO function

GpioMuxRegs.GPFMUX.bit.MDXA_GPIOF12 = 0;
GpioMuxRegs.GPFMUX.bit.MFSRA_GPIOF11 = 0;
GpioMuxRegs.GPFMUX.bit.MFSXA_GPIOF10 = 0;
GpioMuxRegs.GPFMUX.bit.MCLKRA_GPIOF9 = 0;
GpioMuxRegs.GPFMUX.bit.MCLKXA_GPIOF8 = 0;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 0;
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 0;
GpioMuxRegs.GPFMUX.bit.SCIRXDA_GPIOF5 = 0;
GpioMuxRegs.GPFMUX.bit.SCITXDA_GPIOF4 = 0;
GpioMuxRegs.GPFMUX.bit.SPISTEA_GPIOF3 = 0;
GpioMuxRegs.GPFMUX.bit.SPICLKA_GPIOF2 = 0;
GpioMuxRegs.GPFMUX.bit.SPISOMIA_GPIOF1 = 0;
GpioMuxRegs.GPFMUX.bit.SPISIMOA_GPIOF0 = 0;
GpioMuxRegs.GPFDIR.bit.GPIOF14 = 1;
to LED on eZdsp)
GpioDataRegs.GPFSET.bit.GPIOF14 = 1;
//--- Group G pins
GpioMuxRegs.GPGDIR.all = 0x0000;
GpioMuxRegs.GPGMUX.bit.SCIRXDB_GPIOG5 = 0;
GpioMuxRegs.GPGMUX.bit.SCITXDB_GPIOG4 = 0;
//--- Finish up
asm(" EDIS");
access

// 0: select GPIO function

// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 0: select GPIO function
// 1: GPIOF14 is output (connected
// 1: set GPIOF14 (turn LED on)

// All group G GPIO are inputs

// 0: select GPIO function
// 0: select GPIO function

// Disable EALLOW protected register

} // end InitGpio()

//--- end of file -----------------------------------------------------

10) Interfacing an LED:

#include "DSP281x_Device.h"
#include <stdio.h>
void Delay_1ms(long);
void main(void)
{
EALLOW;
SysCtrlRegs.WDCR= 0x0068; // Setup the watchdog
// 0x0068 to disable
the Watchdog , Prescaler = 1
// 0x00AF to NOT disable the Watchdog, Prescaler = 64
SysCtrlRegs.SCSR = 0;
// Watchdog generates a RESET

SysCtrlRegs.PLLCR.bit.DIV = 10;

// Setup the Clock PLL to multiply by 5

SysCtrlRegs.HISPCP.all = 0x1;
// Setup Highspeed Clock Prescaler to divide by 2
SysCtrlRegs.LOSPCP.all = 0x2;
// Setup Lowspeed CLock Prescaler to divide by 4
GpioMuxRegs.GPAMUX.all = 0x0; // all GPIO port Pin's to I/O
GpioMuxRegs.GPBMUX.all = 0x0;
GpioMuxRegs.GPADIR.all = 0x0; // GPIO PORT as input
GpioMuxRegs.GPBDIR.all = 0x00FF;
// GPIO Port B15-B8 input , B7-B0 output
EDIS;
while(1)
{
GpioDataRegs.GPBDAT.all = 0xFF;
Delay_1ms(1000);
//value 1000 for one second delay
GpioDataRegs.GPBDAT.all = 0x0;
Delay_1ms(1000);
}
}
void Delay_1ms(long end)
{
long i;
for (i = 0; i <(9000 * end); i++);
}

//value 1000 for one second delay

11) Generation of PWM

#include "DSP281x_Device.h" // DSP281x Headerfile Include File

#include "DSP281x_Examples.h" // DSP281x Examples Include File
// Prototype statements for functions found within this
file.
void InitSystem(void);
void main(void)
{
InitSystem();
EALLOW;
GpioMuxRegs.GPAMUX.all = 0x01FF; // EVA PWM 1-6 pins
GpioMuxRegs.GPBMUX.all = 0x00FF; // EVB PWM 7-12 pins
EDIS;
DINT;
EvaRegs.T1PR = 0xF424;
// Timer1 period
EvaRegs.T1CMPR = 0x7A12; // Timer1 compare
EvaRegs.T1CNT = 0x0000;
// Timer1 counter

EvaRegs.T1CON.all = 0x1042;
// TMODE = continuous up & Timer enable
EvaRegs.T2PR = 0xF424;
// Timer2 period
EvaRegs.T2CMPR = 0x7A12; // Timer2 compare
EvaRegs.T2CNT = 0x0000;
// Timer2 counter
EvaRegs.T2CON.all = 0x1042;
EvaRegs.GPTCONA.bit.TCMPOE = 1;
// Drive T1/T2 PWM by compare logic
EvaRegs.GPTCONA.bit.T1PIN = 1; // Polarity of GP Timer 1 Compare = Active low
EvaRegs.GPTCONA.bit.T2PIN = 2; // Polarity of GP Timer 2 Compare = Active high
EvaRegs.CMPR1 = 0x7A12;
// Enable compare for PWM1-PWM6
EvaRegs.CMPR2 = 0x7A12;
EvaRegs.CMPR3 = 0x7A12;
EvaRegs.ACTRA.all = 0x0666;
EvaRegs.DBTCONA.all = 0x0530; // Disable deadband
EvaRegs.COMCONA.all = 0xA600;
EvaRegs.CAPCONA.bit.CAPRES = 0; // reset all capture regs to zero
EvaRegs.CAPCONA.all = 0x2240; // enable CAP1, selcting gp timer 1 & detecting rising
edge
EvaRegs.CAPFIFOA.all = 0x0100;
for(;;);
}
void InitSystem(void)
{
EALLOW;
SysCtrlRegs.WDCR= 0x0068;
// Setup the watchdog
// 0x00E8 to disable the Watchdog , Prescaler = 1
// 0x00AF to NOT disable the Watchdog, Prescaler
= 64
SysCtrlRegs.SCSR = 0;
// Watchdog generates a RESET
SysCtrlRegs.PLLCR.bit.DIV = 10;
// Setup the Clock PLL to multiply by 5
SysCtrlRegs.HISPCP.all = 0x1; // Setup Highspeed Clock Prescaler to divide by 2
SysCtrlRegs.LOSPCP.all = 0x2; // Setup Lowspeed CLock Prescaler to divide by 4
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;
SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;
SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;
SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;
SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;
SysCtrlRegs.PCLKCR.bit.ECANENCLK=0;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;

EDIS;
}