Gerfel Philip C.

Gonzales
Homework Number 1
1. Name the different masks in a standard CMOS process. Briefly describe each mask.
(From the Powerpoint Source)
Mask 1 -- N-well (for N-well ion implantation phosphorus)
Mask 2 -- P - well (for P-well ion implantation boron)
Mask 3 -- Shallow Trench Isolation
Mask 4 -- P-well Vt Adjust (for P-well Vt adjust implantation phosphorus)
Mask 5 -- N-well Vt Adjust (for N-well Vt adjust implantation boron)
Mask 6 -- Gate and Local Interconnection (Polysilicon gate)
Mask 7 -- N-channel LDD (N-type LDD implantation Arsenic)
Mask 8 -- N-channel Source/Drain (for N+ source/drain implantation phosphorus)
Mask 9 -- P-channel Source/Drain (for P-channel source/drain implantation boron)
Mask 10 -- Contact Holes (Deposit tungsten for interconnection)
Mask 11 -- Metal 1 Interconnects
Mask 12 -- Via Holes (Deposit tungsten)
Mask 13 -- Metal 2 Interconnects
Mask 13 -- Bonding Pad

2. How many masks are intended for ion implantation?

7
3. How many masks are intended for the interconnections?
5
4. Differentiate thermal oxidation and chemical vapor deposition.
In chemical vapor deposition, a process that allows the reaction of gasses
that produces a solid material and then it is deposited on the surface of the
substrate.
In thermal oxidation, the substrate undergoes simple oxidation, a direct
reaction of the substrate and oxygen that produces oxides on the surface.
5. Assuming that each process of the standard CMOS has an efficiency of 99%. What is
the yield rate?
Yield Rate = 0.99