Chapter05 BoNho

dce
2013
COMPUTER ARCHITECTURE
CSE Fall 2013
BK
TP.HCM
Faculty of Computer Science and

Engineering
Department of Computer Engineering
Vo Tan Phuong
http://www.cse.hcmut.edu.vn/~vtphuong
dce
2013
Chapter 5
B nh my tnh
Computer Architecture Chapter 5
Fall 2013, CS
dce
2013
Ni dung trnh by
Cng ngh v thut ng lin quan n b nh
T chc / thit k b nh
S cn thit phi c b nh m
Phn loi b nh m
nh gi hiu nng ca b nh m
Fall 2013, CS
dce
2013
My tnh PC
Nhn t bn ngoi, b
x l kt ni vi RAM
v chip cu bc (qun
l cc kt ni vo bus
tc cao nh card
ha, khe PCI), chip cu
bc ni vi chip cu
nam (qun l USB bus,
network, cng,
CD)
RAM
Card
ha
CPU
RAM
Chip cu bc
Khe cm PCI
Chip
cu
nam
Fall 2013, CS
H thng b nh my tnh
B nh my tnh hiu
theo ngha rng l tt
c ni cha d liu
(thanh ghi, b nh
m, b nh chnh, b
nh ngoi)
H thng b nh t
chc theo m hnh
phn cp, trn cng l
b thanh ghi, n b
nh m L1, L2, b
nh chnh, b nh ph
Processor
Control
Devices
Memory
Datapath
Input
Output
Microprocessor
Registers
L1 Cache
L2 Cache
Memory Bus
Bigger
2013
Faster
dce
Main Memory
I/O Bus
Magnetic or Flash Disk
Fall 2013, CS
H thng b nh phn cp trong Pipline

MIPS CPU
Imm
RW
Rd
0
1
A
L
U
BusB
BusW
32
0
1
2
3
1
0
ALUout
D-Cache
Address
32
Data_out
WB Data
RB
BusA
32
Data_in
32
Rd4
Address
Rt 5
RA
ALU result 32
PC
Instruction
Rs 5
Register File
I-Cache
Instruction
0
1
Rd3
Imm16
2013
Rd2
dce
Data Block
D-Cache miss
I-Cache miss hoc D-Cache miss

lm qu trnh pipeline b stall
Block Address
Instruction Block
I-Cache miss
Block Address
clk
Interface to L2 Cache or Main Memory
Fall 2013, CS
dce
Cu to thanh ghi
2013
Thanh ghi c thnh phn chnh l cc D Flip-Flop, c n bit

d liu vo, n bit d liu ra, tn hiu WE (Write Enable) v
tn hiu xung nhp Clock
Register
D
C
D
C
D0
D1
D Flip-Flop
Q
Data_In
Data_Out
.
.
.
32
D
C
D31
32
D Latch
WE
Clock
Fall 2013, CS
dce
Chi tit b thanh ghi
2013
B thanh ghi MIPS gm 32 thanh ghi 32 bit; RA, RB l 2 u vo yu

cu truy xut d liu, d liu c a ra BusA, BusB; ghi d liu
cn ch ra ni lu RW, gi tr lu BusW, yu cu ghi RegWrite v thi
im ghi c ng b vi xung nhp Clock
RA
Register
File BusA
32
RB
32
BusB
RW
Clock
BusW
RegWrite
32
Fall 2013, CS
dce
2013
B nh truy xut ngu nhin RAM

L mt mng 2n phn t nh, mi phn t nh lu tr
m-bit d liu
L b nh bc hi
D liu ch c lu khi cn c cung cp in
Truy xut ngu nhin

Thi gian truy xut d liu t mt phn t nh bt k l nh
nhau
Tn hiu iu khin Output Enable (OE)

Yu cu xut d liu khi c
Tn hiu iu khin Write Enable (WE)
RAM
Address
Data
m
OE
WE
Yu cu ghi d liu
2n m RAM : n-bit a ch, m-bit d liu

Fall 2013, CS
dce
2013
Cng ngh b nh
Static RAM (SRAM) dng cho b nh m
1 bit nh cn 6 transistor
Tc truy xut d liu cao (~ 1ns)
Cn t nng lng duy tr gi tr lu tr
Dynamic RAM (DRAM) dng cho b nh chnh

1 bit nh cn 1 transistor + 1 capacitor
Tc truy xut d liu thp (~ 100ns)

Cn phi ghi li gi tr vo nh sau khi c
Cn phi nh k lm ti
Mi hng c th c lm ti ng thi
Fall 2013, CS
10
dce
2013
Cu to SRAM
Fall 2013, CS
11
dce
2013
Cu to DRAM
Fall 2013, CS
12
dce
2013
M hnh bit nh ca DRAM

1 bit nh s dng t lm phn t lu tr
T c t tnh r in tch theo thi gian
Cn lm ti gi mc in th tng ng mc 1
Fall 2013, CS
13
dce
Chu k lm ti DRAM
2013
Chu k lm ti (refresh cycle) vo khong 10ms

Vic lm ti c thc hin cho ton b nh
Mi hng s c c v ghi tr li phc hi in tch
Bng thng b nh b gim bi vic lm ti
Voltage
for 1
1 Written
Refreshed
Refreshed
Refreshed
Threshold
voltage
Voltage
for 0
0 Stored
Refresh Cycle
Time
Fall 2013, CS
14
dce
V d mt IC DRAM
2013
24 chn, dng dual in-line cho b nh 16Mbit = 222 4

22-bit a ch bao gm
Ch thch:
11-bit row address

11-bit column address
a ch hng v ct dng chung
11 ng a ch A0-A10
Ai
CAS
Dj
NC
OE
RAS
WE
Address bit i
Column address strobe
Data bit j
No connection
Output enable
Row address strobe
Write enable
Vss D4 D3 CAS OE A9 A8 A7 A6 A5 A4 Vss

24 23 22 21 20 19 18 17 16 15 14 13
10 11
12
Vcc D1 D2 WE RAS NC A10 A0 A1 A2 A3 Vcc

Fall 2013, CS
15
dce
2013
V d cu trc ca DRAM
La chn ct c/ghi
...
Column decoder
Row Decoder
La chn hng c/ghi
Row address
Row decoder
2r 2c m bits
Cell Matrix
Cell Matrix
Mng 2 chiu cc phn t nh
Sense/Write amplifiers
Sense/write amplifiers
Data
Lm r mc 0/1 khi c/ghi
S dng chung ng d liu vo/ra
Row Latch 2c m bits
...
Column Decoder
c
Column address
Fall 2013, CS
16
dce
Thng s DRAM
2013
Year
Produced
1980
1983
1986
1989
64 Kbit
256 Kbit
1 Mbit
4 Mbit
DRAM
DRAM
DRAM
DRAM
Row
access
170 ns
150 ns
120 ns
100 ns
1992
16 Mbit
DRAM
80 ns
15 ns
120 ns
1996
64 Mbit
SDRAM
70 ns
12 ns
110 ns
1998
128 Mbit
SDRAM
70 ns
10 ns
100 ns
2000
256 Mbit
DDR1
65 ns
7 ns
90 ns
2002
512 Mbit
DDR1
60 ns
5 ns
80 ns
2004
2006
2010
2012
1 Gbit
2 Gbit
4 Gbit
8 Gbit
DDR2
DDR2
DDR3
DDR3
55 ns
50 ns
35 ns
30 ns
5 ns
3 ns
1 ns
0.5 ns
70 ns
60 ns
37 ns
31 ns
Chip size
Type
Column
access
75 ns
50 ns
25 ns
20 ns
Cycle Time
New Request
250 ns
220 ns
190 ns
165 ns
Fall 2013, CS
17
dce
2013
SDRAM v DDR SDRAM
SDRAM: Synchronous Dynamic RAM

Thm tn hiu clock vo DRAM
SDRAM c ng b vi xung nhp h thng

DRAM vi cng ngh c l loi bt ng b
Khi xung nhp h thng tng, SDRAM c hiu nng
cao hn DRAM bt ng b
DDR: Double Data Rate SDRAM

Ging vi SDRAM, DDR ng b vi xung nhp h
thng, nhng khc ch DDR c d liu ti cnh
ln v cnh xung ca tn hiu xung nhp
Fall 2013, CS
18
dce
2013
Transfer Rates & Peak Bandwidth

Standard
Name
Memory
Bus Clock
Millions Transfers
per second
Module
Name
Peak
Bandwidth
DDR-200
100 MHz
200 MT/s
PC-1600
1600 MB/s
DDR-333
167 MHz
333 MT/s
PC-2700
2667 MB/s
DDR-400
200 MHz
400 MT/s
PC-3200
3200 MB/s
DDR2-667
333 MHz
667 MT/s
PC-5300
5333 MB/s
DDR2-800
400 MHz
800 MT/s
PC-6400
6400 MB/s
DDR2-1066
533 MHz
1066 MT/s
PC-8500
8533 MB/s
DDR3-1066
533 MHz
1066 MT/s
PC-8500
8533 MB/s
DDR3-1333
667 MHz
1333 MT/s
PC-10600
10667 MB/s
DDR3-1600
800 MHz
1600 MT/s
PC-12800
12800 MB/s
DDR4-3200
1600 MHz
3200 MT/s
PC-25600
25600 MB/s
1 Transfer = 64 bits = 8 bytes of data

Fall 2013, CS
19
dce
2013
Ni dung trnh by
T chc / thit k b nh
Phn loi b nh m
Fall 2013, CS
20
dce
T chc b nh
2013
n
a
ch
Gii m
a ch
4
a ch 00 (0)
a ch 01 (1)
a ch 10 (2)
a ch 11 (3)
Gii m
a ch
2n
la
chn
4 x 8 bit
D liu 8 bit
a ch 000 (0)
a ch 001 (1)
a ch 010 (2)
a ch 011 (3)
a ch 100 (4)
a ch 101 (5)
a ch 110 (6)
a ch 111 (7)
Gii m
a ch
8 x 16 bit
D liu 16 bit
byte cao byte thp

2010, Dr. Dinh Duc Anh Vu
Fall 2013, CS
21
21
dce
T chc theo dung lng
2013
A15 A0
64K x 8 bit
64K x 8 bit
64K x 8 bit
2
A17
A16
4
64K x 8 bit
Gii m
a ch
Tng cng c 256K x 8 bit
D7 D0
Fall 2013, CS
22
22
dce
T chc theo kch thc
2013
64K x 8 bit
64K x 8 bit
64K x 8 bit
64K x 8 bit
D31 D24
D23 D16
D15 D8
D7 D0
A15 A0
Tng cng c 64K x 32 bit
Fall 2013, CS
23
23
dce
Gii m a ch b nh
2013
A12
A11
00
0000 0000
08
0000 1000
B nh
0000
0000
07FF
0800
Bank 0
Tuyn a ch
Mch
gii m
a ch
0FFF
1000
17FF
07FF
0000
Bank 1
07FF
0000
1800
Bank 2
1FFF
07FF
0000
10
0001 0000
Bank 3
18
07FF
0001 1000
Fall 2013, CS
24
24
dce
Gii m a ch b nh
2013
a ch
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0000
0001
07FF
0800
0801
0FFF
1000
1001
17FF
1800
1801
...
...
...
...
1FFF
Fall 2013, CS
25
25
dce
Mch chi tit
2013
U5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RD
WR
8
7
6
5
4
3
2
1
23
22
19
18
20
21
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U2A
A11
A12
2
3
MREQ
A
B
G
Y0
Y1
Y2
Y3
4
5
6
7
RD
WR
8
7
6
5
4
3
2
1
23
22
19
18
20
21
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
CS
OE
WE
U6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
U3
9
10
11
13
14
15
16
17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RD
WR
8
7
6
5
4
3
2
1
23
22
19
18
20
21
HM6116/SO
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
13
14
15
16
17
CS
OE
WE
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
8
7
6
5
4
3
2
1
23
22
19
18
20
21
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
13
14
15
16
17
D0
D1
D2
D3
D4
D5
D6
D7
CS
OE
WE
U4
RD
WR
HM6116/SO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
HM6116/SO
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
13
14
15
16
17
D0
D1
D2
D3
D4
D5
D6
D7
CS
OE
WE
HM6116/SO
74LS139
Fall 2013, CS
26
26
dce
Bi tp (1)
2013
1) Tnh cc a ch CS1, CS2, CS3, CS4

U7A
A13
A15
MREQ
2
3
A
B
G
U8A
Y0
Y1
Y2
Y3
4
5
6
7
CS1
CS2
A11
A12
74LS139
2
3
A
B
G
Y0
Y1
Y2
Y3
4
5
6
7
CS5
U9A
1
CS3
CS4
74LS139
74LS08
U10A
1
2
74LS08
2) V mch gii m a ch cho b nh cho cc trng hp sau :

a. 14KB = 2 x 4KB + 2 x 2KB + 2 x 1KB
b. 32KB= 2 x 8KB + 4 x 4KB
3) Thit k mch gii m a ch b nh cho h thng Z80-CPU: 1ROM 4K,
1RAM 4K v 2RAM 2K. Yu cu a ch RAM lin tc t 1800H tr i.
Fall 2013, CS
27
27
dce
Bi tp (2)
2013
4) Hy xc nh tm a ch lm cho cc tn hiu CS1,

CS2, CS3 trong mch gii m a ch sau y tch cc.
U1
A10
A11
A12
1
2
3
15
Y0
Y1
Y2
Y3
A15
A14
MREQ
Y4
6
4
5
G1
Y5
G2A
Y6
G2B
Y7
U2A
14
A8
13
A9
12
11
2
3
Y0
Y1
Y2
1
G
10
9
4
A
CS1
U3A
13
12
CS3
Y3
74LS139
74LS11
74LS138
U2B
A7
A8
14
13
12
A
Y0
Y1
Y2
15
G
11
10
CS2
Y3
74LS139
Fall 2013, CS
28
28
dce
2013
Bi tp (3)
5. Mt h thng my tnh
dng CPU c tuyn a ch
16 ng A15 A0 v c
bn s dng b nh
nh sau:
a) Hy xc nh tm a ch
s dng ca tng chip b
nh trong h thng.
b) Thit k mch gii m
a ch b nh y cho
CPU trn. Tn hiu chn b
nh c tn l MREQ.
0000H
4K SRAM1
1K khng c
2K EPROM1
3K khng c
4K SRAM 2
2K EPROM 2
Fall 2013, CS
29
29
dce
2013
Ni dung trnh by
T chc / thit k b nh
Phn loi b nh m
Fall 2013, CS
30
dce
2013
Khong cch v hiu nng ca CPU-DRAM
B x l MIPS chy vi tc 2GHz c th thc thi 100

lnh trong thi gian truy xut d liu b nh chnh
DRAM c thi gian truy xut 50ns
Fall 2013, CS
31
31
dce
2013
Quy lut cc b ca tham kho

Chng trnh c xu hng s dng li d liu v lnh
s dng hoc tham kho gn y
Cc b v mt thi gian
Nu mt phn t (bin, hm, i tng) c tham kho, s
c tham kho li ngay sau
VD: cc lnh trong vng lp c np li sau mi ln lp; hm
printf c th c gi v thc thi nhiu ln
Cc b v mt khng gian
Mt lnh ang c thc thi, lnh k tip nhiu kh nng c
thc thi
Mt phn t c tham kho, cc phn t gn c kh truy
xut sau
VD: Cc lnh c thc thi tun t; duyt cc phn t mng
lin tip nhau
Fall 2013, CS
32
dce
2013
VD tnh cc b ca tham kho

Xt on chng trnh:
Cc b v mt thi gian
sum =
for (i
sum
return
0;
= 0; i<n; i++)
+= a[i];
sum
Bin sum c tham kho mi ln lp

Lnh sum += a[i] c lp li
Cc b v mt khng gian
Cc phn t ca mng a[] ln lc c tham kho qua mi ln
lp
Cc lnh lin tip nhau (dng hp ng ca on chng trnh)

s c thc thi
Fall 2013, CS
33
dce
2013
VD tnh cc b ca tham kho

Sinh vin mn sch tham
kho t th vin
Cc b v mt thi gian
Sch Computer Architecture
c tham kho li hng
tun trong hc k ny
Cc b v mt khng gian
Sch ca nhng mn khc
(vd: Cu trc d liu gii
thut) c ging dy trong
k ny cng c tham kho
Fall 2013, CS
34
dce
2013
S cn thit ca b nh m
Khon cch tc ngy cng xa gia CPU - DRAM
Mi lnh cn t nht mt truy xut n b nh

Mt truy xut np lnh
Truy xut th hai c th c cho lnh load/store
Bng thng b nh gii hn tc thc hin lnh

Chi ph trn mt phn t nh ca b nh tc cao
(SRAM, D Flip-Flop) ln -> gi SRAM 1GHz ??
Cn gii quyt bi ton b nh va nhanh, va r

Bi ton ny c gii quyt bi vic m d liu (b
nh m, t chc b nh phn cp) da vo c tnh
cc b ca tham kho ca mt chng trnh
Fall 2013, CS
35
dce
2013
B nh m l g ?
B nh nhanh (SRAM), dung lng t
m mt phn d liu v lnh ca chng trnh ang thc thi
c s dng gim thi gian truy xut trung bnh n

b nh chnh
B nh m tn dng tnh cc b v thi gian bi
Gi d liu truy xut gn y gn vi b x l
B nh m tn dng tnh cc b v khng gian bi

a c nhng d liu gn d liu ang truy xut vo b nh
m
Mc ch t c
Tc truy xut nhanh ca SRAM dng trong b nh m
Cn bng chi ph ca h thng b nh

Fall 2013, CS
36
T chc b nh phn cp
Cc thanh ghi trn cng
Dung lng thng thng < 1 KB
Thi gian truy xut (access time) < 0.5 ns
B nh m cp 1 L1 Cache (8 64 KB)
Microprocessor
Access time: 1 ns
B nh m L2 (512KB 8MB)
Registers
Access time: 3 10 ns
L1 Cache
B nh chnh (4 16 GB)
L2 Cache
Access time: 50 100 ns
Disk Storage (> 200 GB)

Access time: 5 10 ms
Memory Bus
Bigger
2013
Faster
dce
Main Memory
I/O Bus
Magnetic or Flash Disk
Fall 2013, CS
37
dce
c tnh ca b nh phn cp
2013
Chiu tng
ca thi
gian truy
xut theo
khong
cch n
b x l
n v dch
chuyn
gia mi
cp
Processor
4-8 bytes (word)
L1$
8-32 bytes (block)
L2$
1 to 4 blocks
Main Memory
1,024+ bytes
(disk sector = page)
Secondary Memory
Tnh bao gp
nhng g
trong L1$ l
tp con ca
nhng g
trong L2$ v
l tp con ca
nhng g
trong b nh
chnh v l tp
con ca b
nh th cp
Kch thc tng i c b nh mi cp
38
Fall 2013, CS
38
dce
m d liu ca b nh m
2013
Cp k:
D liu c
dch chuyn
gia cc cp
theo n v
khi (block)
Cp k+1:
Cp m k c tc
nhanh, dung lng t,
d liu l tp con ca
cp m k+1
Cp m k+1 c tc
chm, dung lng ln,
d liu c chia
thnh tng khi
Fall 2013, CS
39
dce
Cc khc nim v b nh m
2013
Chng trnh ang tham kho

d liu w trong block b
Cache hit:
Cp k:
Chng trnh tm thy b b nh

m cp k (vd: block 14)
Cache miss:
b (vd: 12) khng c cp k, phi
ly t cp k+1, ng thi c
a vo cp k
Cch nh x? b s c a vo
v tr no (vd: 12 mod 4 = 0)
Cp
k+1:
Nu b nh m cp k y, mt
block no s c thay th:
Chin lc thay th? vd: thay th
bock c a vo sm nht
Fall 2013, CS
40
dce
2013
Hot ng ca b nh m
B x l yu cu load mt d liu w trong block b
So snh trng tag ca a ch truy xut vi tag address

Miss (khng tm thy
trong b nh m)
Hit (tm
thy trong
b nh
m)
Truy xut block b t b nh

cp thp hn
a block b vo b nh
m + thay th nu cn
Ly d liu w t block b
b nh m cho b x l
Fall 2013, CS
41
dce
2013
Ni dung trnh by
T chc / thit k b nh
Phn loi b nh m
Fall 2013, CS
42
dce
2013
Bn cu hi lin quan ti b nh m
Q1: Mt khi s c a
vo u trong b nh m?
Direct Mapped, Set Associative,
Fully Associative
Q2: Lm sao tm mt khi

(xc nh hit/miss)?
Block address, tag, index
Q3: Khi no s c thay

th khi miss v b nh m
y?
FIFO, Random, LRU
Q4: Vic ghi nh th no?

Write Back/Write Through (with
Write Buffer)
Fall 2013, CS
43
dce
2013
Q1: a mt block vo b nh m
Block 12 c Bt k v tr
no
a vo v tr
no?
Bt k v tr
no trong set
0 (12 mod 4)
Ti v tr 4
(12 mod 8)
Fall 2013, CS
44
dce
2013
Q2: Tm mt block trong b nh m
Index: tm n line (set) no; so snh Tag ca a ch

truy xut vi gi tr trng tags (vi Valid bit V l hp l)
Offset: xc nh d liu w cn ly trong block b
Hnh trn: Direct mapped, 8 Byte/block, 4 line cache
Offset: 3 bit; Index: 2 bit; Tag: 32 (3 + 2) = 27 bit
Fall 2013, CS
45
dce
2013
Q2: Tm mt block trong b nh m
Index: tm n set no; so snh Tag a ch truy xut

vi tt c gi tr trng tags trong set tm n (vi
Valid bit V l hp l)
Hnh trn: 2-way associative, 8 Byte/block, 4 line cache
Offset: 3 bit; Index: 1 bit; Tag: 32 (3 + 1) = 28 bit
Fall 2013, CS
46
dce
2013
nh x mt a ch vo mt block b nh m
V d:
Xt mt b nh m direct-mapped c 256 block (line)
Block size = 16 bytes
Tnh gi tr tag, index, byte offset ca a ch: 0x01FFF8AC
Li gii
32-bit a ch c chia:
Block Address
20
Tag
Index offset
4-bit byte offset, v block size = 24 = 16 bytes

8-bit cache index, v b nh m c 28 = 256 sets (1 set gm 1
line/block)
20-bit tag
Byte offset = 0xC = 12 (4 bit thp gi tr a ch)

Cache index = 0x8A = 138 (8 bit thp tip theo ca gi tr a ch)
Tag = 0x01FFF (20 bit cao ca gi tr a ch)
Fall 2013, CS
47
dce
V d Cache Hits & Misses
2013
Xt mt b nh m direct-mapped c 32 block
B nh m ban u rng, Block size = 16 bytes
Cc a ch sau (dng thp phn) c tham kho:
1000, 1004, 1008, 2548, 2552, 2556.

nh x nhng a ch vo block trong b nh m v xc nh
23
5
4
hit/miss
Li gii:
1000 = 0x3E8
1004 = 0x3EC
1008 = 0x3F0
2548 = 0x9F4
2552 = 0x9F8
2556 = 0x9FC
Tag
Index offset
cache index = 0x1E

cache index = 0x1E
cache index = 0x1F
cache index = 0x1F
cache index = 0x1F
cache index = 0x1F
Miss (truy xut ln u)

Hit
Miss (V = khng hp l)
Miss (khc tag)
Hit
Hit
Fall 2013, CS
48
dce
V d Cache Hits & Misses
2013
Direct-mapped cache, 2 line, block size = 2 word

0 1 2 3 4 3 4 15
Start with an empty cache - all

blocks initially marked as not valid
00
0 miss
Mem(1) Mem(0)
00
1 hit
Mem(1) Mem(0)
00
00
3 hit
Mem(1) Mem(0)
Mem(3) Mem(2)
01
00
00
4 miss
5
4
Mem(1) Mem(0)
Mem(3) Mem(2)
01
00
4 hit
Mem(5) Mem(4)
Mem(3) Mem(2)
1101
00
00
00
2 miss
Mem(1) Mem(0)
Mem(3) Mem(2)
01
00
3 hit
Mem(5) Mem(4)
Mem(3) Mem(2)
15 miss
Mem(5) Mem(4)
15
14
Mem(3) Mem(2)
Fall 2013, CS
49
49
dce
2013
Q3: Thay th mt block khi y + miss

Khng c la chn trong b nh m direct-mapped
V b nh m associative, block no c thay th
khi y v miss?
Ngu nhin
Least Recently Used (LRU)
Thay th block khng c tham kho lu nht
Cp nht th t ca block mi khi hit
First In First Out (FIFO)

Thay th block a vo trc mt set
Mt b m theo di c tng mi khi miss
Fall 2013, CS
50
dce
2013
Q4: Chin lc ghi

Trng hp Cache Hit:
Write Through ghi d liu vo c b nh m v b nh
chnh
Write Back ch ghi d liu vo b nh m, ghi d liu vo
b nh chnh khi miss
Trng hp Cache Miss:

Write Allocate np block cha d liu cn ghi vo b nh
m, sau thc hin ghi
No Write Allocate khng thay i b nh m, ch ghi xung
b nh chnh
Cc kt hp thng dng:
Write Through & No Write Allocate
Write Back & Write Allocate
Fall 2013, CS
51
dce
2013
Ni dung trnh by
T chc / thit k b nh
Phn loi b nh m
Fall 2013, CS
52
dce
Hit Rate & Miss Rate
2013
Hit Rate
= Hits / (Hits + Misses)
Miss Rate = Misses / (Hits + Misses)
I-Cache Miss Rate = Miss rate ti b nh m lnh

D-Cache Miss Rate = Miss rate ti b nh m d liu
V d:
1000 lnh c np, 150 ln miss I-Cache
25% l lnh load-store, 50 ln miss D-Cache
Tnh I-cache v D-cache miss rate?
I-Cache Miss Rate = 150 / 1000 = 15%

D-Cache Miss Rate = 50 / (25% 1000) = 50 / 250 = 20%
Fall 2013, CS
53
dce
2013
Memory Stall Cycles

B x l stall trong trng hp Cache miss
Khi np lnh t Instruction Cache (I-cache)
Khi load/store d liu ti Data Cache (D-cache)
Memory stall cycles = Combined Misses Miss Penalty

Miss Penalty: s chu k xung nhp cn x l miss
Combined Misses = I-Cache Misses + D-Cache Misses
I-Cache Misses = I-Count I-Cache Miss Rate
D-Cache Misses = LS-Count D-Cache Miss Rate

LS-Count (Load & Store) = I-Count LS Frequency
Fall 2013, CS
54
dce
2013
Memory Stall Cycles Per Instruction

Memory Stall Cycles Per Instruction =
Combined Misses Per Instruction Miss Penalty
Miss Penalty c gi s bng nhau cho I-cache & Dcache

Miss Penalty c gi s bng nhau cho Load & Store
Combined Misses Per Instruction =
I-Cache Miss Rate + LS Frequency D-Cache Miss Rate
Do , Memory Stall Cycles Per Instruction =
I-Cache Miss Rate Miss Penalty +

LS Frequency D-Cache Miss Rate Miss Penalty
Fall 2013, CS
55
dce
2013
V d v Memory Stall Cycles

Xt mt chng trnh c cc thng s sau:
Instruction count (I-Count) = 106 lnh
30% l lnh load & store
D-cache miss rate l 5%; I-cache miss rate l 1%
Miss penalty: 100 clock cycles (chu k xung nhp
Tnh combined misses per instruction v memory stall cycles
Combined misses per instruction in I-Cache and D-Cache

1% + 30% 5% = 0.025 combined misses per instruction
25 ln miss trn 1000 lnh
Memory stall cycles

0.025 100 (miss penalty) = 2.5 stall cycles per instruction
Total memory stall cycles = 106 2.5 = 2,500,000
Fall 2013, CS
56
dce
2013
CPU Time vi Memory Stall Cycles

CPU Time = I-Count CPIMemoryStalls Clock Cycle
CPIMemoryStalls = CPIPerfectCache + Mem Stalls per Instruction

CPIPerfectCache = CPI khi b nh m l l tng (khng
b miss)
CPIMemoryStalls = CPI khi tnh n memory stalls
Memory stall cycles lm tng CPI tng th
Fall 2013, CS
57
dce
2013
V d CPI vi Memory Stalls

Mt b x l c CPI l 1.5 cho trng hp khng miss
Cache miss rate l 2% cho I-cache v 5% cho D-cache (load &
store)
20% lnh l load & store

Cache miss penalty: 100 clock cycles cho c I-cache & D-cache
Tnh CPI khi tnh ti cache miss?

Li gii:
Instruction
data
Mem Stalls per Instruction = 0.02100 + 0.20.05100 = 3

CPIMemoryStalls = 1.5 + 3 = 4.5 cycles per instruction
CPIMemoryStalls / CPIPerfectCache = 4.5 / 1.5 = 3
B x l chy chm i 3 ln v memory stall cycles
CPINoCache = 1.5 + (1 + 0.2) 100 = 121.5 (rt ln)
Fall 2013, CS
58
dce
2013
Average Memory Access Time

Average Memory Access Time (AMAT)
AMAT = Hit time + Miss rate Miss penalty
Thi gian truy xut trung bnh tnh c cho trng hp hit
& miss
V d: Tnh AMAT cho b nh m:
Thi gian truy xut b nh m (Hit time) = 1 clock cycle = 2 ns
Miss penalty: 20 clock cycles
Miss rate: 0.05
Li gii:
AMAT = 1 + 0.05 20 = 2 cycles = 4 ns
Khi khng dng b nh m, AMAT s bng Miss penalty = 20 cycle
Fall 2013, CS
59
dce
2013
Ci tin hiu nng ca b nh m

Average Memory Access Time (AMAT)
AMAT = Hit time + Miss rate * Miss penalty
Cng thc AMAT c s dng thc hin ci tin
Gim Hit time
B nh m phi nh v n gin
Gim Miss Rate

B nh m phi ln, associativity nhiu, block size ln
Gim Miss Penalty

B nh m phi nhiu cp
Fall 2013, CS
60
dce
2013
Phn loi Miss 3C
Compulsory (bt buc): Tham kho n mt block cha

tn ti trong b nh m (valid bit c gi tr khng hp l)
Capacity (dung lng): Dung lng b nh m khng

cha d liu cn trong mt chng trnh (vd:
chng trnh cn 5 block cha d liu > 4)
Conflict (xung t): ng do thiu associativity (vd:
chng trnh lp trn 3 block d liu > 2)
Fall 2013, CS
61
dce
Phn loi Miss
2013
Compulsory misses c lp vi cache size

Rt nh khi chy chng trnh di
Miss Rate
14%
Capacity misses gim khi tng dung

lng b nh m
1-way
12%
2-way
Conflict misses khi tng

tnh associativity
10%
4-way
8%
8-way
6%
Capacity
Compulsory
4%
2%
0
1
16
32
64
128 KB Dung lng

Fall 2013, CS
62

Chapter05 BoNho

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dce

Faculty of Computer Science and

Computer Architecture Chapter 5

Computer Architecture Chapter 5

Computer Architecture Chapter 5

Computer Architecture Chapter 5

H thng b nh phn cp trong Pipline

I-Cache miss hoc D-Cache miss

Interface to L2 Cache or Main Memory

Computer Architecture Chapter 5

Thanh ghi c thnh phn chnh l cc D Flip-Flop, c n bit

Chi tit b thanh ghi

B thanh ghi MIPS gm 32 thanh ghi 32 bit; RA, RB l 2 u vo yu

Computer Architecture Chapter 5

B nh truy xut ngu nhin RAM

Truy xut ngu nhin

Tn hiu iu khin Output Enable (OE)

Tn hiu iu khin Write Enable (WE)

2n m RAM : n-bit a ch, m-bit d liu

Cn t nng lng duy tr gi tr lu tr

Dynamic RAM (DRAM) dng cho b nh chnh

Tc truy xut d liu thp (~ 100ns)

Computer Architecture Chapter 5

Computer Architecture Chapter 5

Computer Architecture Chapter 5

M hnh bit nh ca DRAM

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Chu k lm ti (refresh cycle) vo khong 10ms

Bng thng b nh b gim bi vic lm ti

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24 chn, dng dual in-line cho b nh 16Mbit = 222 4

11-bit row address

Vss D4 D3 CAS OE A9 A8 A7 A6 A5 A4 Vss

Vcc D1 D2 WE RAS NC A10 A0 A1 A2 A3 Vcc

La chn hng c/ghi

Lm r mc 0/1 khi c/ghi

S dng chung ng d liu vo/ra

Row Latch 2c m bits

Computer Architecture Chapter 5

Computer Architecture Chapter 5

SDRAM v DDR SDRAM

SDRAM: Synchronous Dynamic RAM

SDRAM c ng b vi xung nhp h thng

DDR: Double Data Rate SDRAM

Transfer Rates & Peak Bandwidth

1 Transfer = 64 bits = 8 bytes of data

Computer Architecture Chapter 5

byte cao byte thp

Computer Architecture Chapter 5

T chc theo dung lng

Tng cng c 256K x 8 bit

Computer Architecture Chapter 5

T chc theo kch thc

Tng cng c 64K x 32 bit

2010, Dr. Dinh Duc Anh Vu

Computer Architecture Chapter 5

Computer Architecture Chapter 5

2010, Dr. Dinh Duc Anh Vu

Computer Architecture Chapter 5

Mch chi tit

2010, Dr. Dinh Duc Anh Vu

Computer Architecture Chapter 5

1) Tnh cc a ch CS1, CS2, CS3, CS4