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A

Compal confidential

Schematics of HP - dv5296ea
Mobile Yonah uFCPGA with
Intel Calistoga_PM+ICH7-M core logic
2005-06-01

REV:0.1

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

Rev
A

, 01, 2005

Sheet
E

of

48

Compal confidential

NAPA

Model:HAQAA
File Name : LA-3011

Mobile Yonah

Fan Control

page 4

Clock Generator

Thermal Sensor
ADM1032AR

uFCPGA-479 CPU
page 4,5,6

LCD CONN

page 4

page 17

page 15

page 28

F SB
H_A#(3..31)

nVIDIA G72/G73
ATI M52/M54 page

Accelerometer
KXP84-0200

ICS9LPRS325AKLFT

533/667MHz

H_D#(0..63)

DDR2 -400/533/667

PCI-E x 16

Intel Calistoga MCH


945PM

18

CRT / TV-OUT

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3

Dual Channel

PCBGA 1466

page 7,8,9,10,11,12

page 16

page 13,14

USB conn x1
(Docking) page

34

(port 6)

USB2.0 HUB /
page
FP Conn

38

(port 0)

FingerPrinter UPEK TCS3C/TCD42A


USBx1
page 38

PCI-E BUS

USB conn x2

DMI

page 24

(port 4,5)

(port 1)

10/100/1000 LAN
82562GX/82573E/82573V

BT Conn

Mini Express Card

page 24

(port 7)

page 28
USB2.0

PCI BUS

page 26,27

USB conn x2
(Sub Board) page

Intel ICH7-M

24

(port 2,3)

Azalia

MDC1.5

page 37

mBGA-652

CardBus Controller

RJ45/11 CONN
page 26

TI PCI7412

page 19,20,21,22

Audio CKT

page 22,23

Slot 0

page 23

1394 port

page 22

ALC861

5in1 Slot

page 22

LED

TPA0232

page 30

SATA HDD Connector

SATA Master

LPC BUS

page 36

AMP & Audio Jack


page 29

page 19

PATA Slave

PATA ODD Connector


page 19

RTC CKT.
page 19

TPM1.2
SLB9635TT1.2

Docking

page 38

page 34

Super I/O

LPC47N217&207

ENE KB910QF

page 33,38

CIR

page 25

page 33

Power On/Off CKT.


FIR

page 37

page 33

DC/DC Interface CKT.


Touch Pad

page 39

page 37

Int.KBD
page 37

BIOS

page 35

Power Circuit DC/DC


Page,40,41,42,43,44,45,46
Compal Secret Data

Security Classification
Issued Date

2005/06/01

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

Re v
A

P, 01, 2005

Sheet
E

of

48

Voltage Rails

Board ID / SKU ID Table for AD channel

Power Plane

Description

S0-S1

S3

S5

VIN

Adapter power supply (18.5V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

Vcc
Ra/Rc/Re
Board ID

ON

OFF

OFF

+0.9VS

1.05V power rail for Processor I/O and MCH/ICH core power
0.9V switched power rail for DDRII Vtt

ON

OFF

OFF

+1.5VS

1.5V switched power rail for PCI-E interface

ON

OFF

OFF

+1.8V

1.8V power rail for DDRII

ON

ON

OFF

+VCCP

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail for MCH video PLL

ON

OFF

OFF

+2.5VALW

3.3V always on power rail

ON

ON

ON*

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_VCC

RTC power

ON

ON

ON

0
1
2
3
4
5
6
7

Internal PCI Devices


DEVICE

Bus

PCI Device ID

1
0
0
0
0
0
0
0
0
0
0
0
0

Azal ia
PCI-E
USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F
D MA
PMU

AD24

D27

AD11

CARD BUS

D28

AD12

D29

AD13

D30

AD14

D30

AD14

D30

AD14

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

IDSEL #

D6

SKU

AD22

BTO Option Table

REQ/GNT #

PIRQ

BOM Structure
PM@

VGA

GM@

A BCD

LAN

82573G@
82573L@
82573@
82562@

INT MIC.

45MIC@

DOCKING

WD@
WOD@

DEVICE

HEX

ADDRESS

CIR@

CIR
FIR

FIR@

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

SUPER I/O

CLOCK GENERATOR (EXT.)

D2

11010010

Battery

2005/06/01

Issued Date

217@
A

SI207@
45@

Compal Secret Data

Security Classification

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PCB Revision
0.1

SKU ID
0
1
2
3
4
5
6
7

I2C / SMBUS ADDRESSING

V AD_BID max
0.100 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

SKU ID Table

BTO Item

PCI Device ID

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

IDSEL #

D8

External PCI Devices


DEVICE

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

Board ID
0
1
2
3
4
5
6
7

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

L AN

3.3V +/- 5%
100K +/- 1%
Rb / Rd / Rf
0
8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%
NC

BOARD ID Table

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

This shall place near CPU

H_RS#[0..2]

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
R115
1
2
56_0402_5%

+VCCP

H_PWRGOOD
H_CPUSLP#

R111 1
R112 1

2
2

51_0402_5%
51_0402_5%

F3
F4
G3
G2

AD4
AD3
AD1
AC4

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBRESET#
C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
XDP_BPM#4 AC2
XDP_BPM#5 AC1
H_PROCHOT# D21

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

H_PW RGOOD D6
H_CPUSLP#
D7
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
TEST1
C26
TEST2
D25
XDP_TMS
AB5
XDP_TRST# AB6

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP# C7

H_THERMTRIP#

H_THERMDA, H_THERMDC routing together.


Trace width / Spacing = 10 / 10 mil

MISC

DINV0#
DINV1#
DINV2#
DINV3#

J26
M26
V23
AC20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

H_STPCLK#
H_SMI#

LEGACY CPU

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

D+

VDD1

THERMDC

D-

ALERT#

EC_SMB_CK2

SCLK

THERM#

EC_SMB_DA2

SDATA

GND

56_0402_5%

XDP_BPM#5

R75

56_0402_5%

XDP_TRST#

R80

56_0402_5%

XDP_TCK

R78

56_0402_5%

ADM1032ARM_RM8

+5VS

B+

+3VS
C

D
G

+IN

OUT
-IN

FAN1_ON

Q29

EN_DFAN1

1
2
5
6

0.01U_0402_25V4Z
2
1
C6

C362
10U_1206_16V4Z

U2A
LM358A_SO8

SI3456DV-T1_TSOP6

R429
10K_0402_5%
1

R2
1

R1

D30

150K_0402_5%

+IN

-IN

1N4148_SOD80

OUT

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

JP16

FAN1

100K_0402_5%

@ C373
1000P_0402_50V7K

U2B
LM358A_SO8

ACES_85205-0300

FAN_SPEED1
@

1
2
3

H_DSTBN#[0..3]

H_DSTBP#[0..3]
R255
1
2
@ 56_0402_5%

+VCCP

Placement near to ICH7


H_FERR# 2
C212

1
@ 180P_0402_50V8J

H_SMI#

2
C159
2
C145
H_NMI
2
C160
H_A20M#
2
C161
H_INTR
2
C144
H_IGNNE#
2
C139
H_STPCLK#
2
C137
H_PW RGOOD
2
C134
H_CPUSLP#
2
C138

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J

H_INIT#

H_STPCLK#
H_SMI#

FOX_PZ47903-2741-42_YONAH

Placement near to CPU side

+VCCP
R117
H_DPSLP# 1

@ 56_0402_5%

@ 56_0402_5%
R110
H_DPRSTP# 1
2

2 2

R118

1 OCP#
Q13
@ MMBT3904_SOT23
5

Compal Secret Data

Security Classification
2005/06/01

Issued Date

@ 56_0402_5%

H_PROCHOT# 3

+VCCP

C374
150U_D2_6.3VM

CONTROL

R76

R116
@ 10K_0402_5%

U8
2

56_0402_1%

XDP_TDO

C371 10U_0805_10V4Z

H_LOCK#
H_RESET#

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

C148
0.1U_0402_16V4Z

THERMDA

2200P_0402_50V7K

56_0402_5%

1000P_0402_50V7K

R114
56_0402_5%
1
2

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

HOST CLK

1
C163

C372

+VCCP

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRD Y#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#

BCLK0
BCLK1

R77

CLK_CPU_BCLK A22
CLK_CPU_BCLK# A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

Thermal Sensor ADM1032ARM

R79

ADSTB0#
ADSTB1#

+3VS

XDP_TDI
XDP_TMS

L2
V4

H_ADSTB#0
H_ADSTB#1

H_ADSTB#0
H_ADSTB#1
C

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

K3
H2
K2
J3
L5

DATA GROUP

ADDR GROUP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

YONAH

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

H_REQ#[0..4]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

+VCCP

H_D#[0..63]

JP22A

H_A#[3..31]

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

OCP#

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

+VCCP

2
1

R86
100_0402_1%
2

R85
100_0402_1%
1
2

VCCSENSE

+1.5VS

C141
0.01U_0402_16V7K

R89
1K_0402_1%

VSSSENSE

R90
2K_0402_1%

Close to CPU pin AD26


within 500mils.

C143
10U_0805_10V4Z

+VCC_CORE

AF7
AE7

VCCSENSE
VSSSENSE

B26

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

H_PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

Close to CPU pin


within 500mils.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

166

AD26

V_CPU_GTLREF
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

R96
54.9_0402_1%
2
1

R105
27.4_0402_1%
2
1

R571
54.9_0402_1%
2
1

GTLREF

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1

COMP0
COMP1
COMP2
COMP3

+VCC_CORE

R579
27.4_0402_1%
2
1

JP22C
D

VCCSENSE
VSSSENSE

H_PSI#

JP22B

+VCCP

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

+VCC_CORE

Length match within 25 mils


The trace width 18 mils space
VCCSENSE
7 mils
VSSSENSE

V_CPU_GTLREF

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

FOX_PZ47903-2741-42_YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FOX_PZ47903-2741-42_YONAH

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C506
22U_0805_6.3V6M

C505
22U_0805_6.3V6M

C504
22U_0805_6.3V6M

C503
22U_0805_6.3V6M

C502
22U_0805_6.3V6M

C501
22U_0805_6.3V6M

C115
22U_0805_6.3V6M

C116
22U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C107
22U_0805_6.3V6M

C108
22U_0805_6.3V6M

C109
22U_0805_6.3V6M

C110
22U_0805_6.3V6M

C111
22U_0805_6.3V6M

C112
22U_0805_6.3V6M

C113
22U_0805_6.3V6M

C114
22U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C530
22U_0805_6.3V6M

C529
22U_0805_6.3V6M

C528
22U_0805_6.3V6M

C527
22U_0805_6.3V6M

C526

22U_0805_6.3V6M
2
@

C525

22U_0805_6.3V6M
2
@

C135

22U_0805_6.3V6M
2
@

C136
22U_0805_6.3V6M
@

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C149

22U_0805_6.3V6M
2
@

C150

22U_0805_6.3V6M
2
@

C151

22U_0805_6.3V6M
2
@

C152

22U_0805_6.3V6M
2
@

C153

22U_0805_6.3V6M
2
@

C154

22U_0805_6.3V6M
2
@

C155

22U_0805_6.3V6M
2
@

C156
22U_0805_6.3V6M
@

Mid Frequence Decoupling

+VCC_CORE
330U_D_2VM

330U_D_2VM

@ 330U_D_2VM

South Side Secondary

North Side Secondary


1

C172
330U_D_2VM

1
+

C173

1
+

C171

1
C532

1
C129

1
C523

1
C491

+
2

1
+ C490
2

ESR <= 1.5m ohm


Capacitor > 1980uF

@ 330U_D_2VM

330U_D_2VM

330U_D_2VM

330U_D_2VM

C522
330U_D2E_2.5VM_R9
@

1
C531

+
2

330U_D2E_2.5VM_R9

+VCCP

C513
0.1U_0402_16V4Z

C515
0.1U_0402_16V4Z

C517
0.1U_0402_16V4Z

C512
0.1U_0402_16V4Z

C514
0.1U_0402_16V4Z

C516
0.1U_0402_16V4Z

Place these inside


socket cavity on L8
(North side
Secondary)

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

R82
54.9_0402_1%
2
1

R81
54.9_0402_1%
2
1

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1

R73
24.9_0402_1%
2
1

R72
24.9_0402_1%
2
1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
H_REQ#[0..4]

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRD Y#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HDINV#0
HDINV#1
HDINV#2
HDINV#3
HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

H_ADSTB#0
H_ADSTB#1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DSTBN#[0..3]

H_DSTBP#[0..3]

R520 1
1
R515

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

2 80.6_0402_1%
2
80.6_0402_1%

AE35
AF39
AG35
AH39

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AY35
AR1
AW7
AW40

SM_CK0
SM_CK1
SM_CK2
SM_CK3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA# AW13
DDR_CS1_DIMMA# AW12
DDR_CS2_DIMMB# AY21
DDR_CS3_DIMMB# AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_OCDOCMP0
M_OCDOCMP1

AL20
AF10

SM_OCDCOMP0
SM_OCDCOMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP

AV9
AT9

PM_BMBUSY#
G28
PM_EXTTS#0
F25
0_0402_5%
PM_EXTTS#1
H26
1
2
H_THERMTRIP#
G6
H_THERMTRIP#
PWROK
AH33
@
PWROK
PLTRST_R#
AH34
2
1
R40
100_0402_1%
K28
MCH_ICH_SYNC#

DPRSLPVR

R495

PLT_RST#

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

CALISTOGA_FCBGA1466~D

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK
MCH_SSCDREFCLK#
MCH_SSCDREFCLK
MCH_CLKREQ#

R481
PM_EXTTS#0

R519
40.2_0402_1%
2
1

R503
40.2_0402_1%
2
1

2
1
2

100_0402_1%
2

R494
2
1
10K_0402_5%

M_OCDOCMP0
M_OCDOCMP1

R74

2
1
10K_0402_5%

PM_EXTTS#1

1
1
R87

221_0603_1%

1
R557
2

221_0603_1%

100_0402_1%

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

H_SWNG1

0.1U_0402_16V4Z
C100

1
R84
2

100_0402_1%

0.1U_0402_16V4Z
C482

1
R549
2

100_0402_1%

0.1U_0402_16V4Z

C473

H_VREF
200_0402_1%

1
R517
2

V_DDR_MCH_REF
C101
0.1U_0402_16V4Z

+VCCP

H_SWNG0

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

PM@

100_0402_1%
V_DDR_MCH_REF

+VCCP

H32

MCH_CLKREQ#

+1.8V

+VCCP

R518

GMCH_C40
GMCH_D41

Layout Note:
Route as short
as possible

R83

D_REF_SSCLKN
D_REF_SSCLKP

C40
D41

H_RS#[0..2]

PM@

GMCH_A27
GMCH_A26

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T16
T20
CFG5
T14
CFG7
T18
CFG9
T17
CFG11
CFG12
CFG13
T21
T15
CFG16
T22
CFG18
CFG19
CFG20

+3VS

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

CALISTOGA_FCBGA1466~D

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#
A27
A26

CLK_REQ#

ICH_SYNC#

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5 @
CFG6 @ PAD
CFG7
CFG8 @ PAD
CFG9
CFG10 @ PAD
CFG11
CFG12 @
CFG13
CFG14
PAD
CFG15
PAD
CFG16 @
CFG17 @ PAD
CFG18
CFG19 @
CFG20

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

D_REF_CLKN
D_REF_CLKP

SM_VREF0
SM_VREF1

PM_BMBUSY#

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

SM_RCOMPN
SM_RCOMPP

AK1
AK41

V_DDR_MCH_REF

H_RS#0
H_RS#1
H_RS#2

B4
E6
D6

M_ODT0
M_ODT1
M_ODT2
M_ODT3

+1.8V

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

CFG

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

Description at page11.

U6B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

CLK

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

PM

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+VCCP

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

HOST

H_A#[3..31]

U6A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

NC

H_D#[0..63]

RESERVED

Stuff R531 & R532 for A1 Calistoga


Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

AU12
AV14
BA20

SA_BS0
SA_BS1
SA_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U6E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYS MEMORY A

DDR_A_DM[0..7]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
T7 PAD
T6 PAD

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..13]

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
T19 PAD
T13 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

DDR SYS MEMORY B

U6D
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

CALISTOGA_FCBGA1466~D

CALISTOGA_FCBGA1466~D

PM@

PM@

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCEI_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCEI_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_P[0..15]

+3VS
GM@
2

R57

GM@

2.2K_0402_5%

LDDC_CLK

2.2K_0402_5%

LDDC_DATA

R483 1

2.2K_0402_5%

GMCH_CRT_CLK

R60

2.2K_0402_5%

GMCH_CRT_DATA

R480 1

10K_0402_5%

LCTLB_DATA

R478 1

10K_0402_5%

LCTLA_CLK

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

R484 1

100K_0402_5%

GMCH_ENBKL

R55

1.5K_0402_1%

LIBG

R69

75_0402_1%

GMCH_TV_COMPS

R68

150_0402_1%

GMCH_TV_LUMA

150_0402_1%

GMCH_TV_CRMA

R67

1
R8

2
1

2100K_0402_5%

GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLKGMCH_ENBKL

GMCH_ENVDD

GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_ENVDD

H27
H28

SDVOCTRL_DATA
SDVOCTRL_CLK

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

B37
B34
A36

LA_DATA0
LA_DATA1
LA_DATA2

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

A16
C18
A19

TVDAC_A
TVDAC_B
TVDAC_C

GMCH_ENBKL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
GMCH_ENVDD
LIBG

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
2
R504

TV_REFSET

1
4.99K_0402_1%
2
R505

GMCH_CRT_CLK
GMCH_CRT_DATA

GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
GMCH_CRT_R

2
R493
2 GM@
R498
2 GM@
R502

GMCH_CRT_G
GMCH_CRT_B

GM@

1
150_0402_5%
1
150_0402_5%
1
150_0402_5%
1
R499

2
255_0402_1%

J20

TV_IREF

B16
B18
B19

TV_IRTNA
TV_IRTNB
TV_IRTNC

J29
K30

TV_DCONSEL1
TV_DCONSEL0

C26
C25

DDCCLK
DDCDATA

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CRT

GMCH_CRT_CLK
GMCH_CRT_DATA

1
0_0402_5%

TV

GMCH_TV_LUMA
GMCH_TV_CRMA

EXP_COMPI
EXP_COMPO

LVDS

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

PEGCOMP trace width


and spacing is 18/25 mils.

U6C

PCI-EXPRESS GRAPHICS

R56

PEGCOMP

D40
D38

+1.5VS_PCIE
R472
24.9_0402_1%
2

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

C400
C36
C384
C25
C398
C38
C382
C27
C396
C40
C380
C29
C394
C42
C387
C31

PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

C401
C35
C385
C24
C399
C37
C383
C26
C397
C39
C381
C28
C395
C41
C388
C30

PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@
PM@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
B

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

CALISTOGA_FCBGA1466~D
PM@

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

of

48

+1.5VS

VCCA_TVBG
VSSA_TVBG

H20
G20

+3VS_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

+3VS_TVDACA

VCCD_HMPLL0
VCCD_HMPLL1

AH1
AH2

+1.5VS

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

A28
B28
C28

VCCD_TVDAC
VCCDQ_TVDAC

D21
H19

VCCHV0
VCCHV1
VCCHV2

A23
B23
B25

C430
0.1U_0402_16V4Z

C427
0.1U_0402_16V4Z

+3VS
R511
2
1
0_0805_5%

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+3VS_TVDACB

PCI-E/MEM/FSB PLL decoupling

+3VS_TVDACC

+1.5VS_3GPLL

+1.5VS_TVDAC
+3VS

C34

R58
2
1
0_0805_5%

1
C462

C449

C53
0.022U_0402_16V7K

10U_0805_6.3V6M
@

10U_0805_6.3V6M

+3VS_TVBG

+3VS
R70
2
1
0_0805_5%

+1.5VS

R560
2
1
0_0805_5%

45mA Max.
1

C483
10U_0805_6.3V6M

+1.5VS_DPLLB

40mA Max.

2
1
0_0805_5%

1
+

+1.5VS

C494
10U_0805_6.3V6M

R59
2
1
0_0805_5%

40mA Max.
1

+1.5VS

GM@

Compal Secret Data


2005/06/01

+1.5VS

+1.5VS_DPLLA

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

R470

GM@

Issued Date

+1.5VS_HPLL
R550
2
1
0_0805_5%

Security Classification

+1.5VS

+1.5VS_MPLL

+1.5VS_TVDAC
0.022U_0402_16V7K

10U_0805_6.3V6M

45mA Max.

R42
2
1
0_0805_5%

C453

+1.5VS

+1.5VS
R41
1
2
0.5_0805_1%

C44
0.1U_0402_16V4Z

P O W E R

CALISTOGA_FCBGA1466~D
PM@

+3VS_TVDACA

C465
0.1U_0402_16V4Z

+1.5VS_MPLL

+3VS
R62
2
1
0_0805_5%

C464
2200P_0402_50V7K

AF2

L14 BLM11A601S_0603
1
2
+2.5VS

+3VS_TVDACB

C57
0.1U_0402_16V4Z

VCCA_MPLL

+3VS
R508
2
1
0_0805_5%

C55
2200P_0402_50V7K

+2.5VS

+3VS_TVDACC

C460
0.1U_0402_16V4Z

A38
B39

10U_0805_6.3V6M

C461
2200P_0402_50V7K

VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

VCCA_LVDS
VSSA_LVDS

220U_D2_4VM

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

C434
330U_D2E_2.5VM_R9

B26
C39
AF1

C441
0.1U_0402_16V4Z~D

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

1 C405 1 C406

220U_D2_4VM

C493

MCH_D2
C103
0.47U_0603_10V7K
MCH_AB1

+2.5VS_CRTDAC

0.1U_0402_16V4Z

1
C102
0.22U_0603_10V7K

C425
0.22U_0603_10V7K

E21
F21
G21

C419
330U_D2E_2.5VM_R9

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

+ C379

C484

C93
0.47U_0603_10V7K

MCH_A6

+1.5VS_3GPLL
+2.5VS

+ C23

+1.5VS

0.1U_0402_16V4Z

AC33
G41
H41

R467
0_0805_5%
2
1

0.1U_0402_16V4Z~D
C417

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

10U_0805_6.3V6M

C43
0.1U_0402_16V4Z

C438
2.2U_0805_16V4Z

C480
4.7U_0805_10V4Z

AB41
AJ41
L41
N41
R41
V41
Y41

C456
0.1U_0402_16V4Z

+1.5VS_PCIE

W=40 mils

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

C77
0.1U_0402_16V4Z

+2.5VS

C457
2200P_0402_50V7K

B30
C30
A30

C81
2200P_0402_50V7K

330U_D2E_2.5VM_R9

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

+2.5VS

C450
0.1U_0402_16V4Z

+ C511

C497

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

H22

C470
0.1U_0402_16V4Z

330U_D2E_2.5VM_R9

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

VCC_SYNC

C418
0.1U_0402_16V4Z

U6H

+VCCP

C416
0.1U_0402_16V4Z

+2.5VS
D

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Re v
A

401395
Date:

P, 01, 2005

Sheet
1

10

of

48

Strap Pin Table


CFG[3:17] have internal pull up

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

1
C99

1
C492

+
2

C495

1
+

2
330U_D2E_2.5VM_R9
B

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

+VCCP
+1.8V
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1 VCCSM_LF2
AJ1 VCCSM_LF1

CALISTOGA_FCBGA1466~D
PM@

C105
0.47U_0603_10V7K

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C104
0.47U_0603_10V7K

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

Place near pin AV1 & AJ1

CFG[19:18] have internal pull down

011
001

C33
0.47U_0603_10V7K

C32
0.47U_0603_10V7K

CFG[2:0]

= 667MT/s FSB
= 533MT/s FSB

CFG5

0 = DMI x 2
1 = DMI x 4 *(Default)

CFG7

0 = Reserved
1 = Mobile Yonah CPU*(Default)

CFG9

0 = Lane Reversal Enable


1 = Normal Operation (Default)*

CFG11

(Acc ording to Intel Napa Schematic Checklist & CRB


Rev1.301 document 2.2Kohm pull-down resistor
r1e q u=e s tReserved
)

0 = Calistoga

Place near pin AT41 & AM41

00
01
10
11

CFG[13:12]
+1.8V

1
C452

0.1U_0402_16V4Z

P O W E R

VCCSM_LF4
VCCSM_LF5

C431

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

0.1U_0402_16V4Z

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

0.1U_0402_16V4Z

C466

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C481

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

0.1U_0402_16V4Z

C485

C435
1U_0603_10V4Z

10U_0805_6.3V6M

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C424

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

+1.8V

U6G

=
=
=
=

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

0 = Dynamic ODT Disabled


1 = Dynamic ODT Enabled *(Default)

CFG18

0 = 1.05V
1 = 1.5V

CFG19

0 = Normal Operation * (Default)


1 = DMI Lane Reversal Enable

*(Default)

0 = No SDVO Device Present *


(Default)
1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is


operational. *(Default)
1 = PCIE/SDVO are operating
simu.

CFG5
CFG7
CFG9

Place near pin BA23

CFG11
CFG12
C92

CFG16

SDVO_CTRLDATA

C54
0.47U_0603_10V7K

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

C475
0.22U_0603_10V7K

C467
0.22U_0603_10V7K

C454
0.22U_0603_10V7K

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

C52

CFG13
CFG16

2
10U_0805_6.3V6M

R513

2 @

2.2K_0402_5%

R507

2 @

2.2K_0402_5%

R509

2 @

2.2K_0402_5%

R514

2.2K_0402_5%

R512

2 @

2.2K_0402_5%

R510

2 @

2.2K_0402_5%

R506

2 @

2.2K_0402_5%

2 10U_0805_6.3V6M

+3VS
C71
0.47U_0603_10V7K

U6F

+VCCP

R479
R482
R490

CFG18
CFG19
CFG20

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

1
1
1

Place near pin BA15

CALISTOGA_FCBGA1466~D
A

PM@

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

11

of

48

U6I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

U6J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

CALISTOGA_FCBGA1466~D
PM@

CALISTOGA_FCBGA1466~D
A

PM@

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

12

of

48

+1.8V

+1.8V
V_DDR_MCH_REF

DDR_A_DQS#[0..7]

Layout Note:
Place near JP27

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_D21
DDR_A_D17

C78

C64

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C87

0.1U_0402_16V4Z

C65

C89

0.1U_0402_16V4Z

C56

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C72

2.2U_0805_16V4Z

C95

2.2U_0805_16V4Z

C59

2.2U_0805_16V4Z

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19

DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA
DDR_A_BS#2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_BS#0
DDR_A_WE#

+0.9VS

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_D34
DDR_A_D38

DDR_A_DQS#4
DDR_A_DQS4

C478

C477

C476

C474

C472

C468

C463

C91

C85

C79

C73

C70

C62

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

M_ODT1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
+0.9VS

DDR_A_MA5
DDR_A_MA8

RP34
1
2

DDR_A_MA1
DDR_A_MA3

RP35 56_0404_4P2R_5% RP8


1
4
4
2
3
3

4
3

Layout Note:
Pla ce these resistor
closely JP27,all
trace length Max=1.5"

RP32 56_0404_4P2R_5%
4
1 DDR_A_BS#2
3
2 DDR_CKE0_DIMMA

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D55

56_0404_4P2R_5%
1 DDR_A_MA7
2 DDR_A_MA6

DDR_A_D56
DDR_A_D61
DDR_A_DM7

RP17 56_0404_4P2R_5% RP33 56_0404_4P2R_5%


DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10

RP36 56_0404_4P2R_5% RP11 56_0404_4P2R_5%


1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2

DDR_A_CAS#
DDR_A_WE#

RP37 56_0404_4P2R_5% RP14 56_0404_4P2R_5%


1
4
4
1 DDR_A_MA0
2
3
3
2 DDR_A_BS#1

DDR_A_D58
DDR_A_D59
CLK_SMBDATA
CLK_SMBCLK

+3VS
C126

RP38 56_0404_4P2R_5% RP20 56_0404_4P2R_5%


DDR_CS1_DIMMA# 2
3
4
1 M_ODT0
M_ODT1
1
4
3
2 DDR_A_MA13
56_0404_4P2R_5% RP5
4
3

CLK_SMBDATA
CLK_SMBCLK

0.1U_0402_16V4Z

56_0404_4P2R_5%
1 DDR_CKE1_DIMMA
2 DDR_A_MA11

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

PTI_A5652D-A0G16-P

SO-DIMM A

DDR_A_DM0
DDR_A_D5
DDR_A_D6

2005/06/01

M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D9
DDR_A_D15

DDR_A_D20
DDR_A_D16
DDR_A_DM2
DDR_A_D18
DDR_A_D23
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0

DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6
DDR_A_D50
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_A_DM1

2006/06/01

Deciphered Date

DDR_A_D12
DDR_A_D13

Compal Secret Data

Security Classification
Issued Date

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

V_DDR_MCH_REF

R101
10K_0402_5%
2
1

DDR_A_D8
DDR_A_D14

DDR_A_D7
DDR_A_D1

R104
10K_0402_5%
2
1

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C17

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_MA[0..13]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C11

DDR_A_D0
DDR_A_D4

DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JP19

DDR_A_D[0..63]

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

13

of

48

+1.8V

DDR_B_DQS#[0..7]

+1.8V

DDR_B_D[0..63]

V_DDR_MCH_REF

DDR_B_DM[0..7]

DDR_B_D10
DDR_B_D11

220U_D2_4VM

C82

C66

0.1U_0402_16V4Z

C75

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C67

0.1U_0402_16V4Z

C84

C94

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C97

2.2U_0805_16V4Z

C58

C60

2.2U_0805_16V4Z

2.2U_0805_16V4Z

1
+ C415
2

220U_D2_4VM

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_B_D21
DDR_B_D20

1
+ C106

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9VS

DDR_B_CAS#
DDR_CS3_DIMMB#
1

M_ODT3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36

2
C98

C90

C86

C80

C74

C69

C63

C96

C88

C83

C76

C68

C61

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_BS#0
DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D47

+0.9VS

DDR_B_MA1
DDR_B_MA3

RP15
1
2

DDR_B_BS#0
DDR_B_MA10

RP18 56_0404_4P2R_5% RP6


1
4
4
2
3
3

DDR_B_MA0
DDR_B_BS#1

RP16 56_0404_4P2R_5% RP13 56_0404_4P2R_5%


DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

4
3

4
3

RP10 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

RP19 56_0404_4P2R_5% RP9


DDR_B_RAS#
1
4
4
DDR_CS2_DIMMB# 2
3
3

DDR_B_D48
DDR_B_D53

Layout Note:
Pla ce these resistor
closely JP26,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50

56_0404_4P2R_5% 5/16
DDR_B_MA7
1
DDR_CKE3_DIMMB
2

DDR_B_D60
DDR_B_D61
DDR_B_DM7
DDR_B_D58
DDR_B_D59

56_0404_4P2R_5% 5/16
DDR_B_MA6
1
DDR_B_MA11
2

CLK_SMBDATA
CLK_SMBCLK

+3VS

DDR_B_CAS#
DDR_B_WE#

56_0404_4P2R_5% RP7
4
3

1
2

C127
0.1U_0402_16V4Z

DDR_B_BS#2
DDR_CKE2_DIMMB

2005/06/01

Issued Date

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_D16
DDR_B_D18
DDR_B_DM2
DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
C

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

M_ODT2

DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

P-TWO_A5692B-A0G16-P

SO-DIMM B

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_D14
DDR_B_D15

R106
1

+3VS

10K_0402_5%
A

Compal Secret Data

Security Classification

56_0404_4P2R_5%

DDR_B_DM1

R103

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

10K_0402_5%

RP21 56_0404_4P2R_5% RP12 56_0404_4P2R_5%


DDR_B_MA4
1
4
4
1
DDR_B_MA2
2
3
3
2
RP23
56_0404_4P2R_5% RP22 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT2
3
4
1
M_ODT3
DDR_B_MA13
1
4
3
2

CLK_SMBDATA
CLK_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D12
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D6
DDR_B_D2

DDR_B_D8
DDR_B_D9

DDR_B_DM0

C18

DDR_B_D7
DDR_B_D3

Layout Note:
Place near JP26

DDR_B_D4
DDR_B_D1

C12

DDR_B_DQS#0
DDR_B_DQS0
D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D5

DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_B_DQS[0..7]

V_DDR_MCH_REF

JP20

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

14

of

48

+CK_VDD_MAIN1

1
R235

+3VS

2
0_0805_5%

C193
10U_0805_10V4Z

C185
0.1U_0402_16V4Z

C535
0.1U_0402_16V4Z

C166

FSLC

FSLB

FSLA

0.1U_0402_16V4Z

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

+CK_VDD_MAIN2

2
0_0805_5%

C142

C147

R125
1
2
1_0805_1%

10U_0805_10V4Z

+CK_VDD_DP
R127
1
2
0_0805_5%

+3VS

0.1U_0402_16V4Z

C165
10U_0805_10V4Z

C182
0.1U_0402_16V4Z

C536
0.1U_0402_16V4Z

22P_0402_50V8J 1

C537
0.1U_0402_16V4Z
C168
1

2 C157

1
C194

CLK_Rd

CLK_48M_ICH
CLK_48M_CB

20

2
1
R588
1K_0402_5%

CLK_Rb

R586

Reserve for ICS954305 & R need change to 475ohm

CLK_Re

REF0/FSLC/TEST_SEL

R EF1

PCI_ ICH

+VCCP

2
B

R159
@
8.2K_0402_5%
2
1

R580

1K_0402_5%

R148
1K_0402_5%

CLK_Rc

2.2K_0402_5%
Q37
2N7002_SOT23

MCH_CLKSEL2

ICH_SMBDATA

2.2K_0402_5%

CLK_SMBDATA

R581

R150

2
G

1
R157
0_0402_5%

CPU_BSEL2

F SC

0_0402_5%

CLK_Rf

32

SEL_24M/PCICLK2

SRCCLKC8LP

69

27

SEL_PCI6/PCICLK1

ICH_SMBCLK

CLKREQ7#

SRCCLKC6LP

64

VTT_PWRGD#/PD

CLKREQ6#

62

SRCCLKT5LP

60

SRCCLKC5LP

61

CLKREQ5#/PCICLK6

29

SRCCLKT4LP

58

SRCCLKC4LP

59

GND

SMBCLK
CLKREQ4#

57

SRCCLKT3LP

55

SMBDAT

GNDSRC

SRCCLKC3LP

56

15

GNDCPU

CLKREQ3#/PCICLK5

28

21

GNDREF

SRCCLKT2LP

52

31

GNDPCI

SRCCLKC2LP

53

35

GNDPCI

CLKREQ2#

26

42

GND48

SRCCLKT1LP

50

68

GNDSRC

SRCCLKC1LP

51

CLKREQ1#

46

LCD100/96/SRC0_TLP

47

LCD100/96/SRC0_CLP

48

1
R151
1
R143
2
R594

+3VS

+3VS

+3VS

1:48M *0:CLKREQ7#
for Pin 38

+3VS

1 2

R208

MCH_3GPLL

1
R167
MCH_3GPLL# 1
R160
CLKREQ5#
2
R172
1
R182
1
R178
2
R189
P CIE_ICH
1
R201
PCIE_ICH#
1
R196
PCI_CLK5
1
R186
1
R214
1
R215
CLKREQ2#
2
R171
1
R212
1
R213
CLKREQ1#
1
R210
1
R211

CLK_PCIE_SATA
0_0402_5%
CLK_PCIE_SATA#
0_0402_5%
SATA_CLKREQ#
1
0_0402_5%

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
2
0_0402_5%
CLK_MCH_3GPLL#
2
0_0402_5%
MCH_CLKREQ#
1
0_0402_5%
2
0_0402_5%
2
0_0402_5%
MINI_CLKREQ#
1
0_0402_5%
CLK_PCIE_ICH
2
0_0402_5%
CLK_PCIE_ICH#
2
0_0402_5%
2 0_0402_5%
CLK_PCIE_LAN
0_0402_5%
CLK_PCIE_LAN#
0_0402_5%
LAN_CLKREQ#
1
0_0402_5%
CLK_PCIE_VGA
2
0_0402_5%
CLK_PCIE_VGA#
2
0_0402_5%

10K_0402_5%
PCI_EC

1
R199

10K_0402_5%

PCI_PCM

10K_0402_5%1

for Pin 6,5

CLK_CPU_BCLK# 2 @
R121

1
49.9_0402_1%
1
49.9_0402_1%

@
CLK_MCH_BCLK 2
R122
CLK_MCH_BCLK# 2 @
R123

1
49.9_0402_1%
1
49.9_0402_1%

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

10K_0402_5%

R141 1

R EF1

R589 2

SATA_CLKREQA#

10K_0402_5% 1

R181 2

CLKREQC#

10K_0402_5% 1

R190 2

CLKREQD#

CLK_PCIE_MCARD
CLK_PCIE_MCARD#
MINI_CLKREQ#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCI_TCG

CLK_PCIE_LAN#

2
49.9_0402_1%
2
49.9_0402_1%

@
CLK_PCIE_VGA
1
R228
CLK_PCIE_VGA# 1 @
R229

2
49.9_0402_1%
2
49.9_0402_1%

@
CLK_PCIE_SATA 1
R152
CLK_PCIE_SATA# 1 @
R144

2
49.9_0402_1%
2
49.9_0402_1%

CLK_PCIE_LAN

CLK_MCH_3GPLL 1
R168
CLK_MCH_3GPLL# 1 @
R161

2
49.9_0402_1%
2
49.9_0402_1%

@
CLK_PCIE_MCARD 1
R183
CLK_PCIE_MCARD#1 @
R179

2
49.9_0402_1%
2
49.9_0402_1%

@
1
R202
CLK_PCIE_ICH#
1 @
R197

2
49.9_0402_1%
2
49.9_0402_1%

CLK_PCIE_ICH

2005/06/01

Issued Date

for Pin 43,44/47,48


1:27M/SRC0 *0:DOT 96M/LCD100

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_GMCH
0_0402_5%
CLK_PCIE_GMCH#
0_0402_5%

MCH_SSCDREFCLK

CLK_MCH_DREFCLK 1
R224
CLK_MCH_DREFCLK#1 @
R225
CLK_PCIE_LAN
1 @
R230
CLK_PCIE_LAN# 1 @
R231

2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%

MCH_SSCDREFCLK#

CLKREQ7#

R595 1@

10K_0402_5%

CLKREQ1#

R592 1@

10K_0402_5%

CLKREQ2#

R164 1@

10K_0402_5%

CLKREQ5#

R173 1@

10K_0402_5%

PCI_CLK5

R180 1@

10K_0402_5%

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LAN_CLKREQ#

Compal Secret Data

Security Classification

MCH_CLKREQ#

CLK_PCIE_GMCH 1
R226
CLK_PCIE_GMCH# 1 @
R227

R206
10K_0402_5%

1:CPU ITP *0:SRC 10

SATA_CLKREQ#

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Place these components


near each pin within 40
mils.

Reserve for ICS954305

*1:PCICLK3 for Pin28

PCI_MINI
R200

10K_0402_5%

J10
NO SHORT PADS

@ 10K_0402_5%

300_0402_5%

10K_0402_5%

CLK_CPU_BCLK#

+3VS

10K_0402_5%2

R216

PCI_ ICH

R222

10K_0402_5%

R217

R193

R238

CLK_ENABLE#

CLK_CPU_BCLK

R239
@ 10K_0402_5%

CLK_MCH_BCLK#

ICS9LPR325AKLFT_MLF72

1:24M *0:test Mode


for Pin 45

PCIE_SATA#

38

0.1U_0402_16V4Z

CLK_MCH_BCLK

PCIE_SATA

63

C167

CLK_CPU_BCLK
2
R120

67

SRCCLKT6LP

ITP_EN/PCICLK_F0

CLK_CPU_BCLK
2
0_0402_5%
CLK_CPU_BCLK#
2
0_0402_5%

1
R130
CPU_BCLK# 1
R131

SRCCLKC7LP

DOTC_96MHz/27MHz_spread

39

CPU_BCLK

71

DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1

37

CLK_MCH_BCLK
2
0_0402_5%
CLK_MCH_BCLK#
2
0_0402_5%

66

44

CLK_SMBCLK

2N7002_SOT23
Q38

+3VS

H_STP_CPU#

1
R132
MCH_BCLK# 1
R133

CLKREQ8#

43

+3VS

H_STP_PCI#

MCH_BCLK

SRCCLKT7LP
SEL_PCI5/REF1

2
G

SRCCLKT8LP

17

R149

SEL_48M/PCICLK3

16

+3VS

SRCCLKC9LP

72

0_0402_5%

CLK_SMBDATA

CLK_SMBDATA

70

SRCCLKT9LP

CLKREQ9#

PCICLK4/FCTSEL1

22

CLK_SMBCLK

CLK_SMBCLK

13

X2

R119

0_0402_5%

CPUCLKC0LP

23

CLK_ENABLE#

CLK_EN#

14

F SC

1
2 MCH_DREFCLK
R218 GM@
33_0402_5%
CLK_MCH_DREFCLK# 1
2 MCH_DREFCLK#
R219 GM@
33_0402_5%
2 R207
1
33_0402_5%

CPUCLKT0LP

CLK_MCH_DREFCLK

CLK_PCI_ICH

10

FSLB/TEST_MODE/24Mhz

1 12_0402_5%
1 R165

CLK_PCI_ICH

CPUCLKC1LP

45

R158
2
@ 10K_0402_5%
2

1
33_0402_5%

11

CPUCLKT2_ITP/SRCCLKT10LP

PCI_MINI

2
R142

CPUCLKT1LP

USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP

1 R187

MCH_CLKSEL1

H_STP_CPU#

41

33_0402_5% 2

CLK_MCH_DREFCLK#

24

FSB

CLK_PCI_USB20

1
R593
0_0402_5%

CPU_BSEL1

33.3

+VDDAD

CPU_STOP#

FSA

CLK_PCI_EC

CLK_MCH_DREFCLK

1K_0402_5%

33.3

100

+3VS

H_STP_PCI#

33

CLK_14M_SIO

X1

19

34

2
R587

VDD48

PCI_EC

CLK_14M_SIO

40

PCI_PCM

CLK_PCI_SIO

FSB

CK_VDD_48

1 R188

*0:CLKREQ5# for Pin 29

+VCCP

GNDA

+VDDAD

25

0.1U_0402_16V4Z

33_0402_5% 2

1K_0402_5%

VDDREF

R209 12_0402_5%
2
1
2
1
R223
12_0402_5%

VDDCPU

18

CLK_14M_ICH 2
1
R166
33_0402_5%
Reserve for ICS954305
@ 33_0402_5% 2
1 R192
CLK_PCI_TCG
33_0402_5% 2
1 R194
CLK_PCI_PCM

R598
@

12

CLK_14M_ICH

100

166

CK_VDD_REF

CLK_XTAL_OUT

MCH_CLKSEL0

R599
1K_0402_5%

CLK_Ra
C

2
C158

CLK_48M_ICH
CLK_48M_CB

1
1

VDDA

R126
2
1
0_0805_5%

PCI_SRC_STOP#
VDDPCI
VDDPCI

CLK_XTAL_IN

2
R602
8.2K_0402_5%
FSA 2
1

22P_0402_50V8J

VDDSRC
VDDSRC
VDDSRC
VDDSRC

30
36

0.1U_0402_16V4Z

Y1
14.31818MHZ_20P_6X1430004201
R601
56_0402_5%

133

1
49
54
65

5/20

+VCCP

1
R603
0_0402_5%

U9

2 CK_VDD_48
R124
2.2_0805_1%

0.1U_0402_16V4Z

+CK_VDD_MAIN1

CPU_BSEL0

+CK_VDD_DP

C146

PCI
MHz

CK_VDD_REF

1
R129

+3VS

SRC
MHz

Size

Document Number

R ev
A

401395
Date:

, ?01, 2005

Sheet

15

of

48

CRT Connector

R29

2
GM@

2
GM@

4
7
9
12

0_0402_5%

R30

2
GM@

CRT_G

R441

R21

0.1U_0402_16V4Z

CRT_R
WOD@ 0_0402_5%
2 CRT_G
WOD@ 0_0402_5%
2 CRT_B
WOD@ 0_0402_5%

1
C364

2
0.1U_0402_16V4Z

2
R433

P
OE#

VGA_CRT_HSYNC

39_0402_5%

C365

D_CRT_HSYNC

C357

2
C369

6P_0402_50V8K
6P_0402_50V8K
2
2
2
6P_0402_50V8K

1
10K_0402_5%

1
C366

C368

DSUB_12_DATA
220P_0402_50V7K

2
@ 6P_0402_50V8K

@ 6P_0402_50V8K
2

DSUB_15_CLK

2 @ 6P_0402_50V8K

2
GM@

39_0402_5%

VGA_CRT_VSYNC

C356

68P_0402_50V8K 68P_0402_50V8K

5
1

2
0.1U_0402_16V4Z

1
C367

D_CRT_HSYNC

U37
SN74AHCT1G125GW_SOT353-5

P
OE#

1
C370

TYCO_1470801-1

C361

+5VS
2

1
R39

JP15

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

DVI_B

L11
1
2
FCM2012C-800_0805

CRT_B

5
1

1
C375

GMCH_CRT_VSYNC

1
2
FCM2012C-800_0805

150_0402_1%

150_0402_1%

GM@

CRT Conn.

CH491D_SC59 POLYSWITCH_1A
1
C360

DVI_G

L10

+5VS

DAN217_SC59
@

L13
1
2
FCM2012C-800_0805

CRT_R

150_0402_1%

1
R38

+CRT_VCC
F1

D VI_R

CRT_B

R9

GMCH_CRT_HSYNC

DAN217_SC59
@

CRT_G

FSAV330MTC_TSSOP16

Close to VGA conn.

Pop with No-Docking

DAN217_SC59
@

2
+3VS

D_CRT_R
D_CRT_G
D_CRT_B

GND

W D@

D28

D_CRT_R
D_CRT_G
D_CRT_B

+R_CRT_VCC
D25

D27

CRT_R

0_0402_5%
0_0402_5%

+5VS
D29

3
6
10
13

Near to JP45

CRT CONNECTOR
2

1B2
2B2
3B2
4B2

1A
2A
3A
4A

VGA_CRT_B
GMCH_CRT_B

2
5
11
14

2 470_0402_1%
2 470_0402_1%
2 470_0402_1%

VGA_CRT_G
GMCH_CRT_G

16

1B1
2B1
3B1
4B1

R28

VCC
SEL
OE#

R6
1
R18 1
R434 1

W D@

VGA_CRT_R
GMCH_CRT_R

1
15

2 0.1U_0402_16V4Z

DOCKIN#

DOCKIN#

D_CRT_R
D_CRT_G
D_CRT_B

1
C376

U3

VGA_CRT_R
1
R16
VGA_CRT_G
1
R22
VGA_CRT_B
1
R448

Match with Docking resistor to 150ohm


+5VS

D_CRT_VSYNC

D_CRT_VSYNC

D_CRT_HSYNC 1
L12

2
FCM1608C-121T_0603

D_CRT_VSYNC 1
L9

2
FCM1608C-121T_0603

U36
SN74AHCT1G125GW_SOT353-5

VSYNC

C363
10P_0402_50V8J

Close to VGA conn.

HSYNC

C358
10P_0402_50V8J

+5VS

0_0402_5%GM@
1

R27
2

R431

4.7K_0402_5%
1

DSUB_12_DATA

+3VS

Q32
BSS138_SOT23

VGA_DDC_DATA

VGA_DDC_DATA

R430
4.7K_0402_5%

R427

GMCH_CRT_DATA

0_0402_5%

+3VS

DSUB_15_CLK

VGA_DDC_DATA

2
R26
0_0402_5% GM@

2
0_0402_5% PM@

Close to VGA conn.

R432

2 C133
@ 22P_0402_50V8J

VGA_TV_LUMA

1
2
FBM-11-160808-121T_0603

L1

1
2
FBM-11-160808-121T_0603

2
GM@

0_0402_5%

1
R35

L2
0_0402_5%

R113

VGA_DDC_CLK

150_0402_1%

150_0402_1%

C128
100P_0402_25V8K

CRMA_1
LUMA_1

2 C130
@ 22P_0402_50V8J

C140
100P_0402_25V8K

C131

C132

4
3
2
1

4
3
2
1

6
5

1.
2.
3.
4.

6
5

D_DDC_CLK

D_DDC_CLK

Q30
BSS138_SOT23 GM@

TV-OUT
Conn.
JP23

R107

Close to VGA conn.

2
GM@

1
R34

VGA_TV_CRMA
GMCH_TV_CRMA

D_DDC_DATA

+3VS

GMCH_TV_LUMA

D_DDC_DATA

Q33
BSS138_SOT23 GM@

GMCH_CRT_CLK

Q31
BSS138_SOT23

3
S

VGA_DDC_CLK

VGA_DDC_CLK

Y
C
Y
C

ground
ground
(luminance+sync)
(crominance)

2
0_0402_5% PM@

R428

ALLTO_C10877-104A1-L_4P
100P_0402_25V8K

100P_0402_25V8K

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

16

of

48

+3VS

VGA BOARD Conn.

LCD POWER CIRCUIT

R33
D2

2PM@ 0_0402_5%

GMCH_ENVDD

R15

2GM@

BKOFF#

5
1

U4

PCIE_MTX_C_GRX_P[0..15]

4
2

PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

1
R25
300_0402_5%

2
1

1 2

R7

100_0402_5%

PCIE_MTX_C_GRX_N[0..15]

2
R14

PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]
+2.5VS
VGA_LCD_CLK
VGA_LCD_DATA
VGA_TZCLKVGA_TZCLK+

+LCDVDD
VGA_TZOUT0VGA_TZOUT0+

C386

100K_0402_5%

0.047U_0402_16V7K

C404
4.7U_0805_10V4Z

VGA_TZOUT1VGA_TZOUT1+

C389

VGA_TZOUT2VGA_TZOUT2+

0.1U_0402_16V4Z

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

LCD/PANEL BD. Conn.


B+

PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

B+
JP3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

DISPOFF#
+LCDVDD
LCD_DATA
TXCLK+
TXCLK-

2
C45
4.7U_0805_10V4Z

TXOUT2+
TXOUT2TXOUT1TXOUT1+
TXOUT0TXOUT0+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+1.5VS

AO3413_SOT23

2
1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

PCIE_MTX_C_GRX_P[0..15]

Q35

2
G

B+

DISPOFF#

+3VS

PCIE_MTX_C_GRX_N[0..15]

SN74AHCT1G125GW_SOT353-5

P
OE#

2
1
C7
0.01U_0402_16V7K

2
RB751V_SOD323

+LCDVDD

Q4
2N7002_SOT23

0_0402_5%

+3VALW

BKOFF#

JP18

4.7K_0402_5%

R3

GMCH_ENVDD

VGA_ENVDD

DAC_BRIG
INVT_PWM

DAC_BRIG
INVT_PWM

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2

+3VS

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

LCD_CLK
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

TZCLKTZCLK+

C378
TZOUT1TZOUT1+
TZOUT2+
TZOUT2TZOUT0+
TZOUT0-

0.1U_0402_16V4Z

PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

ACES_88242-3000

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11
LCD_CLK
LCD_DATA
B

0_0402_5%
2
2
0_0402_5%

PM@
1
1
PM@

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

R449 VGA_LCD_CLK
R450 VGA_LCD_DATA

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

TXOUT0TXOUT0+

R461 1
R460 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TXOUT0VGA_TXOUT0+

TZOUT0TZOUT0+

R440 1
R439 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TZOUT0VGA_TZOUT0+

TXOUT1TXOUT1+

R463 1
R462 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TXOUT1VGA_TXOUT1+

TZOUT1TZOUT1+

R435 1
R436 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TZOUT1VGA_TZOUT1+

TXOUT2TXOUT2+

R464 1
R468 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TXOUT2VGA_TXOUT2+

TZOUT2TZOUT2+

R438 1
R437 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TZOUT2VGA_TZOUT2+

TXCLKTXCLK+

R469 1
R471 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TXCLKVGA_TXCLK+

TZCLKTZCLK+

R451 1
R452 1

2PM@ 0_0402_5%
2PM@ 0_0402_5%

VGA_TZCLKVGA_TZCLK+

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15
CLK_PCIE_VGA
CLK_PCIE_VGA#
VGA_CRT_R
VGA_CRT_G

LCD_CLK
LCD_DATA

0_0402_5%
2
2
0_0402_5%

GM@
1
1
GM@

VGA_CRT_B
R457 GMCH_LCD_CLK
R458 GMCH_LCD_DATA

GMCH_LCD_CLK
GMCH_LCD_DATA

TXOUT0TXOUT0+

R45
R44

1
1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TXOUT0GMCH_TXOUT0+

TXOUT1TXOUT1+

R47
R46

1
1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TXOUT1GMCH_TXOUT1+

TXOUT2TXOUT2+

R48
R49

1
1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TXOUT2GMCH_TXOUT2+

TXCLKTXCLK+

R50
R51

1
1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TXCLKGMCH_TXCLK+

PLT_RST#
SUSP#
VGA_ENBKL

TZOUT0TZOUT0+

R447 1
R446 1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TZOUT0GMCH_TZOUT0+

TZOUT1TZOUT1+

R442 1
R443 1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TZOUT1GMCH_TZOUT1+

TZOUT2TZOUT2+

R445 1
R444 1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TZOUT2GMCH_TZOUT2+

TZCLKTZCLK+

R454 1
R455 1

2GM@ 0_0402_5%
2GM@ 0_0402_5%

GMCH_TZCLKGMCH_TZCLK+

CLK_PCIE_VGA
CLK_PCIE_VGA#
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
SUSP#
VGA_ENVDD
VGA_ENBKL

DVI_TXC+
DVI_TXCDVI_TXD0+
DVI_TXD0-

+3VS
+5VS
VGA_TXCLKVGA_TXCLK+
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
VGA_DDC_CLK
VGA_DDC_DATA

VGA_DDC_CLK
VGA_DDC_DATA

VGA_TV_LUMA

VGA_TV_LUMA

VGA_TV_CRMA

VGA_TV_CRMA

VGA_CRT_VSYNC
VGA_CRT_HSYNC

VGA_CRT_VSYNC
VGA_CRT_HSYNC
DVI_DET#
DVI_SCLK
DVI_SDATA
DVI_TXD1+
DVI_TXD1DVI_TXD2+
DVI_TXD2-

Compal Secret Data


2005/06/01

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

ACES_88386-1K71

Security Classification

+1.8VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

R ev
A

401395
Date:

, 01, 2005

Sheet
1

17

of

48

+3VS

2 8.2K_0402_5%

PCI_PLOCK#

R343 1

2 8.2K_0402_5%

PCI _IRDY#

R334 1

2 8.2K_0402_5%

PCI_SERR#

R622 1

2 8.2K_0402_5%

PCI_PERR#

R325 1

2 8.2K_0402_5%

PCI_REQ4#

R618 1

2 8.2K_0402_5%

PCI_REQ3#

U21B

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS

R355 1

2 8.2K_0402_5%

PCI_PIRQA#

R352 1

2 8.2K_0402_5%

PCI_PIRQB#

R348 1

2 8.2K_0402_5%

PCI_PIRQC#

R346 1

2 8.2K_0402_5%

PCI_PIRQD#

R630 1

2 8.2K_0402_5%

PCI_PIRQE#

R646 1

2 8.2K_0402_5%

PCI_PIRQF#

R634 1

2 8.2K_0402_5%

PCI_PIRQG#

R650 1

2 8.2K_0402_5%

PCI_PIRQH#

R643 1

2 8.2K_0402_5%

PCI_REQ0#

R306 1

2 8.2K_0402_5%

PCI_REQ1#

R303 1

2 8.2K_0402_5%

PCI_REQ2#

R624 1

2 8.2K_0402_5%

PCI_REQ5#

R318 1

2 8.2K_0402_5%

ICH_GPIO48

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI

PLTRST#
PCICLK
PME#

Interrupt

A3
B4
C5
B5

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AE5
AD5
AG4
AH4
AD9

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

PCI_REQ1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2#
PCI_GNT2#

PCI_REQ4#
ICH_GPIO48
PCI_REQ5#

+3VS
5

PCI_FRAME#

R619 1

PCI_PCIRST#

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

U18

2 8.2K_0402_5%

AE9
AG8
AH8
F21
AH20

PCI_RST#

PCI_RST#

PCI_TRDY#

R615 1

@ TC7SH08FU_SSOP5

PCI_IRDY#
PCI_PAR

2 8.2K_0402_5%

R299
0_0402_5%
1

PCI_DEVSEL#
PCI_PERR#

+3VS

PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_STOP#

R617 1

PCI_PLTRST#

U17

PCI_DEVSEL#

2 8.2K_0402_5%

PLT_RST#

PLT_RST#

2 8.2K_0402_5%

R616 1

CLK_PCI_ICH

TC7SH08FU_SSOP5

R328 1

R296
@ 0_0402_5%
2
1

MCH_ICH_SYNC#

Place closely pin A9

ICH7_BGA652~D

CLK_PCI_ICH
B

R336

@10_0402_5%

C254
@ 8.2P_0402_50V

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

18

of

48

1 10P_0402_50V8K

+5V_SATA

JP26

NC

IN

R386

NC

OUT

10M_0402_5%

CS
SK
DI
DO

33_0402_5% 1

2 R384

33_0402_5% 1

2 R380

33_0402_5% 2

1 R368

W1
Y1
Y2
W3

AT93C46-10SI-2.7_SO8
LCI_CLK
LCI_RSTSYNC
LCI_RXD0
LCI_RXD1
LCI_RXD2
LCI_TXD0
LCI_TXD1
LCI_TXD2

33_0402_5% 1

2 R381

ACZ_BITCLK
ACZ_S YNC

33_0402_5% 2

1 R369

ACZ_RST#
ICH_AC_SDIN0
ACZ_SDIN1
33_0402_5% 2

ICH_SDOUT_AUDIO

33_0402_5% 2

ACZ_SDOUT_MDC
PHDD_LED#

1
R621

R311

AB3

LPC_FRAME#

U3

LAN_RSTSYNC

U5
V4
T5

LAN_RXD0
LAN_RXD1
LAN_RXD2

U7
V6
V7

LAN_TXD0
LAN_TXD1
LAN_TXD2

U1
R6

ACZ_BCLK
ACZ_SYNC
ACZ_RST#

ACZ_SDIN0
ACZ_SDIN1

T2
T3
T1

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

T4

ACZ_SDOUT

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

20K_0402_5%

332K_0402_1%

R333
R623

@ 0_0402_5%

AE22
AH28
AG27

H_CPUSLP_R#

TP1 / DPRSTP#
TP2 / DPSLP#

AF24
AH25

FERR#

AG26

GPIO49 / CPUPWRGD

AG24

H_PW RGOOD

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#

RCIN#

AG23

R274 2
EC_KBRST#

SMI#
NMI

AF23
AH24

H_SMI#
H_NMI

STPCLK#

AH22

H_STPCLK#

THERMTRIP#

AF26

THRMTRIP_ICH#

DA0
DA1
DA2

AH17
AE17
AF17

PD_A0
PD_A1
PD_A2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

DCS1#
DCS3#

AE16
AD16

PD_CS#1
PD_CS#3

AF7
AE7
AG6
AH6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

DDREQ

AE15

PD_DREQ

SATA_CLKN
SATA_CLKP

AH10
AG10

SATARBIASN
SATARBIASP

AG16
AH16
AF16
AH15
AF15

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

24.9_0402_1%

+3VS

4.7K_0402_5% 2
8.2K_0402_5% 2

1 R315
1 R304

PD_IO RDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

IDE

+3VS

T29

PAD

DPRSLP# R271 2
H_DPSLP#
R251 2
H_FERR#

SATALED#

AF3
AE3
AG2
AH2

CLK_PCIE_SATA# AF1
CLK_PCIE_SATA AE1

CLK_PCIE_SATA#
CLK_PCIE_SATA

ICH_INTVRMEN

A20GATE
A20M#

1 R279 10K_0402_5%
EC_GA20
H_A20M#

1 0_0402_5%
1 56_0402_5%
H_FERR#

H_DPRSTP#
H_DPSLP#
+VCCP

3900P_0402_50V7K
SATA_TXN0
2

3900P_0402_50V7K
SATA_TXP0
2

C279
SATA_TXP0_C

H_INIT#
H_INTR

H_INIT#
H_INTR

3900P_0402_50V7K
SATA_RXN0
2

H_SMI#
H_NMI
H_STPCLK#

3900P_0402_50V7K
SATA_RXP0
2

C221
SATA_RXP0_C

C270
R345
10K_0402_5%

10U_0805_10V4Z

Q23
DTC124EK_SC59

IDE_RESET#

Place component's closely IDE CONN.

***Must be placed close to AF26 pin within 2"

C293
10U_0805_10V4Z

C290

C289

C281

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2
2
2

ODD CONN

C179

CD_AGND
10U_0805_10V4Z

CD_AGND

JP24

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
53

INT_CD_L
ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
PD_IOW#
PD_IO RDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
SHDD_LED#

R95
R93

1
2

SEC_CSEL
2
1@ 4.7K_0402_5%
470_0402_5%

INT_CD_R

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
54

INT_CD_R

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#
PD_DACK#
PDIAG#
R109 1
PD_A2
PD_CS#3
W=80mils

100K_0402_5%

+5VS

+5VS
+5VS
+5VS

C524 0.1U_0402_16V4Z

OCTEK_CDR-50JD1

+5VS

+RTCBATT

1
C518

1
C519

1
C520

1
C521

10U_0805_10V4Z
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z
2

D17

Place component's closely ODD CONN.

BAS40-04_SOT23

+CHGRTC

+3VALW

PLT_RST#

PLT_RST# 1

C310
0.1U_0402_16V4Z

ODDRST#

+RTCVCC

2
R391

2005/06/01

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

ODD_RST#

TC7SH08FU_SSOP5

1
33_0402_5%

Compal Secret Data

Security Classification
Issued Date

U32

Y
@

C274
0.1U_0402_16V4Z

Reserve for test

+RTCBATT

45@ RTCBATT

Near Device side.

+5V_IDE

H_THERMTRIP#

RTC Battery

Q24

1U_0603_10V4Z

+5VS
+5VS

AOS 3401_SOT23

C275
1
2

+5V_SATA

+5VS

1 R266
2
24.9_0402_1%

10K_0402_5%

BATT1

2
240K_0402_5%

56_0402_5%

+3VS

1
R351

+5VS

+5VS

JUMP_43X118

SHDD_LED#

C219

+3VS

R267

+5VS

SATA_RXN0_C

+3VS +VCCP

1 10K_0402_5%
EC_KBRST#

R108

Near ICH7 side.

SUYIN_127043FB022G208ZR_22P_RV

H_IGNNE#

C282

H_PW RGOOD

ICH7_BGA652~D
SATA_TXN0_C

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

LPC_FRAME#

EC_GA20
H_A20M#

J4

LPC_DRQ#0
LPC_DRQ#1

CPUSLP#

1 R370
1

LAN_CLK

R5

R620

@ 332K_0402_1%

LFRAME#

SATA

+RTCVCC

V3

AF18
+3VS

+3VALW

1 R371

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

EEP_CS
EEP_SK
EEP_DOUT
EEP_DIN

1
2
3
4

AC-97/AZALIA

ICH_RST_AUDIO#

LPC_DRQ#0
LPC_DRQ#1

JUMP_43X118

2
@
0.1U_0402_16V4Z

VCC
NC
NC
GND

R649
1
2
@ 10_0402_5%
@ 10P_0402_25V8K
33_0402_5% 1
2 R383

ACZ_RST#_MDC

AC3
AA5

SATA_RXN0
SATA_RXP0

8
7
6
5

C602
2
1

ICH_SYNC_AUDIO

LDRQ0#
LDRQ1# / GPIO23

CPU

C283

ACZ_SYNC_MDC

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

INTVRMEN
INTRUDER#

AA6
AB5
AC4
Y6

+5VS

J6

RTCRST#

ICH_INTVRMEN W4
SM_INTRUDER# Y5

LAD0
LAD1
LAD2
LAD3

LAN

C498
1U_0603_10V4Z
1
2

ICH_BITCLK_AUDIO

RTXC1
RTCX2

U31

SHORT PADS

1
2
1M_0402_5%

+RTCVCC

+3VALW

AB1
AB2

SATA_TXP0
SATA_TXN0

R641

CMOS_CLR1
1
2

ACZ_BITCLK_MDC

ICH_RTCX2

LPC_AD[0..3]

ICH_RTCRST# AA3

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

2
+RTCVCC
D

1 10P_0402_50V8K

@ JUMP_43X118
U21A

RTC

C291
R385 1
20K_0402_5%

Y2

+5V_IDE
J5

32.768KHZ_12.5P_1TJS125BJ2A251

ICH_RTCX1

LPC

C308

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

R ev
A

401395
Date:

, 01, 2005

Sheet
1

19

of

48

Place closely pin B2

CLK_14M_ICH

R269

SB_SPKR
SUS_STAT#
DBRESET#

PM_BMBUSY#

OCP#

OCP#

+3VS

IDE_RESET#
PCIE_WAKE#

8.2K_0402_5%
R297 1
2 PM_CLKRUN#

R365 2

BT_DET#

PM_CLKRUN#

PM_CLKRUN#

10K_0402_5%
R281 1
2 SIRQ

VGATE

R614

0_0402_5%
1
SIRQ
EC_THERM#

R276

100K_0402_5%

AB18

GPIO0 / BM_BUSY#

AC20
AF21

GPIO18 / STPPCI#
GPIO20 / STPCPU#

A21

GPIO26

B21
E23

GPIO27
GPIO28

AG18

GPIO32 / CLKRUN#

AC19
U2

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#
WAKE#
SERIRQ
THRM#

AD22

VRMPWRGD

AC21
AC18
E21

GPIO6
GPIO7
GPIO8

0_0402_5%

+3VA
EC_SMI#

EC_SMI#

GPIO

ICH7_BGA652~D

10K_0402_5%
R625 1
2

SPI_MOSI

10K_0402_5%
R382 1
2

SPI_MISO

R285 1

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

0.1U_0402_16V7K 2
0.1U_0402_16V7K 2

1 C201
1 C200

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

0.1U_0402_16V7K 2
0.1U_0402_16V7K 2

1 C203
1 C202

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

1K_0402_5%
SB_PCIE_WAKE#
2

F26
F25
E28
E27

PERn1
PERp1
PETn1
PETp1

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

R2
P6
P1

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

P5
P2

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
A

SPI

SPI_CS#

DIRECT MEDIA INTERFACE

SPI_CS#

ICH_SUSCLK

SUSCLK

C20
B24
D23
F22

PWROK

AA4

PWROK

AC22

DPRSLPVR

TP0 / BATLOW#

C21

ICH_LOW_BAT#

PWRBTN#

C23

PBTN_OUT#

LAN_RST#

C19

RSMRST#

Y4

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

@ 4.7P_0402_50V8C

USB

@ 4.7P_0402_50V8C

T31 PAD

PM_SLP_S3#
SLP_S4#
SLP_S5#

PM_SLP_S3#

PWROK
1
DPRSLPVR

R640
2 10K_0402_5%

DPRSLPVR 2

1
R284
100K_0402_5%

PBTN_OUT#
LAN_RST#

EC_RSMRST#
R645 10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

EC_SCI#

EC_RSMRST#

EC_SCI#

BT_DET#
EC_LID_OUT#

EC_FLASH#
SATA_CLKREQ#

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

DMI_ZCOMP
DMI_IRCOMP

C605

CLK_14M_ICH
CLK_48M_ICH

SLP_S3#
SLP_S4#
SLP_S5#

GPIO16 / DPRSLPVR

BT_DET#
EC_LID_OUT#
NVM_PORT
LAN_DISABLE#
ODDRST#
EC_FLASH#
SATA_CLKREQ#
+3VA
2 C187
0.1U_0402_16V4Z

U21D
PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCI-EXPRESS

10K_0402_5%
R626 1
2

CLK_14M_ICH
CLK_48M_ICH

AC1
B2

C313

R295
100_0402_5%
1
2

U11

10K_0402_5%
R264 1
2 OCP#

8.2K_0402_5%
R280 2
1 ICH_LOW_BAT#

CLK14
CLK48

AF19
AH18
AH19
AE19

Need update symbol

10K_0402_5%
R275 1
2 DBRESET#

8.2K_0402_5%
R245 1
2 EC_SWI#

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO11 / SMBALERT#

SB_PCIE_WAKE# F20
SIRQ
AH21
EC_THERM#
AF20

SPKR
SUS_STAT#
SYS_RST#

GPIO

SB_INT_FLASH_SEL#
@ 10K_0402_5%
R249 1
2 LINKALERT#

RI#

A19
A27
A22

B23

H_STP_PCI#
H_STP_CPU#

H_STP_PCI#
H_STP_CPU#

A28

SYS

PM_BMBUSY#

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

PM_SLP_S5#
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

EC_SWI#

EC_SWI#
SB_SPKR
SUS_STAT#
DBRESET#

1
C22
B22
A26
B25
A25

@ 10_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

R655

@ 10_0402_5%

SLP_S4#

2 0_0402_5%
2 0_0402_5%

SATA
GPIO

R272

Clocks

1
1

ICH_SMBCLK
ICH_SMBDATA

SMB

ICH_SMBCLK
ICH_SMBDATA

U21C

2.2K_0402_5%

POWER MGT

R268

10K_0402_5%

2.2K_0402_5%
10K_0402_5%

R367

SLP_S5#

TC7SH08FU_SSOP5

R273
R254

1
2

2
R256

+3VA
1

+3VA

Place closely pin AC1

CLK_48M_ICH

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

RP29
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

CLK_PCIE_ICH#
CLK_PCIE_ICH
R610 24.9_0402_1%
1
2

Within 500 mils

4
3
2
1

5
6
7
8

+3VA

10K_1206_8P4R_5%

+1.5VS

RP28
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

4
3
2
1

5
6
7
8

10K_1206_8P4R_5%

R656 22.6_0402_1%
1
2

Within 500 mils


A

ICH7_BGA652~D

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

20

of

48

+3VA

+3VALW
J8
2

+VCCP

0.1U_0402_16V4Z
+5VS

+3VS

C548

C547

C545

C209
R338

D14

ICH_V5REF_RUN
1

C579
0.1U_0402_16V4Z

0.1U_0402_16V4Z
220U_D2_4VM

CH751H-40_SC76
1

100_0402_5%
2

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

2
0.1U_0402_16V4Z

Place closely pin


D28,T28,AD28.

C570
0.1U_0402_16V4Z

+5VALW +3VA

R337

D15

CH751H-40_SC76
2

10_0402_5%

ICH_V5REF_SUS
C588
0.1U_0402_16V4Z

+3VS

C551
0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.


+1.5VS_DMIPLL
R250
1

0.5_0805_1%

2
0_0805_5%

C600

+1.5VS
1

+3VA
C599
0.1U_0402_16V4Z

0.1U_0402_16V4Z

AG28

+1.5VS

C592
0.1U_0402_16V4Z

Place closely pin AG5.


+3VS
1

+1.5VS
C251
1U_0603_10V4Z

+1.5VS
C606
0.1U_0402_16V4Z

1
T36
T33
2

PAD
PAD
@
@

+3VA

ICH_AA2
ICH_ Y7

Vcc3_3 / VccHDA

U6

VccSus3_3/VccSusHDA

R7

Vcc3_3[1]
VccDMIPLL

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7
1

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AA2
Y7

ICH_SUSLAN

V5REF_Sus

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Place closely pin AG9.

B27
+1.5VS_DMIPLL

C578
0.1U_0402_16V4Z

C210
10U_0805_10V4Z

R241
1

C546
0.01U_0402_16V7K

+1.5VS_DMIPLLR

+1.5VS

V5REF[2]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

C198

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

A24
C24
D19
D22
G19

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

C218
330U_D2E_2.5VM_R9

+3VS

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

P7

C553
1
2

C587
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
2

+3VS
1

C552
0.1U_0402_16V4Z
1
2

C572
0.1U_0402_16V4Z

C199
4.7U_0805_10V4Z

+3VS

+RTCVCC
1

Vcc1_5_A[19]
Vcc1_5_A[20]

AB17
AC17

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

T7
F17
G17

Vcc1_5_A[24]
Vcc1_5_A[25]

AB8
AC8

C558
0.1U_0402_16V4Z

C589
0.1U_0402_16V4Z

+3VA
C565
0.1U_0402_16V4Z

+3VA
C597
0.1U_0402_16V4Z

+1.5VS

VccSus1_05[1]

K7

C568 0.1U_0402_16V4Z
ICH_K7
PAD

T34

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

T28
T30

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

+VCCP

+3VA

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

W5

1U_0603_10V4Z

AE23
AE26
AH26

VccRTC

C567

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]

C590
0.1U_0402_16V4Z

F6

U21E

C591
0.1U_0402_16V4Z

ICH_V5REF_SUS

0.1U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C596
0.1U_0402_16V4Z

+1.5VS
D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C577
0.1U_0402_16V4Z

AD17

V5REF[1]

C573
0.1U_0402_16V4Z

G10

JUMP_43X118

U21F
ICH_V5REF_RUN

A1
H6
H7
J6
J7

@ PAD
PAD
@
@
+1.5VS
1

C586
0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

ICH7_BGA652~D

ICH7_BGA652~D
C583

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

21

of

48

+3VS
CHB1608U301_0603
1
2

0.01U_0402_16V7K

10U_0805_10V4Z

10U_0805_10V4Z

1
C549

+3VS

2
1U_0603_10V4Z
0.1U_0402_16V4Z
1

MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

E9
A8
B8

SD_CD#
MS_CD#
SM_CD#

A7
E8
B6
A6
C7
B7

MS_CLK/SD_CLK/SM_EL_WP#
MS_BS/SD_CMD/SM_WE#
MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1
MS_SDIO(DATA0)/SD_DAT0/SM_D0

P1
W8

K1
K19

SMRE
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE
XD_CD#

R608 1
R220 1
R605 1

SM_CLE
XD_CD#/SM_PHYS_WP#

P12
2 1K_0402_5%
F1
2 0_0402_5%
2 4.7K_0402_5% P17

R609

6.34K_0402_1%
T18
2
T19
XTPBIAS0
R13
XTPA0+
V14
XTPA0W14
XTPB0+
V13
XTPB0W13
XTPBIAS1
W17
XTPA1+
V16
XTPA1W16
XTPB1+
V15
XTPB1W15
CPS
R12

X_OUT
X_IN

R18
R19

PCI7412

AGND
AGND
AGND
R14
U13
U14

56.2_0603_1%

SPKROUT

H3

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

G1
H5
H2
H1
J1
J2
J3

SCL
SDA

G2
G3

VR_EN#

K2

PCI7412ZHK_PBGA257

2
0.1U_0402_16V4Z

C539

2
C544

2.2K_0402_5%
2

SDWP#_SMCE

R261
1

2.2K_0402_5%
2

SM_RB

R263
1

2.2K_0402_5%
2

2
0.01U_0402_16V7K

C541
1U_0603_10V4Z

R175
1

SMELWP#

5 in 1 CardReader Conn.
C

JP29

R606
1
2
43K_0402_5%

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

+VCC_5IN1

41

XD-VCC

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

33
34
35
36
37
38
39
40

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

MSBS_SDCMD_SMWE
SMELWP#
SDCMD_SMALE
XD_CD#
SM_RB
SMRE
SDWP#_SMCE
SMCLE

30
31
29
23
25
26
27
28

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

32
24

XD-GND
XD-GND

PCI_PERR#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#

42
18

15
9

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-CMD
SD-CD-SW
SD-CD-COM
SD-WP-SW
SD-WP-COM

16
19
20
11
12
13
21
22
43
44

MSCLK_SDCLK
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSBS_SDCMD_SMWE#
SD_CD#

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
SD-GND
SD-GND
MS-GND
MS-GND

8
4
3
5
7
6
2
14
17
1
10

MSCLK_SDCLK
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MS_CD#
MSBS_SDCMD_SMWE#

N.C.
N.C.

+VCC_5IN1

SDWP#_SMCE#

+3VS

5IN1_LED
2
R604

4 IN 1 CONN

SD-VCC
MS-VCC

TAITW_R007-530-L3

CLK_PCI_PCM
PCI_RST#

CLK_48M_CB
PCM_SPK

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
SIRQ
PCI_PIRQD#
5IN1_LED#
1
+3VS
10K_0402_5%

CLK_PCI_PCM

R205
R591
33K_0603_1%

R253

@ 10_0402_5%

+VCC_5IN1

@ 10_0402_5%

C191

C206

R310

2
2 300_0402_5%
300_0402_5%

@ 10P_0402_50V8J

@ 15P_0402_50V8J
470_0402_5%
D
Q21

1
R248
1K_0402_5%

+3VS

C204
0.1U_0402_16V4Z

MC_PWRON#
2
G
2N7002_SOT23

+VCC_5IN1

2
R298
10K_0402_5%
MC_PWRON#

U16

1
2
3
4

GND
IN
IN
EN#
G528_SO8

OUT
OUT
OUT
FLG

8
7
6
5

C227
0.1U_0402_16V4Z

X_OUT

C220
C222
4.7U_0805_10V4Z
2
2
1U_0603_10V4Z

C562

MSCLK_SDCLK

place near Chip 7411

CLK_PCI_PCM
PCI_RST#

+VDDPLL

18P_0402_50V8J

33_0402_5%

2 R258
1 PCI_AD22
100_0402_5%

1
1 R234
R600

R176 33_0402_5%
1
2

MSCLK_SDCLK_SMELWP#

R294
1

56.2_0603_1%

R293
1

1U_0603_10V4Z

J5

SMRE

X2
24.576MHz_16P_3XG-24576-43E1

R302
R292
5.1K_0603_1% 56.2_0603_1%
2
1
2
1

XTPA1+
XTPA1XTPB1+
XTPB1-

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

C542

XTPBIAS1
XTPA1+
XTPA1XTPB1+
XTPB1R291
56.2_0603_1%
2
1

C228
220P_0402_50V7K

C232

P2
U5
V7
W10

SUSPEND#

R607 1
2 CPS
4.7K_0402_5%

PCI7412@

C/BE3#
C/BE2#
C/BE1#
C/BE0#

L1
K3
K5
L5

+3VS

CLOSE TO CHIP

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCLK
PRST#
GRST#
RI_OUT#/PME#

XO
XI

CLOSE TO CHIP

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#

TEST0
CLK_48
PHY_TEST_MA

R0
R1
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
TPBIAS1
TPA1P
TPA1N
TPB1P
TPB1N
CPS

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

2.2K_0402_5%
2

R262
1

1
2

SC_PWR_CTRL

B4
A3

G5

VSSPLL

C224
220P_0402_50V7K

SD_CLK/SM_RE#
SD_CMD/SM_ALE
SD_DAT0/SM_D4
SD_DAT1/SM_D5
SD_DAT2/SM_D6
SD_DAT3/SM_D7
SD_WP/SM_CE#

R17

JP25
B

R290
56.2_0603_1%

1
2

R287
56.2_0603_1%
2
1

TYCO_1470383-2
4 4
6 G 3 3
5 G 2 2
1 1

R289
56.2_0603_1%

R301
R288
5.1K_0603_1% 56.2_0603_1%
2
1
2
1

C231
1U_0603_10V4Z

CLK_48M_CB
+3VS

A4
C5
C6
A5
B5
E6
E7

0.01U_0402_16V7K
1

C538

VCCP
VCCP

VDDPLL_33
VDDPLL_15

MC_PWR_CTRL_0
MC_PWR_CTRL_1/SM_R/B#

R260
1

SD_CD#
MS_CD#

C8
F8

VR_PORT
VR_PORT

U19
P15

P13
P14
U15
AVDD_33
AVDD_33
AVDD_33

PCI_CBE#[0..3]

MSBS_SDCMD_SMWE

1 1

C569

U13B

MC_PWRON#
SM_RB

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

C566

PCI_AD[0..31]

PCI_CBE#[0..3]

+VCC_5IN1

L15
C556

C564

C550
0.01U_0402_16V7K
1
2 +VDDPLL
0.1U_0402_16V4Z

0.01U_0402_16V7K

PCI_AD[0..31]

0.01U_0402_16V7K

C559

C554

C555
0.1U_0402_16V4Z

C560

L16

0.1U_0402_16V4Z

C561

CHB1608U301_0603
2
1

C563

+AVDD_7411
+3VS

18P_0402_50V8J

C540

X_IN

Compal Secret Data

Security Classification
Issued Date

2005/06/01

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

R ev
A

, 01, 2005

Sheet
1

22

of

48

+S1_VCC

+3VS

CardBus Power Switch


+S1_VCC

U45

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

E13
E18
H18
L17

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

H14
E19
G15
F17
G18
F19
H15
G19
C12
C14
G17
A12
A11
F18
E12

CPAR/A13
CFRAME#/A23
CTRDY#/A22
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)

S1_A16_C

1
2
33_0402_5%

S1_RST

C15

CRST#/RESET

S1_BVD2

B12

CAUDIO/BVD2(SPKR#)

N15
B11
A13
B16

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

E10

A_USB_EN#

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2
C543
1

S1_CD1#

F6
F9
F12
F14
J6
J14
L6
L14
P6
P8
P10

S1_CD2#

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

C183
1

F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

100P_0402_25V8K

VPPD1
VCCD0#
VPPD0

C574

4.7U_0805_10V4Z

C576

5
6

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

S1_D2

3.3V
3.3V

R629
10K_0402_5%

VCCD1#

VCCD0
VCCD1
VPPD0
VPPD1

1
2
15
14

C593
1
C595
1
C582
1
C580

0.1U_0402_16V4Z
2
10U_0805_10V4Z
2
0.01U_0402_25V4Z
2
1U_0603_10V4Z

OC

VCCD0#
VCCD1#
VPPD0
VPPD1

TPS2211AIDBR_SSOP16

R174
43K_0402_5%

B10
C4
D1
E1
E2
E3
F2
F3
F5
G6
H17 S1_A18
M19 S1_D14

SHDN

3
4

GND

C571

16

C575

4.7U_0805_10V4Z

10

1
2
C594 0.1U_0402_16V4Z

5V
5V

0.1U_0402_16V4Z

VPP

RSVD/D2
RSVD/VD0/VCCD1#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

100P_0402_25V8K

B9
A9
C9

0.1U_0402_16V4Z

+3VS

PCI 7412

40mil

20mil

+5VS

DATA/VD2/VPPD1
CLOCK/VD1/VCCD0#
LATCH/VD3/VPPD0

12V

13
12
11

+S1_VPP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

R596

VCCB
VCCB

U13A
D

A15
J19

VCC
VCC
VCC

***
JP11

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
E5
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18

GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
OE#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
VCC
VCC
VPP
VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
WP
CD2#
GND
GND

Near to PCMCIA slot.


+S1_VCC

C223
10U_0805_10V4Z

C225
0.1U_0402_16V4Z

+S1_VPP

C233
10U_0805_10V4Z

C230
0.1U_0402_16V4Z

PCI7412ZHK_PBGA257

PCI7412@

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_VCC

+S1_VCC

S1_VPP
S1_A16_C
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

+S1_VPP

SANTA_130602-2

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

Rev
A

, 01, 2005

Sheet
1

23

of

48

USB CONN. 1
+USB_VCCC

W=60mils

+USB_VCCC

+5VALW

C117 +
150U_D2_6.3VM

+USB_VCCC

OUT
OUT
OUT
FLG

C120
1000P_0402_50V7K

***
JP21

1
2
3
4

USB20_N4
USB20_P4

G528_SO8

3
+5VALW

8
7
6
5

4.7U_0805_10V4Z
2

USB_EN#

USB_EN#

VCC
DD+
GND

SUYIN_2537A-04G5T

C508

GND
IN
IN
EN#

0.1U_0402_16V4Z
2

U43

1
2
3
4

C118

D32
PSOT24C_SOT23
@

Place on the left side


C510

C509

C611 +
@ 150U_D2_6.3VM

2.2P_0402_50V8C

2.2P_0402_50V8C

USB CONN.2
2 port in right side

+USB_VCCA

W=60mils

+5VALW
J7

USB20_N2
USB20_P2

C355 +
150U_D2_6.3VM

2
4
6
8
10
12

USB20_N3
USB20_P3

C350

0.1U_0402_16V4Z
2

C351
1000P_0402_50V7K
***

+5VALW

+USB_VCCA
U35

ACES_88025-120L

C359

1
2
3
4

JP14

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
FLG

1
2
3
4

USB20_N5
USB20_P5

G528_SO8
4.7U_0805_10V4Z
2

D26
PSOT24C_SOT23
@

Place on the rear side

USB_EN#
C353

Bluetooth Conn.

VCC
DD+
GND

SUYIN_2537A-04G5T

1
3
5
7
9
11

USB_EN#

+USB_VCCA

2.2P_0402_50V8C

+3VS

C352

2.2P_0402_50V8C

+5VS

JP7

R92
100K_0402_5%

5
+BT_VCC

KILL_SW#
BT_RST#

C123
4.7U_0805_10V4Z

BT_RESET#
BT_WAKE_UP

BT_WAKE_UP

BT_RESET#
BT_DETACH
WLAN_BT_CLK

TC7SH08FU_SSOP5

W=40mils

0.1U_0402_16V4Z

U7

C119

C121
0.1U_0402_16V4Z
2

Q10
DTC124EK_SC59

+3VS

Q12
SI2301BDS_SOT23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

BT_DET#

BT_DET#

BT_PWR

C122
1U_0603_10V4Z

R88

USB20_P7
USB20_N7
WLAN_BT_DATA

@ 0_0402_5%

+BT_VCC
(MAX=200mA)

ACES_87151-2005
C124
(Top Contact)

0.1U_0402_16V4Z

Bluetooth Connector

Compal Secret Data

Security Classification
2005/06/01

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

24

of

48

+LDO3_EC
+LDO3_EC

+LDO3_EC

LRST#

+3VALW

R308
10K_0402_5%

SKU ID definition,
Please see page 3.
C

R140
100K_0402_1%
1

Rc

PME#

SKU_ID

C180

Rd

PME#

2 0.1U_0402_16V4Z

R155 2

1 0_0402_5%

R154 2

1 8.2K_0402_1%
@
1 18K_0402_1%
@
1 33K_0402_1%
@
56K_0402_1%
1
@
1 100K_0402_1%
@
1 200K_0402_1%
@

R153 2
R136 2
R137 2
R138 2
R139 2

KB_CLK
KB_DATA
PS_CLK
PS_DATA
TP_CLK
TP_DATA
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

+LDO3_EC
1
R236

IE_BTN#
2
R232

+3VALW

IE_BTN#
10K_0402_5%

1
100K_0402_5%
KB_CLK
KB_DATA
PS_CLK
PS_DATA
TP_CLK
TP_DATA
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

DKN_B+_ON
EC_SCI#
BT_RST#
BT_WAKE_UP
ENBKL
BKOFF#
BKOFF#
FSTCHG
FSTCHG
EC_SMI#
EC_SMI#
DPCONF_S5P_R
2
5.6K_0402_5%
WL_OFF#
EC_SWI#
S4_LATCH
S4_DATA
LID_SW#
LID_SW#
MODE#
MODE#
SYSON
SYSON
SUSP#
SUSP#
VR_ON
VR_ON
EJCTSW#
EJCTSW#
BT_DETACH
BT_DETACH
PBTN_OUT#
PBTN_OUT#

DKN_B+_ON
EC_SCI#
BT_RST#
BT_WAKE_UP
+LDO3_EC
RP25
1
2
3
4

8
7
6
5

MODE#
FR D#
SELIO#
FSEL#

R145 1

DPCONF_S5P

10K_0804_8P4R_5%

+5VALW

+5VS
RP27
1
2
3
4

RP24
8
7
6
5

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

4.7K_0804_8P4R_5%

1
2
3
4

8
7
6
5

KB_CLK
KB_DATA
PS_CLK
PS_DATA

4.7K_0804_8P4R_5%
C207
2

+5VS
2
4.7K_0402_5%
2
4.7K_0402_5%

1 TP_CLK
R257
1 TP_DATA
R265

0.1U_0402_16V4Z
1

2
R252

+3VALW

1
47K_0402_5%

PADS_LED#
CAPS_LED#
NUM_LED#
PHDD_LED#
EC_GA20
EC_KBRST#

PADS_LED#
CAPS_LED#
NUM_LED#

PSCLK1
PSDAT1
PSCLK2
PSDAT2PS2
PSCLK3
PSDAT3

163
164
169
170

SCL1
SDA1
SCL2
SDA2

8
20
21
22
27
28
48
62
63
69
70
75
109
118
119
148
149
155
156
162
168

GPIO04
GPIO07
GPIO08
GPIO09
GPIO0D
GPIO0E
GPIO10
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B
GPIO2D

55
54
23
41
19
5
6
31

VCC
VCC
VCC
VCC
VCC
VCC
VCC

110
111
114
115
116
117

X-BUS Interface

+3VALW

1K_0402_5%
1K_0402_5%
1K_0402_5%

2
2
2

2
100K_0402_5%

1
R277
1
R282
1
R286
1
R307

KBA1

1
R146

DPCONF_S5P_R
10K_0402_5%

1
R147

1394_DILSON_S3P
1K_0402_5%

1
R184

KBA4
KBA5
EJCTSW#

Wake Up

1394_PHYRST_S3P
1K_0402_5%

GPWU0
GPWU1
GPWU2
GPWU3
Pin
GPWU4
GPWU5
TIN1/GPWU6
TIN2/FANFB2/GPWU7

Digital To Analog

GPIO

+3VALW

EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#

2005/06/01

Issued Date

INVT_PWM
BEEP#
PWR_SUSP_LED#
ACOFF
USB_EN#
EC_ON
EC_LID_OUT#
EC_MUTE

INVT_PWM
BEEP
PWR_SUSP_LED#
ACOFF
USB_EN#
EC_ON
EC_LID_OUT#
EC_MUTE

ON /OFF

ON/OFF

KILL_SW#
PM_SLP_S3#
PM_SLP_S5#

C184
0.1U_0402_16V4Z

PME#
R309

81
82
83
84
87
88
89
90

BATT_TEMPA
SKU_ID
BATT_AOVP

GPODA0/DA0
GPODA1/DA1
GPODA2/DA2
GPODA3/DA3
GPODA4/DA4
GPODA5/DA5
GPODA6/DA6
GPODA7/DA7

99
100
101
102
1
42
47
174

DAC_BRIG
BT_PWR
IREF
EN_DFAN1#

2
0_0402_5%

+3VALW

R247
10K_0402_5%

D10
2

KILL_SW#
PM_SLP_S3#
PM_SLP_S5#
CIR_IN

ACIN

RB751V_SOD323

PCIE_WAKE#
ECAGND
2
1
C178 0.01U_0402_16V7K

BATT_TEMPA

BATT_AOVP
X_SENSOR
Y_SENSOR
Z_SENSOR

AD_BID0

1
R191
DAC_BRIG
BT_PWR
IREF
EN_DFAN1
PWROK
G_BEEP
Docking_Ctrl
AUD_SUDMUT_P3#

AUD_SUDMUT_P3#
PWR_LED#
WL_LED
HDD_LED#
BATT_LOW_LED#
BATT_CHGI_LED#

GPIO2E/TOUT1/FANFB1
DPLL_TP/GPIO06/FANFB3
FANTEST_TP/GPIO05/FAN3PWM

171
12
11

FAN_SPEED1
1
1394_PHYRST_S3P
1394_DILSON_S3P

TOUT2/GPIO2F

175

EC_THERM#

E51IT0/GPIO00
E51IT1/GPIO01
E51RXD/GPIO21/ISPCLK
E51TXD/GPIO22/ISPDAT

3
4
106
107

SHDD_LED#
E51_RXD
E51_TXD

XCLKI
XCLKO

158
160

C186

2
100K_0402_5%
2
0.22U_0402_10V4Z

Motion
F_FALL

CRY1

C248

R329 2 0_0402_5%
FAN_SPEED1
1394_PHYRST_S3P
1394_DILSON_S3P
EC_THERM#

EC_RSMRST#
SHDD_LED#
2 ALI/MH#
0_0402_5%

R242

ADP_I

PWR_LED#
WL_LED
HDD_LED#
BATT_LOW_LED#
BATT_CHGI_LED#
VGATE
MOTION
F_FALL

1 R319
2 CRY2
@ 20M_0603_5%

1
C247
X1

ALI/MH#

CRY2
CRY1

32.768KHZ_12.5P_1TJS125BJ2A251

KB910Q B4_LQFP176

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

AD_BID0
1

R169
33K_0402_1%

Rb

Compal Secret Data

Security Classification

R162
100K_0402_5%

Ra

KSO17

85
86
91
92
93
94
97
98

Timer Pin

FnLock#/GPIO12 *
CapLock#/GPIO011 *
NumLock#/GPIO0A *
ScrollLock#/GPIO0F *
MISC
ECRST#
GA20/GPIO02
KBRST#/GPIO03
ECSCI#

2
26
29
30
44
76
172
176

Analog Board ID definition,


Please see page 3.

KSO17

GPIAD0/AD0
GPIAD1/AD1
GPIAD2/AD2
GPIAD3/AD3
GPIAD4/AD4
GPIAD5/AD5
GPIAD6/AD6
GPIAD7/AD7

* GPIO18/XIO8CS#
* GPIO19/XIO9CS#
* GPIO1A/XIOACS#
* GPIO1B/XIOBCS#
Expanded I/O * GPIO1C/XIOCCS#
* GPIO1D/XIODCS#
* GPIO1E/XIOECS#
* GPIO1F/XIOFCS#

17
35
46
122
137
167

GPOW0/PWM0
GPOW1/PWM1
FAN2PWM/GPOW2/PWM2
GPOW3/PWM3
Width GPOW4/PWM4
GPOW5/PWM5
GPOW6/PWM6
FAN1PWM/GPOW7/PWM7

32
33
36
37
38
39
40
43

SMBus

ENBKL
@ 120K_0402_5%

1
R221

71
72
73
74
77
78
79
80

Analog To Digital

+3VALW

Pulse

Interface

GPIK0/KSI0
GPIK1/KSI1
GPIK2/KSI2
GPIK3/KSI3
GPIK4/KSI4
GPIK5/KSI5
GPIK6/KSI6
GPIK7/KSI7

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

@ ACES_85205-0400

10P_0402_50V8J

0_0402_5%

2 @ 0_0402_5%

+5VALW

E51_RXD
E51_TXD

R317 1

KSO[0..15]

R316 1

PLT_RST#

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

IN

PCI_RST#

RD#
WR#
MEMCS#
IOCS#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1/XIOP_TP
A2
A3
A4/DMRP_TP
A5/EMWB_TP
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/GPIO23
E51CS#/GPIO20/ISPEN

KSO[0..15]
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

GPOK0/KSO0
GPOK1/KSO1
GPOK2/KSO2
GPOK3/KSO3
GPOK4/KSO4
GPOK5/KSO5
GPOK6/KSO6
GPOK7/KSO7
GPOK8/KSO8
GPOK9/KSO9
GPOK10/KSO10
GPOK11/KSO11
GPOK12/KSO12
GPOK13/KSO13
GPOK14/KSO14
GPOK15/KSO15
GPOK16/KSO16
GPOK17/KSO17

1
2
3
4

1
2
3
4

OUT

ENBKL

KSI[0..7]

NC

0_0402_5%

150
151
173
152
138
139
140
141
144
145
146
147
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
105

For EC Tools
JP12
KSI[0..7]

NC

GM@
2

FR D#
FW R#
FSEL#
SELIO#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
IE_BTN#

JUMP_43X118

1U_0603_10V4Z

R233 1

FRD#
FWR#
FSEL#

C243

GMCH_ENBKL

0_0402_5%

R243 1

VGA_ENBKL

DOCKIN#
PGD_IN

0.1U_0402_16V4Z

SIRQ
DOCKIN#
PGD_IN

PM@
2

CLK_PCI_EC

10P_0402_50V8J

LRST#

LAD0
LAD1
LAD2
LAD3
LFRAME# LPC Interface
LRST#/GPIO2C
LCLK
SERIRQ
CLKRUN#/GPIO0C *
LPCPD#/GPIO0B *

ENE-KB910-B4

1 @ 33_0402_5%

15
14
13
10
9
165
18
7
25
24

C238

0.1U_0402_16V4Z

GND
GND
GND
GND
GND
GND

R259 2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

95

U14
C213
@ 22P_0402_50V8J
2
1

VCCA

16
34
45
123
136
157
166

1
+3VALW

C189
2

J2

C192
1000P_0402_50V7K

159

2
2
0.1U_0402_16V4Z

C181
1000P_0402_50V7K
1
1

EC_CIR@

JUMP_43X118

Internal Keyboard

2
2
0.1U_0402_16V4Z

L3
ECAGND
1
2
FBM-L11-160808-800LMT_0603

C214

to 0 ohm

ECAGND

C239

R198 Change
1
2
0_0603_5%

+LDO3

J3
R320
0_0402_5%

BATGND

0.1U_0402_16V4Z
1
2

161

0.1U_0402_16V4Z
1
1 C237
1
C217

ADB[0..7]

96

ADB[0..7]

VCCBAT

KBA[0..19]

AGND

KBA[0..19]

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

R ev
A

401395
Date:

, 01, 2005

Sheet
1

25

of

48

R425 2
R426 2

+3VLAN

Tekoa 82573E -> IAMT support only (WoL Support)


Vidalia 82573L -> No management
82562GZ -> 10/100 support

***
JP13

*ICH7 SMBALRT# signal reserve*


*a 0ohm resistor connect to S0 power*

T4
T26
T24
T23

C7
C8
B8
A8
SPI_MOSI
SPI_MOSO
SPI_CE#
SPI_CLK

LAN_SPI_MOSI
LAN_SPI_MOSO
LAN_SPI_CE#
LAN_SPI_CLK

When support S5 WOL


this pin connect to EC
to be a wake up even

Pull high support D3


cold power state
R65
+3VLAN
R66

LAN1_XO
LAN1_XI
2 3.3K_0402_5%
2@ 100_0402_5%

1
1

NVM_TYPE
NVM_PORT

NVM_SI-NC
NVM_SO-NC
NVM_CE#-NC
NVM_SK-NC

K14
J14

XTAL1-XTAL1
XTAL2-XTAL2

C6

AUX_PWR-NC

NVM_SHRD
R63
@ 10K_0402_5%

R500
3.3K_0402_5%

Pull down
when with docking
(Control PHY strength)

LED0#-SPEED_LED
LED1#-ACT_LED
LED2#-LILED

B11
C11
A12

LAN_LINK#
LAN_ACTIVITY#

NC-JRXD[2]
NC-JRXD[1]
NC-JRXD[0]
NC-JRST_SYNC

M12
N13
P13
M13

R523
R543
R524
R544

CLK_VIEW-JTXD[2]

L14

R527 1

2 0_0402_5% 82562@

LCI_RXD2

NC-JXD[1]

L13

R545 1

2 0_0402_5% 82562@

LCI_RXD1

NC-JXD[0]

M14

R526 1

2 0_0402_5% 82562@

LCI_RXD0

N14

R525 1

2 0_0402_5% 82562@

LCI_CLK

NC-JCLK
PE_WAKE#-NC

A6
A5
B4
D3

NVM_TYPE-NC
NVM_PROT-NC
NVM_REQ-NC
NVM_SHARED#-NC

C3

DOCK_IND-NC

H1
H2
H3
J1
J2
J3
K1
L1
M1
M3
N2
P1

TEST0-NC
TEST1-NC
TEST2-NC
TEST3-NC
TEST4-NC
TEST5-NC
TEST6-NC
TEST7-NC
TEST8-NC
TEST9-NC
TEST10-NC
TEST11-NC

LAN_PWR_GOOD-NC

P5

PE_RST#-NC

P7

Connect to GPIO pin for SPI protect


Pull high -> NVM protect
Pull low -> Non protect

NVM_PORT

SDP[3]-NC
SDP[2]-NC
SDP[1]-NC
SDP[0]-NC

A9
B9
B10
C9

P10

PCIE_WAKE#

PHY_TESTp-TOUT
PHY_TESTn-RBIAS100
PHY_TSTPT-RBIAS10

ALT_CLK125-NC

2
2
2
2

2 0_0402_5%
2@ 0_0402_5%

M9
N9
N7
L8
P14
J13
M5
D11

TEST16-NC
TEST15-NC
TEST14-NC
TEST13-NC
TEST12-NC

A14
E3
P9
M8
N3

LCI_TXD2
LCI_TXD1
LCI_TXD0
LCI_RSTSYNC

LCI_RXD2

PR1+

SHLD2

14 Chassis ground

SHLD1

13

Green LEDGreen LED+

RJ45_GND 1

LANGND

2
1

1
C348

LCI_CLK

C349
4.7U_0805_10V4Z

0.1U_0402_16V4Z

Must connect to RSMRST#


(S5 power)

EC_RSMRST#
PCI_RST#

T25 PAD~D

+LAN_AVDD25

LAN_CLKREQ#

LAN_CLKREQ#

R36
82573@

Connect to colck gen


for PCIE clock request

R37
82573@

GST5009 for GIGA LAN


TST1284B for 10/100 LAN
T1

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MDI0+
RJ45_MDI0-

LAN_MDI2P
LAN_MDI2N

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MDI2+
RJ45_MDI2-

LAN_MDI3P
LAN_MDI3N

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MDI3+
RJ45_MDI3-

LAN_MDI1P
LAN_MDI1N

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MDI1+
RJ45_MDI1-

LAN_MDI0P
LAN_MDI0N

C486
2
1
0.1U_0402_16V4Z
82573@
R528
82573@49.9_0402_1%

R529
82573@49.9_0402_1%
2
1

2
1
C487
0.1U_0402_16V4Z
R530
82573@49.9_0402_1%
82573@

R531
82573@49.9_0402_1%
2
1

1
2

R10
0.5u_GST5009
82573@

LAN1_XO

C496
22P_0402_50V8J

LAN1_XI

C499
22P_0402_50V8J

R13

R11
R12

RJ45_GND

1 25MHZ_20PF_1BG25000CK1A

0.1U_0402_16V4Z

82573@C488
0.1U_0402_16V4Z

R532 82573@
49.9_0402_1%

R533 82573@
49.9_0402_1%
2
1

R534 82573@
49.9_0402_1%

PR1-

RJ45_MDI0+

C22

82573@C489
0.1U_0402_16V4Z

C354
1000P_1206_2KV7K

0.1U_0402_16V4Z 82573@

PR2+

RJ45_MDI0-

LCI_RXD0

Y3

NVM_SHRD

PR3+

RJ45_GND

0.1U_0402_16V4Z 82573@

NVM_TYPE

RJ45_MDI1+

LCI_RXD1

0.1U_0402_16V4Z

When use 82573G/L R748,R749,R754, R750 = 49.9ohm


When use 82562GZ R748,R749,R754, R750 = 54.9ohm
and C603, C604, non-stuff

RJ45_MDI2+

TYCO_3-440470-4

C21

PR3-

LCI_TXD2
LCI_TXD1
LCI_TXD0
LCI_RSTSYNC

C20

PR2-

C19

RJ45_MDI2-

T=10mil 10

15

PLT_RST#

N10 TP_ALT_CLK125

NC-NC1
NC-NC2
NC-NC3
NC-NC4
NC-NC5
NC-NC6
NC-NC7
NC-NC8

0_0402_5% 82562@
0_0402_5% 82562@
0_0402_5% 82562@
0_0402_5% 82562@

PR4+

LAN_LINK#

LAN_LINK#

Non stuff when use 82562GZ

Install to use SPI


Flash (Tekoa only)
Stuff for 82573G
No-stuff for 82573L
5

@ R491
1K_0402_5%

R64
1K_0402_5%

1
1
1
1

RJ45_MDI0+

82573L@

RJ45_MDI0-

Close to IC 82573

R535 82573@
49.9_0402_1%
2
1

RJ45_MDI1+

R542 1
R541 1

82573E_FBGA196
LAN_MDI0P
LAN_MDI0N
LAN_MDI1P
LAN_MDI1N
LAN_MDI2P
LAN_MDI2N
LAN_MDI3P
LAN_MDI3N

RJ45_MDI2+

RJ45_MDI1-

B12
B13
B14

RJ45_MDI2-

RJ45_MDI3+

T27

THERMp-NC
THERMn-NC

RJ45_MDI1-

16

SHLD1

75_0402_1% 2

82562@ PAD~D
2 649_0603_1%
2 619_0402_1%
82562@
PAD~D
PAD~D
PAD~D
PAD~D

L3
L2

LAN_MDI0P
LAN_MDI0N
LAN_MDI1P
LAN_MDI1N
LAN_MDI2P
LAN_MDI2N
LAN_MDI3P
LAN_MDI3N

RJ45_MDI3+

SHLD2
PR4-

R71 1
R540 1

PE_CLKp-NC
PE_CLKn-NC

C13
C14
E13
E14
F13
F14
H13
H14

Amber LED-

75_0402_1% 2

Only stuff for 82562 bias

T3
T2

G1
G2

MDIOp-TDP
MDIOn-TDN
MDI1p-RDP
MDI1n-RDN
MDI2p-NC
MDI2n-NC
MDI3p-NC
MDI3n-NC

11

PAD~D
PAD~D

PE_T0p-NC
PE_T0n-NC

2 3.3K_0603_5% +3VS
ICH_SMBDATA
ICH_SMBCLK

Amber LED+

75_0402_1% 2

CLK_PCIE_LAN
CLK_PCIE_LAN#

D1
C1

R537 1
ICH_SMBDATA
ICH_SMBCLK

82573@
82573@

N11
M11
P11

0_0402_5% 1

1 C447
1 C448

SMB_ALRT#-NC
SMB_DATA-NC
SMB_CLK-NC

0.1U_0402_16V7K 2
0.1U_0402_16V7K 2

PCIE_RXP1
PCIE_RXN1

PE_R0p-NC
PE_R0n-NC

12

RJ45_MDI3-

RJ45_MDI3-

0_0402_5% 1

F2
F1

LAN_ACTIVITY#T=10mil

LAN_ACTIVITY#

Must pull high to S0 power


for system power good

U41A
PCIE_TXP1
PCIE_TXN1

1 200_0402_5%
1 200_0402_5%

75_0402_1% 2

Compal Secret Data

Security Classification

Install when sharing


SPI Flash with the ICH7M
Use dedicate SPI flash only

Issued Date

2005/06/10

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

@, 01, 2005

Rev
A
Sheet
1

26

of

48

+3VLAN
+LAN_AVDD25

CE#
SO
WP#
VSS

VDD
HOLD#
SCK
SI

LAN_SPI_CE#
LAN_SPI_CLK
LAN_SPI_MOSI
LAN_SPI_MOSO

1
2
3
4

CS
SK
DI
DO

8
7
6
5

VCC
NC
NC
GND

SPI_CLK
SPI_MOSI
47_0402_5%
82573G@

Size:
IAMT support:
At last 4Mbits SPI flash
ASF2.0 Support:
64Kbits EEPROM or SPI flash
No magagement:
1Kbits EEPROM

U40
SPI_CE#
SPI_CLK
SPI_MOSI
SPI_MOSO

80 mil

@ JUMP_43X118

R497
R496
+3VLAN

J1

47_0402_5%

SST25LF080A_SO8
82573G@

JUMP_43X118

R516
2
1
@ 10K_0402_5%

AT93C46-10SI-2.7_SO8
82573L@

VCC3.3-NC1
VCC3.3-NC2
VCC3.3-NC3
VCC3.3-NC4
VCC3.3_REG2.5-NC5
VCC3.3_REG2.5-NC6

M10
J4
F3
D9
A2
M2

VCC2.5_PCIE-VCC3.3-1
VCC2.5_PCIE-VCC3.3-2
VCC2.5_PCIE-VCC3.3-3
VCC2.5_XTAL-VCC3.3-4
VCC2.5_IO-NC1
VCC2.5_IO-NC2
VCC2.5_IO-NC3
VCC2.5_IO-NC4
VCC2.5_IO-NC5
VCC2.5_PHY-NC6
VCC2.5_PHY-NC7
VCC2.5_PHY-VCC3.3

J5
G5
H5
K13
H4
N7
M4
G3
B6
J12
L12
A11

VCC3.3-VCC3.3-1
VCC3.3-VCC3.3-2
VCC3.3-VCC3.3-3
VCC3.3-VCC3.3-4
VCC3.3-VCC3.3-5
VCC3.3_REG2.5-VCC3.3

P2
N6
A7
P12
N8
A3

EEPROM stuff for 82573L

For 82562GZ LAN disable function


+3VLAN

Only 82562GZ mode0 stuff


If use mode1,2 no-stuff and
only connect LAN_DISABLE#
signal to Ball L7

R554

Strapping resistor for 82562GZ


Ehanced Mode configuration
Populate according table

R546

R559

R548

@ 200_0402_5%

+3VLAN

32

C422

C420

2
0.1U_0402_16V4Z

2
4

40mil
C50

0.1U_0402_16V4Z
1
1

R476

1_2010_5%

4.7U_0805_10V4Z

C426
10U_0805_10V4Z

C429

TC7SH08FU_SSOP5
82562@

C428

2
0.1U_0402_16V4Z

DEVICE_OFF#-AVD10

B2
B1

82573E_FBGA196
82573L@

+LAN_AVDD25

R485
0_0603_5%
82573@

R492
0_0603_5%
82562@

+3VLAN

1
+

2
LAN_CTRL12

+LAN_AVDD25

Use internal regulator


please take care thermal

82562GZ Hardware configuration table (Default Mode 1)


TESTEN ISOL_TCK ISOL_TI ISOL_EXEC Mode
TESTEN ISOL_TCK ISOL_TI ISOL_EXEC
Mode
Mode0
XOR tree
0
0
1
0
0
0
0
0
Mode2
Mode1
1
0
0
1
0
1
1
0
Test Mode
Mode3
0
1
1
0
1
1
0
1
Isolate
Mode4
1
1
1
0
1
0
0
1
Power down 1
Reserved
1
0
1
1
1
1
1
Testing
1
0
1
1
Compal Secret Data

Issued Date

2005/06/10

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

CTRL_1.2-NC
2.5V_OUT-NC1
2.5V_OUT-NC2

+3VLAN

LAN_RST#

Security Classification

L7

P3

+LAN_AVDD25
+3VLAN

Connect to ICH7 LAN reset pin


Y

+LAN_VDD12

LAN_DISABLE#

PHY_REF-ISOL_TI
NC-ISOL_TCK
NC-ISOL_TXE
TEST_EN-TEST_EN

U42

For 82562GZ LAN_RST# signal must


not be de-asserted sooner than 10ms
after the Resume power supply reaches
its nominal voltage.

1/2W Resistor

EC_RSMRST#

1
Q34
BCP69_SOT223

LAN_DISABLE# 1

1
1

C423

2
22U_0805_6.3V6M

LAN_CTRL12

C421

D12
D14
D10
A13

4.7U_0805_10V4Z

R477
1_2010_5%

82573@ 4.99K_0402_1%
R538 1
2 ISOL_TI
ISOL_TCK
ISOL_EXEC
R521 1
2 TESTEN
82573@ 3.3K_0402_5%

+3VLAN

R43
4.7K_0402_5%

JTAG_TMS-NC
JTAG_TCK-NC
JTAG_TDI-NC
JTAG_TDO-NC

82562GZ mode0 LAN_DISABLE# pin


is used as ADV10 (auto-negotiation
advertise 10M only)

1.2V power supply


1

N4
N5
P4
P6

LAN_DISABLE#

@ 200_0402_5%
200_0402_5%
82562@

22U_0805_6.3V6M
1
1

PAD~D
PAD~D
PAD~D
PAD~D

ISOL_EXEC

R536
200_0402_5%
82562@

T8
T11
T9
T12

ISOL_TI

NC1-VSS
NC2-VSS
NC3-VSS
NC4-VSS
NC5-VSS
EN2.5REG-NC
CTRL_2.5-NC

ISOL_TCK

2
G
@ 2N7002_SOT23S

B7
M6
L6
K12
L11
B5
A4

LAN_DISABLE#

VSS1-VSS
VSS2-VSS
VSS3-VSS
VSS4-VSS

T10 PAD~D

TESTEN

(Default Mode 1)

200_0402_5%
82562@

Q36

R552

R547 1
2
@ 100_0402_5%
R558 1
2
@ 100_0402_5%
R539 1
2
@ 100_0402_5%
R553 1
2
@ 100_0402_5%

4.7K_0402_5%

(Connect to GPIO)

2
2

1
R551

LAN_DISABLE#

R556

R522
@ 200_0402_5%

R555
@ 470_0402_5%

200_0402_5%
82562@

+3VLAN

@ 200_0402_5%

R61
10K_0402_5%
2
1

+3VLAN
+3VLAN

P8
C12
D13
N12

VSS-VSS1
VSS-VSS2
VSS-VSS3
VSS-VSS4
VSS-VSS5
VSS-VSS6
VSS-VSS7
VSS-VSS8
VSS-VSS9
VSS-VSS10
VSS-VSS11
VSS-VSS12
VSS-VSS13
VSS-VSS14
VSS-VSS15
VSS-VSS16
VSS-VSS17
VSS-VSS18
VSS-VSS19
VSS-VSS20

C10
D6
D7
D8
E6
E7
E8
E9
F6
F7
F8
F9
G7
G8
G9
H9
G14
K2
E2
N1

G6
H6
H7
J6
J7
J8
K4
K5
K7
K8
L5
H8
J9
J10
J11
K9
K10
L9
L10
K11
K6
H11
K3
G13

R488
0_0603_5%
82562@

C455
0.1U_0402_16V4Z

R489
47_0402_5%
82573G@

8
7
6
5

+LDO3

VCC1.2-VCC3.3-1
VCC1.2-VCC3.3-2
VCC1.2-VCC3.3-3
VCC1.2-VCC3.3-4
VCC1.2-VCC3.3-5
VCC1.2-VCC3.3-6
VCC1.2-VCC3.3-7
VCC1.2-VCC3.3-8
VCC1.2-VCC3.3-9
VCC1.2-VCC3.3-10
VCC1.2-VCC3.3-11
VCC1.2-VCC3.3-12
VCC1.2-VCC3.3-13
VCC1.2-VCC3.3-14
VCC1.2-VCC3.3-15
VCC1.2-VCC3.3-16
VCC1.2-VCC3.3-17
VCC1.2-VCC3.3-18
VCC1.2-VCC3.3-19
VCC1.2-VCC3.3-20
VCC1.2-VCC3.3-21
VCC1.2-VCC3.3-22
VCC1.2-VCC3.3-23
VCC1.2-VCC3.3-24

U39

1
2
3
4

J9

R501
10K_0402_5%
82573G@

F12
H12
G12
C5
C4
A10

R487
0_0603_5%
82573@

+3VLAN
C451
0.1U_0402_16V4Z
82573G@
2
1

82573G@

R486
10K_0402_5%
2
1

+3VLAN

+3VLAN

VCC1.2-NC1
VCC1.2-NC2
VCC1.2-NC3
VCC1.2-NC4
VCC1.2-NC5
VCC1.2-NC6

1
+3VALW

E1
L4
E11
E12

C444
0.1U_0402_16V4Z

+3VLAN

NC-VCC3.3-1
NC-VCC3.3-2
NC-VCC3.3-3
NC-VCC3.3-4

C479
0.1U_0402_16V4Z

Flash stuff for 82573E

Only dedicate SPI support

VSS1-NC
VSS2-NC
VSS3-NC
VSS4-NC
VSS5-NC
VSS6-NC
VSS7-NC
VSS8-VSS
VSS9-VSS
VSS10-VSS
VSS11-VSS
VSS12-VSS
VSS13-VSS
VSS14-VSS
VSS15-VSS
VSS16-VSS
VSS17-VSS

C440
10U_0805_6.3V4Z

*For 82562GZ stuff 1Kbits EEPROM at ICH7*

SPI_CE#
SPI_MOSO

+3VLAN

A1
C2
D2
G4
D4
D5
B3
E4
E5
E10
F11
F10
G11
G10
H10
F5
F4

C471
10U_0805_6.3VM

C439
10U_0805_6.3V4Z

C403
0.1U_0402_16V4Z

C414
0.1U_0402_16V4Z

C408
0.1U_0402_16V4Z

C413
0.1U_0402_16V4Z

C407
0.1U_0402_16V4Z

C402
0.1U_0402_16V4Z

C433
0.1U_0402_16V4Z

C437
0.1U_0402_16V4Z

C443
0.1U_0402_16V4Z

C432
0.1U_0402_16V4Z

+LAN_VDD12
U41B

C442
0.1U_0402_16V4Z

C436
0.1U_0402_16V4Z

C469
0.1U_0402_16V4Z

C459
0.1U_0402_16V4Z

C445
0.1U_0402_16V4Z

C458
0.1U_0402_16V4Z

C446
0.1U_0402_16V4Z

+LAN_VDD12

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

@, 01, 2005

Rev
A
Sheet
1

27

of

48

+3VS

C211

C271

C278

+1.5VS

C215

C226

C261

+3VALW

C234

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.01U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

+3VS

+3VS
U10
1
2
3
4
5
6
7

MOTION
F_FALL
X_SENSOR
Y_SENSOR
Z_SENSOR

GND
NC
VDD
IO VDD
MOTION SCL/SCLK
FF
SDA/SDO
Output X ADDR0/SDI
Output Y
CS#
Output Z
RESET

14
13
12
11
10
9
8

EC_SMB_CK2
EC_SMB_DA2

Mini-Express Card

+1.5VS +3VS

***

1
C169 C164

8.2K_0402_5%
R128

3300P_0402_50V7K
2
2
2200P_0402_50V7K
2200P_0402_50V7K
2

0.1U_0402_16V4Z

KXP84-0200_DFN14
1
1
C175 C174

1 R134
2 10K_0402_5%
1
2
+3VS
C162
10U_0805_10V4Z

JP28
PCIE_WAKE#
WLAN_BT_DATA
WLAN_BT_CLK
MINI_CLKREQ#
CLK_PCIE_MCARD#
CLK_PCIE_MCARD

PCIE_RXN2
PCIE_RXP2

R305
PCIE_RXN2
1
PCIE_RXP2
1
R300
PCIE_TXN2
PCIE_TXP2

PCIE_WAKE#
MINI_CLKREQ#
CLK_PCIE_MCARD#
CLK_PCIE_MCARD

0_0402_5%
2 PCIE_C_RXN2
2 PCIE_C_RXP2
0_0402_5%
PCIE_TXN2
PCIE_TXP2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

XMIT_OFF#
2

PLT_RST#
+3VALW

+3VS
10U_0805_6.3V6M

ICH_SMBCLK
ICH_SMBDATA
R283 2
2
R278

C177

10_0402_5%
1
0_0402_5%

USB20_N1
USB20_P1

0.01U_0402_16V7K

C176

C170

0.1U_0402_16V4Z

FOX_AS0B226-S40N-7F~D

Kill SWITCH
+3VALW

+3VALW
2

D18
DAN217_SC59

KILL_SW#

TC7SH08FU_SSOP5

D13

1
RB751V_SOD323

1BS003-1211L_3P
2

1
1

KILL_SW#

TIP
3

2 0.1U_0402_16V4Z

U20

WL_OFF#
KILL_SW#

KILL_SW#

C235

WL_OFF#

R402
100K_0402_5%

+3VALW

SW4

XMIT_OFF#

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

28

of

48

+VDDA

28.7K for Module Design (VDDA = 4.702)


+5VALW

R404
10K_0402_5%
R401
1
2
560_0402_5%

VIN

VOUT

DELAY SENSE or ADJ

ERROR

SD

40mil

1
C337

2
1U_0603_10V4Z

C323

C325

10U_1206_16V4Z
2
2
0.1U_0402_16V4Z

R415
10K_0402_5%

CNOISE

GND

R397
30K_0402_1%

2
R403
1
2
560_0402_5%

2
B
E

R359 2

1 @ 6.8K_0402_5%

R360 2

1 @ 6.8K_0402_5%

LINE_IN_L

R358 2

LINE_IN_R

W D@ 6.8K_0402_5%
R361 2
1

R406
1
2
560_0402_5%

C335 1
1U_0603_10V4Z

SB_SPKR

D16
RB751V_SOD323

2 C294
W D@ 1U_0402_6.3V4Z

2 C295
W D@ 1U_0402_6.3V4Z

W D@ 6.8K_0402_5%

R353
10K_0402_5%

C286
WOD@ 1U_0402_6.3V4Z

HD Audio Codec
+AVDD_AC97

20mil

INT_CD_L
INT_CD_R

1
1
1
1

20K_0402_5%
6.8K_0402_5%
6.8K_0402_5%
20K_0402_5%

C316
CD_R_R
C318

1
R398

R389

CD_AGND_R
C317
MIC1_L

MIC1_L

C604
MIC1_R

MIC1_R

C603

1
R366

2
0_0603_5%

LINE2_L

FRONT-OUT-L

35

AMP_LEFT

15

LINE2_R

FRONT-OUT-R

36

AMP_RIGHT

16

MIC2_L
39

HP_OUT_L

41

HP_OUT_R

LINER

24

LINE1_R

6.8K_0402_5%

MONO_IN

12
11
10

R395
@ 0_0402_5%

1
C326

BIT_CLK

SDATA_IN

CD_L
CD_R
CD_GND
MIC1_L
MIC1_R

NC
NC
NC
NC
NC
NC

2
33
47
37
3
29

C617
@1000P_0402_50V7K

AMP_RIGHT

SURR_OUT_L

C287
WOD@1U_0402_6.3V4Z

AMP_LEFT

SURR_OUT_R

CD_L_RC
18
1U_0603_10V4Z
CD_R_RC
20
1U_0603_10V4Z
CD_AGND_RC19
1U_0603_10V4Z
MIC1_C_L
21
1U_0603_10V4Z
MIC1_C_R
22
1U_0603_10V4Z
13

9
DVDD2

38

DVDD1

C327
@ 1000P_0402_50V7K

14

2
27P_0402_50V8J
ICH_BITCLK_AUDIO

R387

2 33_0402_5%

ICH_AC_SDIN0

T5

PAD

SENSE A
PC_BEEP

MIC2_VREFO

30

MIC1_VREFO_L

28

VREF

27

MIC1_VREFO_R

32

LINE2_VREFO

31

SENSE B
CEN-OUT
LFE-OUT

34
43
44

JDREF
AVSS1
AVSS2

40
26
42

RESET#
SYNC

SDATA_OUT

45
46

SIDE-SURR-L
SIDE-SURR-R

2
2
0_0603_5%

0.1U_0402_16V4Z

LINE1_L

C303
10U_1206_16V4Z

MIC2_R

ICH_SDOUT_AUDIO

1
R400

23

ICH_SYNC_AUDIO

2
0_0603_5%

C328

17

LINEL

ICH_RST_AUDIO#

1
R658

U48

LINER

+3VS

1
C322

25

2
0.1U_0402_16V4Z

0_0402_5%

CD_L_R

1 20K_0402_5%
1

R393 2

CD_AGND

2
2
2
2

C329

LINEL

48

SPDIFO

4
7

DVSS1
DVSS2

10mil

MIC1_VREFO_L

10mil

MIC1_VREFO_R

10mil

ACZ_VREF

C319
10U_0805_10V4Z

R392
R388
R390
R394

AVDD2

C331
10U_1206_16V4Z

0.1U_0402_16V4Z

40mil

AVDD1

+VDDA

0.1U_0402_16V4Z
1
1
C305

L4
1
2
FBM-L11-160808-800LMT_0603

R396
10K_0402_1%

0.1U_0402_16V4Z

1U_0603_10V4Z
1
2
Q25
R407
2SC2411K_SC59 2.4K_0402_5%

SYSON

MONO_IN

C324
10U_1206_16V4Z

C333 1
1U_0603_10V4Z

PCM_SPK

C341
1
2

4.85V

1
C332

SI9182DH-AD_MSOP8

+VDDA

U33

4
2

C330 1
1U_0603_10V4Z

BEEP

(output = 250 mA)

60mil

R399
@ 20K_0402_1%

ALC861-GR_LQFP48
4

GND

DGND

GNDA

2005/05/12

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

AGND

Title

SCHEMATIC, M/B LA-3011


Size
B
Date:

Document Number

Rev
A

401395
, 01, 2005
G

Sheet

29

of
H

48

D3

@ PSOT24C_SOT23

D1
+5VS

R660
100K_0402_5%

W=40mil

@ PSOT24C_SOT23
+5VS

SHUTDOWN#
C292
4.7U_0805_10V4Z

Q26
2N7002_SOT23
2
G

C288
0.1U_0402_16V4Z

EC_MUTE
JP2

SPKL+
SPKLSPKR+
SPKR-

U47
7
18
19
R362 1

2 100K_0402_5%

2
3
4
21
5
23
6
20

VOL_AMP

SPKL+
SPKR+
AMP_LEFT

C608

AMP_RIGHT

C616

LEFT_2
RIGHT_2

2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z

PVDD SHUTDOWN#
PVDD
SE/BTL#
VDD
PC-BEEP
BYPASS
HP/LINE#
LOUTVOLUME
ROUTLOUT+
LIN
ROUT+
RIN
LLINEIN
RLINEIN
GND
LHPIN
GND
RHPIN
GND
GND
CLK

17

22
15
14
11
9
16
10
8

NBA_PLUG

C613

1
12
13
24

2
C298
1U_0402_6.3V4Z1

TPA0232PWP_TSSOP24
1
2

R659 1

BYPASS

2 100K_0402_5%
2
1U_0402_6.3V4Z
SPKLSPKR-

20mil

+5VS
G_BEEP

R19
R24
R31
R32

1
1
1
1

2
2
2
2

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

SPK_L+
SPK_LSPK_R+
SPK_R-

4
3
2
1
ACES_85204-0400

Speaker Conn.

C296
1
1U_0402_6.3V4Z

C297
1U_0402_6.3V4Z

C614
0.047U_0402_16V7K
2
2 0.1U_0402_16V4Z

C609

C615
0.1U_0402_16V4Z 1

1 C607
0.1U_0402_16V4Z

Headphone JACK 1
JP31
5

10mil

NBA_PLUG
1
100K_0402_5%
HPOUT1_R_4
2
FBM-11-160808-700T_0603
HPOUT1_L_4
2
FBM-11-160808-700T_0603

2
R405
2 HPOUT1_R_3 1
0_0603_5%
L6
2 HPOUT1_L_3 1
0_0603_5%
L5

2 HPOUT1_R_2
150U_D2_6.3VM
2 HPOUT1_L_2
150U_D2_6.3VM

1
R421
1
R420

4
3
6
2
1
FOX_JA6033L-5S1-TR

Volumn Control VR

SPKR+
1
C321
SPKL+
1
C320

+5VS

+5VS

C340
330P_0402_50V7K

C334
330P_0402_50V7K

R410
2.61K_0603_1%

Reserve for noise.

MIC1_VREFO_R
MIC1_VREFO_L

10mil

+5VS

R411
100K_0402_5%

Int MIC Conn.

R408
1

1
S

Q28
2N7002_SOT23

2
G

NBA_PLUG 2
G

S
Q27
2N7002_SOT23

1
2

45@
R409
5.76K_0603_1%

15mil

WM-64PCY_2P

INT_MIC_R
INT_MIC_L

45@

10mil

R414
4.7K_0402_5%

R413
4.7K_0402_5%

JP32
5
4

MIC1_R
MIC1_L

MIC1_R

MIC1_L

L8
2
FBM-11-160808-700T_0603
L7
2
FBM-11-160808-700T_0603
1

MIC1

15mil

MIC2

1.5K_0603_1%

VOL_AMP

0.01W_10KC_EVUTWZB19C14
VR1

C336
@ 0.1U_0402_16V4Z

1
2

C338
220P_0402_50V7K

WM-64PCY_2P

MIC1_R_1

3
6
2
1

MIC1_L_1
1

FOX_JA6033L-5S1-TR

C339
220P_0402_50V7K
2
2

BTL MODE
R293//R294=1.19K
Vmax=0.431V , GAINmax=14dB
Vmin=4.05V, GAINmin=-80dB
SE MODE
Vmax=1.53V , GAINmax=-6db
Vmin=4.28V, GAINmin=-80db
4

Compal Secret Data

Security Classification
2005/03/25

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

30

of

48

R631 1

2
W D@ 1K_0402_5% 1

R638 1

W D@ 1000P_0402_50V7K

+VDDA
W D@ 1U_0402_6.3V4Z
C263 1
2

2
4

W D@ 1U_0402_6.3V4Z

LINEIR#

R628 1

2 W D@ 10K_0402_5%
W2D@ 4.7K_0402_5%

2 W D@ 1K_0402_5%R632 1
1

W D@ 1U_0402_6.3V4Z

C262

V+

R651 1
R652 1

+DOCK_AUD_VREF

1
C255

W D@ 1000P_0402_50V7K

2 W D@ 10K_0402_5%

+VDDA
D

+VDDA

R639 1

W D@ 1000P_0402_50V7K

LINE_IN_L

U26A
W D@ LMV824MTX_TSSOP14

C277

2
W D@ 1K_0402_5%

V-

LINEIL

R647 1

11

C285

2 W D@ 4.7K_0402_5%

R375
1
2
W D@ 100K_0402_5%

2 W D@ 4.7K_0402_5%

+VDDA

R374
W D@ 100K_0402_5%

C284
W D@ 1K_0402_5%
2

2 R654
1

W D@ 1000P_0402_50V7K

+DOCK_AUD_VREF

R653 1

W D@ 1U_0402_6.3V4Z

2 W D@ 10K_0402_5%

W D@

V+

R648 1

V-

C276

11

LINEIR

V+

C264

2 W D@ 10K_0402_5%

10

V-

R627 1
2
W D@ 1U_0402_6.3V4Z

1 C307

11

1
C256

LINEIL#

+DOCK_AUD_VREF

+DOCK_AUD_VREF

U26C
LMV824MTX_TSSOP14
W D@

2 0.1U_0402_16V4Z
W D@

C306
@
1U_0402_6.3V4Z

LINE_IN_R

U26B
W D@ LMV824MTX_TSSOP14

4.7K_0402_5%

+VDDA
R378 1

W D@

22K_0402_5%

2
W D@ 68P_0402_50V8K

+VDDA

13

V+

C312

12

V-

+VDDA

C267 1

1U_0402_6.3V4Z

3
2

U28C

V+

W D@
C268

U28A
W D@ LMV824MTX_TSSOP14

1U_0402_6.3V4Z

14

LINEOL

W D@

R339
4.7K_0402_5%
W D@

+VDDA
R342 2

1 4.7K_0402_5%

W D@ LMV824MTX_TSSOP14

13

12

11

2
C258
0.1U_0402_16V4Z
W D@

11

V+

+DOCK_AUD_VREF

V-

W D@
+VDDA

V+

C304
0.1U_0402_16V4Z
@

V-

U26D
W D@ LMV824MTX_TSSOP14

11

10

+DOCK_AUD_VREF

V+

2
9

V-

W D@ 22K_0402_5%
1
2

V-

11

1
C315

W D@ 1U_0402_6.3V4Z
HP_OUT_L

11

R379

C253

U28B
W D@ LMV824MTX_TSSOP14

1U_0402_6.3V4Z
W D@

14

U28D
W D@ LMV824MTX_TSSOP14

LINEOL#

+VDDA
B

C311

1
C265

V+

U27C

14

U27D
W D@ LMV824MTX_TSSOP14

2
1U_0402_6.3V4Z

V-

U27A
W D@

V+

C302
0.1U_0402_16V4Z
1 @

11

C266

1U_0402_6.3V4Z
W D@

LINEOR

LMV824MTX_TSSOP14

W D@ LMV824MTX_TSSOP14
R340
W D@ 4.7K_0402_5%

+DOCK_AUD_VREF

V-

9
10

W D@

11

HP_OUT_R

R377
W D@ 22K_0402_5%
1
2

12
+VDDA

+VDDA
W D@ 1U_0402_6.3V4Z
1
2
C314

V+

2
W D@ 68P_0402_50V8K
1
2

11

R376 1

13

V-

W D@
22K_0402_5%

W D@ 4.7K_0402_5%
1

R341 2

+DOCK_AUD_VREF
C257
0.1U_0402_16V4Z
@

11

V+

V-

+VDDA

C252

U27B

1U_0402_6.3V4Z
W D@

LINEOR#

W D@ LMV824MTX_TSSOP14

Compal Secret Data

Security Classification
2005/04/25

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PROPRIETARY NOTE

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

31

of

48

C534
1

0.1U_0402_16V4Z
2

ON/OFFBTN#

1N4148_SOT23

2
1
P

1
2
R597
10K_0402_5%

U44
NC7SZ14M5X_SOT23-5

1
2
R240
10K_0402_5%

1
C197

1
2
R246
10K_0402_5%

0.1U_0402_16V4Z
2

74LCX74MTC_TSSOP14

D9
2

S4_DATA

VCC
CD2#
D2
CP2
SD2#
Q2
Q2#

RTCVREF
C196
1

D_SET_S4

C47
1

217@ RB420D_SOT23

C51
2

217@ 220P_0402_50V7K

LPTSTB#
LPTAFD#
INIT#
SLCTIN#

LPTSTB#

R53

LPTAFD# R475 1

INIT#

SLCTIN#

LPD0
LPD1
LPD2
LPD3

R474 1
R473 1

LPD0
LPD1
LPD2
LPD3

R_LPTSTB#
AFD#/3M#
LPTINIT#
LPTSLCTIN#

217@ 68_1206_8P4R_5%
F D0
4
5
F D1
3
6
F D2
2
7
F D3
1
8

R_LPTSTB#
AFD#/3M#
LPTINIT#
LPTSLCTIN#

FD0
FD1
FD2
FD3

2 @ 220P_0402_50V7K

LPTSLCTIN#

2 @ 220P_0402_50V7K

LPTINIT#

2 @ 220P_0402_50V7K

LPTERR#

2 @ 220P_0402_50V7K

AFD#/3M#

C409 1

2 @ 220P_0402_50V7K

LPTACK#

C46
R52 217@
2.2K_0402_5%

Clo se to Docking

C410 1

2 @ 220P_0402_50V7K

LPTBUSY

C411 1

2 @ 220P_0402_50V7K

LPTPE

C412 1

2 @ 220P_0402_50V7K

LPTSLCT

C13

2 @ 220P_0402_50V7K

F D0

C14

2 @ 220P_0402_50V7K

F D1

C15

2 @ 220P_0402_50V7K

F D2

C16

2 @ 220P_0402_50V7K

F D3

C390 1
C393
C391 1

2 @ 220P_0402_50V7K

F D4

2 @ 220P_0402_50V7K

F D5

C392 1

2 @ 220P_0402_50V7K

F D6

2 @ 220P_0402_50V7K

F D7

RP3
+5V_PRN

1
2
3
4

8
7
6
5

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

217@ 2.7K_1206_8P4R_5%
RP4
1
8 AFD#/3M#
2
7 LPTERR#
3
6 LPTINIT#
4
5 LPTSLCTIN#

C5
WD@ 0.1U_0402_16V4Z
2
LPTERR#

C1
WD@ 0.1U_0402_16V4Z

DTR#1
RTS#1
TXD1
CTS#1
RI#1
RXD1
DCD#1
DSR#1

217@ 2.7K_1206_8P4R_5%
RP1
F D0
1
8
F D1
2
7
F D2
3
6
F D3
4
5
217@ 2.7K_1206_8P4R_5%
RP2
F D7
1
8
F D6
2
7
F D5
3
6
F D4
4
5

C4
WD@ 0.1U_0402_16V4Z

26

C48

SUSP#

28

C1+

24
1

C1C2+

2
14
13
12
19
18
17
16
15
20

C2TIN1
TIN2
TIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUTB2

23

FORCEON

22

U1

VCC

C49

217@
33_0402_5%
217@
33_0402_5%
217@
33_0402_5%
217@
33_0402_5%

Q18
2N7002_SOT23

+3VS

+5V_PRN

Close to Docking

D4
+5VS

2
G

RB751V_SOD323

Docking Parallel Port

+3VALW

@ 1U_0805_16V7K

CD1#
D1
CP1
SD1#
Q1
Q1#
GND

14
13
12
11
10
09
08

2
1U_0805_16V7K

1
2
3
4
5
6
7

1
2
R185
1
10K_0402_5%
C188

3
2

RTCVREF
R204
10K_0402_5%

2
G
Q40
2N7002_SOT23

U12

S4_LATCH

PSOT24C_SOT23

RTCVREF

D7

1
Q19
2N7002_SOT23
0.1U_0402_16V4Z

Q39
2N7002_SOT23

SYSON

C195

2
G
3

Y
G

A
3

2
G

S4_LID_SW#

2
1U_0805_16V7K

ON/OFFBTN#

D33

680K_0402_5%

1
C533

100K_0402_5%
2

R584

100K_0402_5%

R585

R590

RTCVREF

RTCVREF

RTCVREF RTCVREF

V+

27

V-

TOUT1
TOUT2
TOUT3
RIN1
RIN2
RIN3
RIN4
RIN5

9
10
11
4
5
6
7
8

INVLD#

21

GND

25

C2
C3

1
WD@ 0.1U_0402_16V4Z

1
WD@ 0.1U_0402_16V4Z
DTR#
RTS#
TXD
CTS#
R I#
RXD
D CD#
DSR#

DTR#
RTS#
TXD
CTS#
RI#
RXD
DCD#
DSR#

FORCEOFF#

WD@

MAX3243CAI_SSOP28

217@ 2.7K_1206_8P4R_5%
4

RP30

RP31
LPD7
LPD6
LPD5
LPD4

LPD7
LPD6
LPD5
LPD4

4
3
2
1

5
6
7
8

F D7
F D6
F D5
F D4

2005/04/25

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

217@ 68_1206_8P4R_5%

Compal Secret Data

Security Classification

FD7
FD6
FD5
FD4

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

R ev
A

401395
Date:

@, 01, 2005

Sheet
E

32

of

48

+3VS

SUPER I/O SMsC LPC47N217

+3VS

1
C245
4.7U_0805_10V4Z

LPC_AD[0..3]

LPC_AD[0..3]

C300
0.1U_0402_16V4Z

217@
R354 1 217@

2 10K_0402_5%

SIO_SMI#

R364 2 217@

1 100K_0402_5% FIR_DET#

217@

U30

217@

LPC_FRAME#
LPC_DRQ#0
PCI_RST#
SIO_PD#

SIO_IRQ

R350 2

1@ 10K_0402_5%

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
PME#

IRRX

R347 1

2 10K_0402_5%

CLK_14M_SIO

Agilent IRRX unpop 10K


Vishay IRRX pop 10K

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

10
12
13
14

LAD0
LAD1
LAD2
LAD3

LPC_FRAME#
LPC_DRQ#0

15
16

LFRAME#
LDRQ#

SIO_RST#
SIO_PD#

17
18

PCI_RESET#
LPCPD#

PM_CLKRUN#
CLK_PCI_SIO
SERIRQ
PME#

19
20
21
6

CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#

CLK_14M_SIO

FIR_DET#

FIR_DET#

SIO_GPIO11
SIO_SMI#
SIO_IRQ

CLK_14M_SIO
+3VS
CLK_PCI_SIO

R349
@ 10K_0402_5%

R373
@ 10_0402_5%

8
22
43
52

VSS
VSS
VSS
VSS

C309
@ 15P_0402_50V8J

FIR IRRX2
IRTX2
IRMODE/IRRX3

37
38
39

IRRX
IRTXOUT
IRMODE

INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

INIT#
SLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

VTR
VCC
VCC
VCC
VCC

7
11
26
45
54

POWER

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1
IRRX
IRTXOUT
IRMODE
INIT#
SLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

+3VS

1
C273
+3VS

217@ 0.1U_0402_16V4Z

0 *= 02Eh
1 = 04Eh

SIO_GPIO11

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

LPC47N217-JV_STQFP64
217@

Base I/O L-Address

62
63
64
1
2
3
4
5

CLOCK

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

C280
@ 15P_0402_50V8J

R356
@ 10K_0402_5%

CLK14

23
24
25
27
28
29
30
31
32
33
34
35
36
40

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

SERIAL I/F

SIO_PD#

PARALLEL I/F

2 10K_0402_5%

LPC I/F

R372 1

GPIO

R357

Serial Port
for Debug

217@

1K_0402_5%

Port 80 Debug Card Connector

+5VS

**

JP5

L: R POP; FIR Enable


H: R De-POPFIR Disable

FIR Module

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

FIR_DET#

R363 1

1
2
3
4
5
6
7
8
9
10

2 1K_0402_5%
FIR@

JP8
PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

1
2
3
4
5
6
7
8
9
10

@ E&T_96212-1011S
+IR_ANODE
R417
1

1
2

C342
22U_1206_16V4Z_V1

2
1

C343
@ 10U_0805_10V4Z

R424
0_1206_5%
FIR@

1
C347
FIR@ 10U_1206_16V4Z

2
4.7_1206_5%
FIR@

(60mil)
U49

IR1
IRRX

+IR_3VS
(30mil)

1
R418
2

2
4
6
8

IRED_C
RXD
VCC
GND

IRED_A
TXD
SD/MODE
MODE

1
3
5
7

CLK_PCI_USB20
+5VS
PCI_RST#
PCI_FRAME#
PCI_TRDY#
PCI_AD9

CIR

@ 4.7_1206_5%
2

IRTXOUT
IRMODE

(30mil, 3via)
FIR@ TFDU6102-TR3_8P

1
GND

GND

VCC

ROUT

C344

R569

2
R100 2
R99 2
R98 2
R97

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
CLK_PCI_USB20_C
1
33_0402_5%
1
1 33_0402_5%
1 33_0402_5%
1 33_0402_5%
33_0402_5%

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_85201-2005
CIR@ 4.7U_0805_10V4Z

R423
1

CLK_PCI_USB20_C

(60mil)
+3VS

1
1
1
1
1
1
1
1
1
1
1
1
1

100_0805_5%

+5VALW
CIR_IN

R570
@10_0402_5%

+3VS

R572
R573
R574
R575
R576
R577
R578
R563
R564
R565
R566
R567
R568

2
2
2
2
2
2
2
2
2
2
2
2
2

R422
0_0402_5%
CIR@

TSOP6238-TR_4P

C618
FIR@ 0.1U_0402_16V4Z
2

1
C500
@ 18P_0402_50V8K

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE


MODE: HIGH/LOW SPEED SELECT

Compal Secret Data

Security Classification
2005/04/25

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

33

of

48

+3VALW

+3VALW

+3VALW
W D@ 0.1U_0402_16V4Z
C377 2

DCOCT1#

I0

DCOCT2#

I1

245
246

+DC_IN_S1

241

DKN_B+

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

DCOCT1#
+5VS

PS_CLK
KB_CLK

PS_CLK
KB_CLK

1394_PHYRST_S3P
DPCONF_S5P

1394_PHYRST_S3P
DPCONF_S5P

D_DDC_CLK
D_CRT_R
D_CRT_G
D_CRT_B
D_CRT_VSYNC
DVI_SCLK

D_DDC_CLK
D_CRT_R
D_CRT_G
D_CRT_B
D_CRT_VSYNC
DVI_SCLK

DVI_TXD2+
DVI_TXD2DVI_TXD1+
DVI_TXD1DVI_TXD0+
DVI_TXD0-

DVI_TXD2+
DVI_TXD2DVI_TXD1+
DVI_TXD1DVI_TXD0+
DVI_TXD0-

DVI_TXC+
DVI_TXCDVI_DET#

DVI_TXC+
DVI_TXCDVI_DET#

RJ45_MDI3+
RJ45_MDI3-

RJ45_MDI3+
RJ45_MDI3-

VCC
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S55
S56

59
60

M59
M60

253

GND

DOCKIN#

DOCKIN#
JP17B

W D@ TC7SH32FU_SSOP5

GND
GND

247
248

249
250

VCC

242

+DC_IN_S1

243

S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

DKN_B+

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173

S115

115

RJ45_MDI2-

S117

117

RJ45_MDI2+

DKN_B+
EJCTSW#

D_EC_SMB_CK2

EJCTSW#
+5VS

PS_DATA
KB_DATA

+5VS
+5VALW
XTPA1+

PS_DATA
KB_DATA

D_DDC_DATA

TPB1+

XTPB1+

1394_DILSON_S3P

TPA1+

1394_DILSON_S3P
D_DDC_DATA

Pin 73, 74 and 75


D_CRT_HSYNC
DVI_SDATA

for VGA GND

AUD_SUDMUT_P3#

AUD_SUDMUT_P3#

D_CRT_HSYNC
DVI_SDATA

LINEOL
LINEIL
LINEIR#

LINEOL
LINEIL
LINEIR#

DOCK_ON/OFFBTN#
DC D#
DSR#
TXD
R I#
LPTPE
F D7
F D6

DOCK_ON/OFFBTN#
DCD#
DSR#
TXD
RI#
LPTPE
FD7
FD6

F D4
F D1
F D2
F D0
R_LPTSTB#

FD4
FD1
FD2
FD0
R_LPTSTB#

+3VALW

RJ45_MDI2RJ45_MDI2+

MODEM
+5VALW

RJ45_GND
RJ45_MDI0+
RJ45_MDI0-

RJ45_GND
RJ45_MDI0+
RJ45_MDI0-

+3VALW

GND
GND

251
252

VCC

VCC

244

S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
S171
S172
S173

S181
S182
S183
S184
S185
S186
S187
S188
S189
S190
S191
S192
S193
S194
S195
S196
S197
S198
S199
S200
S201
S202
S203
S204
S205
S206
S207
S208
S209
S210
S211
S212
S213
S214
S215
S216
S217
S218
S219
S220
S221
S222
S223
S224
S225
S226
S227
S228
S229
S230
S231
S232
S233
S234
S235
S236

181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236

LAN_ACTIVITY#
LAN_LINK#
DCOCT2#

L239
L240

239
240

RJ45_MDI1+
RJ45_MDI1-

GND

254

GND
GND

175

S175

178
179
180

L178
L179
L180

DKN_B+
D_EC_SMB_DA2
+5VS
TPA1-

XTPA1-

TPB1USB20_P6
USB20_N6

XTPB1USB20_P6
USB20_N6

LINEOR
LINEOR#
LINEOL#
LINEIL#
LINEIR

LINEOR
LINEOR#
LINEOL#
LINEIL#
LINEIR

RXD
RTS#
CTS#
DTR#
LPTSLCT
LPTBUSY
LPTACK#
F D5

RXD
RTS#
CTS#
DTR#
LPTSLCT
LPTBUSY
LPTACK#
FD5

F D3
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#

FD3
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#

LAN_ACTIVITY#
LAN_LINK#

LAN
RJ45_MDI1+
RJ45_MDI1-

MDC1_RING
MDC2_TIP

55
56

GND
GND

W D@ 10K_0402_5%

JP17A

R453

R456

R459
100K_0402_5%

U38

Docking Conn.

W D@ 10K_0402_5%

2
G

R23
W D@ 100K_0402_5%

W D@ TYCO_1674036

3 Q6
W D@ 2N7002_SOT23

1394_DILSON_S3P

W D@ TYCO_1674036

JP1
W D@

1
2
3
4

R20

+5VALW

2
W D@

+5VALW

D_EC_SMB_DA2

Q5
2N7002_SOT23

Compal Secret Data

Security Classification

W D@ ACES_87213-0410

W D@ 4.7K_0402_5%
2

EC_SMB_DA2

D_EC_SMB_CK2
4.7K_0402_5%

Q3
2N7002_SOT23

MDC to Docking Conn.


MDC1_RING
MDC2_TIP

1
D

W D@

3
S

EC_SMB_CK2

R17

2005/06/01

Issued Date

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

34

of

48

+3VALW

+LDO3_EC

+LDO3_EC

2
G

INT_FLASH_SEL

SUS_STAT#

I1

O
G

EC_FLASH#

FWE#

I0

U22

U19A

SUSP#

0.1U_0402_16V4Z

R312
100K_0402_5%

OE#

SN74LVC125APWLE_TSSOP14

14

SB_INT_FLASH_SEL#

C242

Q20
2N7002_SOT23

TC7SH32FU_SSOP5

FWR#
+3VALW

C240 1

R314
10K_0402_5%

INT_FLASH_EN#

OE#

2 22_0402_5%

FSEL#

R3221

1
+5VALW
INT_FSEL#

R313 1
100K_0402_5%

U19B

+5VALW

2 0.1U_0402_16V4Z

R335

2 0.1U_0402_16V4Z

SN74LVC125APWLE_TSSOP14
100K_0402_5%

C244 1

1
U24

1
2
3
4

AT24C16AN-10SI-2.7_SO8

0_0402_5%

U19C

8
13

A0
A1
A2
GND

2
@

SN74LVC125APWLE_TSSOP14

U19D

11

12

OE#

VCC
WP
SCL
SDA

10

8
7
6
5

OE#

EC_SMB_CK1
EC_SMB_DA1

R321

R326
SN74LVC125APWLE_TSSOP14

100K_0402_5%

KBA[0..19]

KBA[0..19]

ADB[0..7]

ADB[0..7]

1MB ROM Socket


1MB Flash ROM

JP30
+LDO3_EC

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

U23

FRD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

INT_FSEL#
FR D#
FWE#

22
24
9

CE#
OE#
WE#

VCC0
VCC1

31
30

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

RP#
NC
READY/BUSY#
NC0
NC1

10
11
12
29
38

GND0
GND1

23
39

SST39VF080-70_TSOP40

1
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
RESET#

1
R344

C259
0.1U_0402_16V4Z

100K_0402_5%

+LDO3_EC

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

KBA17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
+3VALW
ADB3
ADB2
ADB1
ADB0
FR D#
FSEL#
KBA0

SUYIN_80065AR-040G2T

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet

35

of

48

1
R244

2
100K_0402_5%

5 In 1 Card LED
(Close to Socket)

+3VALW

D11

INBTN#

IE_BTN#

51ON#

+3VS

51ON#

DAN202U_SC70

R665
150_0603_5%

2
+LDO3_EC
100K_0402_5%

1
R270

+5VALW
+5VALW

Battery LED
AC-IN LED

+3VALW

D19

1
R664
300_0603_1%

PWR_SUSPLED0#
ACIN

2 120_0402_5%

PWR_SUSPLED1#

D21
HT-297UD/NB_BLUE/AMB_0603

Q46
S
2N7002_SOT23

R668 1

HDD LED

2
G

Change from 300 to 120


R667 1
2 120_0402_5%

DTA114YKA_SC59

PWR_SUSP_LED#

Low Active

2
@ 0_0402_5%

Amber
R663
300_0603_1%

2
G
3

R6611

R662
300_0603_1%

Green

1
D

Green

HT-191UYG-DT_GRN_0603
PWR_SUSP_LED#

10K

Q48

Q45
2N7002_SOT23

SY SON

47K

ACES_85201-1205

ON/OFFBTN#

MODE#
51ON#

DAN202U_SC70

1
2
3
4
5
6
7
8
9
10
11
12

INBTN#
PWR_LED0#
PWR_SUSPLED0#
Mode_Key

5IN1_LED#

2
3

JP4
KSI2
KSI3
KSI4
KSI5
KSO3

HT-191UYG-DT_GRN_0603

D12

Mode_Key 1

Green
D23

Vivace(SW-DJ) Button
PWR BTN/B

10C/10GC:Green:SC591UYG000
10/10C:Blue:SC5191NB000

BATT_CHGI_LED#

BATT_LOW_LED#

+5VS

R666
300_0603_1%

10/10C:Blue/Amber:SC597UDB000
10C/10GC:Green/Amber:SC500001900
+5VALW

Power LED

D22

SYSON

2
G

47K

10K

HDD_LED#

Q8
2N7002_SOT23
1
R54 1

PWR_LED#

Wireless Lan LED

PWR_LED#

Low Active
+5VS

Change from 120 to 300


R465 1
2 300_0402_5%

PWR_LED0#

R466 1

PWR_LED1#

R669
150_0402_5%

2 300_0402_5%

2
@ 0_0402_5%

Amber

D34

Amber:SC5110UD000

Amber
WL_LED
D20
PWR_SUSPLED1#

PWR_LED1#

WL_LED 2
G
Q47
2N7002_SOT23

HT-110UD_1204
D

HT-191UYG-DT_GRN_0603

Q7
DTA114YKA_SC59

Green

4
1
HT-297UD/NB_BLUE/AMB_0603

Green

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Re v
A

401395
Date:

, 01, 2005

Sheet

36

of

48

INT_KBD CONN.
KSO[0..17]

MDC 1.5 Conn.


1
3
5
7
9
11

ACZ_SDOUT_MDC

ACZ_SYNC_MDC
ACZ_SDIN1
ACZ_RST#_MDC

R324 1
2
33_0402_5%

ACZ_SYNC_MDC
ACZ_SDIN1_MDC
ACZ_RST#_MDC

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

13
14
15
16
17
18

+3VS

1
C229

1000P_0402_50V7K
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

2
4
6
8
10
12

ACZ_BITCLK_MDC

ACZ_BITCLK_MDC

GND
GND
GND
GND
GND
GND

ACZ_SDOUT_MDC

JP10

+3VS

JP27

C236

KSO[0..17]
KSI[0..7]

KSI[0..7]

ACES_88018-124G

Connector for MDC Rev1.5


C241
@ 4.7U_0805_10V4Z

2
2
0.1U_0402_16V4Z

KSO15
KSO14
KSO10
KSO11
KSO8
KSO9
KSO13
KSI7
KSO3
KSO7
KSO12
KSI4
KSI6
KSI5
KSO6
KSO5
KSI3
KSI0
KSO0
KSO1
KSI1
KSI2
KSO2
KSO4

NUM_LED#
PADS_LED#
CAPS_LED#
1
300_0402_5%

1
300_0402_5%

1
300_0402_5%

2
R135

+3VS

+3VS

R582

+3VS

R583

ACES_88170-3400

100P_1206_8P4C_50V8
KSO8
1
8
KSO9
2
7
KSO13
3
6
KSI7
4
5

Reserved power button


SW1

Power Button

CP2

RTCVREF

+3VALW

D5

1
2
R419 47K_0402_5%

0_0402_5%
U34
A3212EEH_MLP6
5

ON/OFFBTN#

NC

51ON#

51ON#

C345

DAN202U_SC70

NC

2 C190

D8

0.1U_0402_16V4Z

LID_SW#

LID_SW#

1
3

KSO15
KSO14
KSO10
KSO11

1
2
3
4

8
7
6
5

CP6

CP1

S4_LID_SW#

1
2
3
4

100P_1206_8P4C_50V8
KSO3
1
8
KSO7
2
7
KSO12
3
6
KSI4
4
5

8
7
6
5

CP3
100P_1206_8P4C_50V8

DAN202U_SC70
C346

KSI3
KSI0
KSO0
KSO1

2
3

2
2

L ID

ON/OFF

1
RTCVREF

VDD OUTPUT

GND

D6

100P_1206_8P4C_50V8
KSI1
KSI2
KSO2
KSO4

8
7
6
5

CP4

D24

100K_0402_5%

1
2
3
4

100P_1206_8P4C_50V8

1
R177

KSI6
KSI5
KSO6
KSO5

R416
100K_0402_5%

R412

PSOT24C_SOT23

10P_0402_25V8K

1
2
3
4

8
7
6
5
CP5

R156
1
1000P_0402_50V7K

100K_0402_5%
WD@

RLZ20A_LL34

2 1

100K_0402_5%
WD@

R163

+LDO3_EC
2

SMT1-05_4P

ON/OFFBTN#

100P_1206_8P4C_50V8

Lid Switch

2
6
5

Q15
D

1
2
G

JP9
R195

2N7002_SOT23
@ 0_0402_5%

TP Button

10K_0402_5%
SW3
SW_L

SW_R

SMT1-05_4P

TP_DATA
TP_CLK

TP_DATA
TP_CLK

SW2

6
5

R170

2
1

+5VS

TP CONN.

EC_ON

4
6
5

2N7002_SOT23
WD@

Q14

DOCK_ON/OFFBTN#

SW_L
SW_R
R102 2

SMT1-05_4P

1
@ 0_0402_5%

12
11
10
9
8
7
6
5
4
3
2
1

C125
0.1U_0402_16V4Z

ACES_87151-1207
Touchpad mount direction:
Standard: N/A, Reverse: Stuff

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet

37

of

48

+3VS

SUPER I/O SMsC LPC47N207

Finger printer

C507
0.1U_0402_16V4Z

LPC_AD[0..3]

+3VS
R562
R561
3

USB20_N0
USB20_P0

JP6
1
2
3
4
5

0_0402_5%
2
1
2
1
0_0402_5%

LPC_AD[0..3]
D

ACES_85201-0505

1
1

C301
SI207@ 4.7U_0805_10V4Z

D31
@ PACDN042_SOT23~D
1

C269
SI207@ 0.1U_0402_16V4Z
2

C260
SI207@ 0.1U_0402_16V4Z

2
C585

T32 PAD

GPIO
GPIO2

8
9

TEST1
TESTB1/BADD

R642
4.7K_0402_5%

1
1
0.1U_0402_16V4Z

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

26
23
20
17
22
16
28
27
21

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#
SUS_STAT#
SIRQ
CLK_PCI_TCG

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#
SUS_STAT#
SIRQ
CLK_PCI_TCG

CLKRUN#

15

PM_CLKRUN#

R637
0_0402_5%

VTR

+3VS

5
17
31
42
60
3.3V
3.3V
3.3V
3.3V
3.3V

GPIO

IRTXOUT
IRRX
IRMODE

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

R331
@ 10K_0402_5%

IRTXOUT
IRRX
IRMODE

Base I/O Address


0 *= 02Eh
1 = 04Eh

PM_CLKRUN#

LPC47N207-JN_STQFP64
SI207@

R327
SI207@ 1K_0402_5%

+3VS

XTALO

14

4.7K_0402_5%
TPM_XTALO

XTALI/32K IN

13

TPM_XTALI

NC
NC
NC
GND
GND
GND
GND

PP
3
12
1

49
50
51

DTR#1 1
2
R330
SI207@ 10K_0402_5%

R633

2
R644
@ 4.7K_0402_5%

IRTX2
IRRX2
IRMODE/IRRX3

FIR_DET#

RTS#1

S L B 9 6 3 5 T T 1.2

C598

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

FIR_DET#

VDD
VDD
VDD

6
2

DLPC_CLK_33
DLDRQ1#
DLFRAME#
DCLKRUN#
DSER_IRQ
DSIO_14M

52
53
54
55
56
57
58
59

RXD1 1
2
R332
SI207@ 1K_0402_5%

VSB
T35 PAD

2
C601

1
U46

9
11
13
15
18
26

0.1U_0402_16V4Z

RXD1
TXD1
DRSR1#
RTS1#/SYSOPT0
CTS1#
DTR1#/SYSOPT1
RI1#
DCD1#

8
7
6
5
4.7K_8P4R_1206_5%

GND0
GND1
GND2
GND3
GND4
GND5

0.1U_0402_16V4Z

+3VS

DLAD0
DLAD1
DLAD2
DLAD3

1
2
3
4

63
1
3
6

GPIO10
GPIO11
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37

SERIAL I/F

0.1U_0402_16V4Z
C584

10
19
24

TPM1.2 on board

+3VS

LPC_CLK_33
LDRQ1#
LDRQ0#
LFRAME#
CLKRUN#
SERIRQ
PCI_CLK
PCIRST#
SIO_14M
LPCPD#
IO_PME#

DCD#1
RI#1
CTS#1
DSR#1

27
28
30
32
33
34
35
36
38
39
40
41
43
44
46
61

8
20
29
37
45
62

+3VALW

CLK_14M_SIO
SIO_PD#
PME#

10
12
24
14
16
19
21
22
23
25
47

RP26

IR

LPC_DRQ#1
LPC_FRAME#
PM_CLKRUN#
SERIRQ
CLK_PCI_SIO

LAD0
LAD1
LAD2
LAD3

LPC I/F

LPC_DRQ#1
LPC_FRAME#
PM_CLKRUN#
SIRQ
CLK_PCI_SIO
PCI_RST#
CLK_14M_SIO
SIO_PD#
PME#

64
2
4
7

DLPC I/F

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

48

+3VS
U29

+3VS

SLB 9635 TT 1.2_TSSOP28

4
11
18
25

Base I/O Address


0 = 02Eh
* 1 = 04Eh

C299

+3VALW
0.1U_0402_16V4Z
1
C272

2
2
0.1U_0402_16V4Z

C612 1
1

TPM_XTALI

C581

0.1U_0402_16V4Z

18P_0402_50V8J
2
32.768KHZ_12.5P_1TJS125BJ2A251
NC 2

IN

OUT

NC

R657

Y4
TPM_XTALO
C610 1
10M_0402_5%

2
18P_0402_50V8J

Compal Secret Data

Security Classification
2005/06/01

Issued Date

2006/06/01

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
1

38

of

48

+5VALW

R635
FM1
47K_0402_5%

FM2

FM4

FM6

FM5
1

CF7

CF5

CF4

CF6

CF13 CF14

R636

CF3

CF11 CF12 CF10 CF9

1
CF8

+5VALW

CF2

CF1

Q43
2N7002_SOT23

S
1

2
G

SYSON

FM3

SYSON#

SYSON#

10K_0402_5%

Q44
2N7002_SOT23

2
G

SUSP#

H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
D

SUSP

SUSP

+5VALW to +5VS Transfer

+3VALW to +3VS Transfer


+3VALW

+5VALW

+5VS

+3VS
0.1U_0402_16V4Z

D
D
D
D

1
2
3
4

S
S
S
G

SI4800DY_SO8

C205

1
2
3
4

SI4800DY_SO8

10U_0805_10V4Z

C250

470_0402_5%

2
G

SUSP

Q22
2N7002_SOT23
S

2
G

R611
Q41
2N7002_SOT23

R323

2
D

D
Q42

SUSP

S
2N7002_SOT23

470_0402_5%
2

C246

RUNON

2
1

S
S
S
G

470_0402_5%

RUNON

2
G
3

SUSP

R613

D
D
D
D

R612
330K_0402_5%

1
C208
10U_0805_10V4Z

C249
10U_0805_10V4Z

8
7
6
5

B+

8
7
6
5

C216
10U_0805_10V4Z

0.1U_0402_16V4Z

U25
U15

C557
0.01U_0402_16V7K

+1.8V to +1.8VS Transfer


+1.8V
+2.5VS

+1.8V

+1.5VS

+VCCP

+1.8VS
0.1U_0402_16V4Z

2
G
3

2
G

SUSP

Q16

S
2N7002_SOT23

C8
10U_0805_10V4Z

C9

470_0402_5%

2
G

SUSP

D
RUNON

S
2N7002_SOT23

R5

2
2

SI4800DY_SO8

1
2
3
4

Q17

S
2N7002_SOT23

S
S
S
G

D
SYSON#

Q11

C10
10U_0805_10V4Z

D
D
D
D

D
2 SUSP
G

S
2N7002_SOT23

1
470_0805_5%

1 2

R203

470_0805_5%
1 2

R237

470_0805_5%
1 2

R94

470_0805_5%
1 2

R4

D
Q2

U5
8
7
6
5

Q1
2N7002_SOT23

2
G

SUSP

S
+0.9VS

R91

1 2

470_0805_5%
D
Q9

2
G

2005/06/01

Issued Date

2006/06/01

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

2N7002_SOT23

Compal Secret Data

Security Classification

SUSP

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet
E

39

of

48

VS
VIN

1
PR7
10K_0402_5%

PR10

1000P_0402_50V7K

10K_0402_5%

1000P_0402_50V7K
VIN

RTCVREF

3.3V

Vin Detector

PD2

PD1
PR167

PR11

2
2

1
@ TP0610K_SOT23

PR13

PC8
0.1U_0603_25V7K

1
PD4

VIN

1 PR15

1 PR16

PU2
S-812C33AUA-C2N-T2_SOT89

1K_1206_5%

1
OUT

IN

PR19
499K_0402_1%

PC10
10U_0805_10V4Z

PC9
1U_0805_25V4Z

GND

PR20

VL

PR21

10K_0402_5%

2.2M_0402_5%

8
-

6
1

PC12

PR25
237K_0402_1%
PR24

0.1U_0402_16V7K

66.5K_0402_1%

+0.9VS

PR26

JUMP_43X118

1000P_0402_50V7K

PQ2

2
G

(2A,80mils ,Via NO.= 4)


+1.8VP

PJ7 PJ5
2 2

+1.8V

JUMP_43X118
@
2
1 1

+2.5VSP

@ PJ6
2 2

PACIN

47K_0402_5%

2N7002-7-F_SOT23-3

+2.5VS

14.3V/13.18V for adapter

(2A,80mils ,Via NO.= 4)

JUMP_43X118

Precharge detector

JUMP_43X118

2
@

1
1

@ PJ4
2 2

+0.9VSP

(5A,200mils ,Via NO.= 10)

+5VALW

VL

34K_0402_1%

LM393DG_SO8 PC13

JUMP_43X118

PC11
1000P_0402_50V7K

499K_0402_1%

RB715F_SOT323

ACON

+5VALWP

+1.5VS

1 PR23

@ PJ3
2 2

JUMP_43X118

(3.5A,140mils ,Via NO.= 7)

PR22

+1.5VSP

O
G

+3VALW

(5A,200mils ,Via NO.= 10)

JUMP_43X118

+3VALWP

MAINPWON

PD5
@ PJ2
2 2

PU1B

@ PJ1
2 2

560_0603_5%

560_0603_5%

B+

3.3V

PR18

PR17

1K_1206_5%

1N4148_SOD80

RTCVREF

+CHGRTC

1K_1206_5%

2
@ 22K_0402_5%

1
PR14

0.22U_1206_25V7M

PC7
@

PR12
@100K_0402_5%

51ON#

200_0603_5%

VS

PQ1

PR9
68_1206_5%

PR8

PR168 68_1206_5%
1538VCC

2
1

High 14.57 14.01 13.46


Low 14.06 13.51 12.98

1N4148_SOD80

1N4148_SOD80

68_1206_5%
1
2

68_1206_5%

BATT_A

PACIN

RLZ4.3B_LL34

100P_0402_50V8J

PD3

PC6
0.1U_0402_16V7K

1000P_0402_50V7K

20K_0402_1%

PACIN

LM393DG_SO8

PR6

PC5
100P_0402_50V8J

ACIN
1

O
-

SINGA_2DW-0005-B03
@

PC4

2
3
15.4K_0402_1%
2

PC3

1
PR5

PU1A

PC2

PC1

1
2
PR4
1K_0402_5%

61.9K_0402_1%

PR2
5.6K_0402_5%

2
1M_0402_1%

VS
PR3

12A_65V_451012MRL

FBMA-L18-453215-900LMA90T_1812

1
PR1

DC_IN_S1

DC_IN_S2
PJP1

VIN

PF1

+DC_IN_S1
PL1

PQ3

+5VALWP

DTC115EUA_SC70

(8A,320mils ,Via NO.= 16)


4

+VCCPP

@ PJ8
2 2

+VCCP

JUMP_43X118

(3.5A,140mils ,Via NO.= 7)


Compal Secret Data

Security Classification
Issued Date

2005/06/23

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size
B
Date:

Document Number

Rev
A

401395
, 01, 2005

Sheet
D

40

of

48

PH1 under CPU botten side :


CPU thermal protection at 84 degree C
Recovery at 45 degree C
1

2
1

47K_0402_1%

MAINPWON

PQ4
DTC115EUA_SC70
PD6

PR32
1
2
13.7K_0402_1%
TM_REF1

PC14
0.1U_0603_25V7K
PR30
1
2
47K_0402_1%
PU3A
3 +
O 1
2 -

LM393DG_SO8

1SS355_SOD323

PR37

2
PC18

VL

100K_0402_1%

1K_0402_5%

PR36
22K_0402_1%

1
PR38

+3VALWP

PC17
0.22U_0805_16V7K

ALI/MH#
PR35
6.49K_0402_1%

VL

PR27

PH1

PC16
0.01U_0402_25V7Z

VS

PC15
1000P_0402_50V7K

VL

+3VALWP

BATT

PL2

1K_0402_5%

PR31

1
1

SUYIN_250005MR007G132ZR

PR29
47K_0402_5%

PR33

PF2

1K_0402_5%
1 PR28
2

2
3
4
5
6
7

ALI/NIMH#
AB/I
TS_A
EC_SMDA
EC_SMCA

100_0402_5%

BATT_S1

ID
B/I
TS
SMD
SMC
GND

100_0402_5%
PR34
1
2

BATT+

VMB_A
FBMA-L18-453215-900LMA90T_1812
1
2

12A_65V_451012MRL
1
2

100K_0603_1%_TH11-4H104FT

PJP2

PR39

BATT_TEMPA

100K_0402_1%

EC_SMB_DA1
EC_SMB_CK1
1000P_0402_50V7K

PH2 near main Battery CONN :


BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL

PR41
1
2
47K_0402_1%

PD7

O
4

PR43

PU3B

TM_REF1

1
1

PR42
10.7K_0402_1%
1
2

1
1SS355_SOD323

LM393DG_SO8

22K_0402_1%

PC19
0.22U_0805_16V7K

PR40
47K_0402_1%

PH2

100K_0603_1%_TH11-4H104FT

VL

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/06/23

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

SCHEMATIC, M/B LA-3011


Size
B
Date:

Document Number

Rev
A

401395
, 01, 2005

Sheet
D

41

of

48

P3

B+
PQ5
AO4407_SO8

0.015_2512_1%

B++

JUMP_43X118

PC20
4.7U_1206_25V6K

PC21
4.7U_1206_25V6K

PC22

8
7
6
5

4.7U_1206_25V6K

1
2
3

8
7
6
5

1
2
3

@ PJ9
2 2

1
2
3

PR44

PQ7
AO4407_SO8

PQ6
AO4407_SO8

8
7
6
5

Iadp=0~4.7A

P2

VIN

-INE2 VCC(o)

21

FB2

OUT

20

VREF

VH

19

FB1

8
9

+INE1

-INE3

16

OUTC1

FB3

15

11

OUTD

CTL

14

12

-INC1

+INC1

13

0.1U_0402_16V7K

PC33
2
1

2
100K_0402_1%

PL3
PR60
1
2
47K_0402_5%
ACON

PC32
1
2

PR58

16UH_D104C-919AS-160M_3.7A_20%

1500P_0402_50V7K
PD9
EC31QS04

BATT

0.02_2512_1%

PD10
EC31QS04

MB3387PFV-ERE1_SSOP24~N

PR174
47K_0402_5%

PR61

CC=0.5~3.0A
CV=12.6V(6 CELLS LI-ION)

0.1U_0603_25V7K
1
2
PR55
68K_0402_5%

1 2

+3VALWP

43K_0402_5%

IREF=1.07*Icharge
IREF=0.6V~3.21V

PR175
1

ACON

1
10
10K_0402_5%

DTC115EUA_SC70

PC36

17

LXCHRG
PC31
1
2

4.7U_1206_25V6K
PC35

RT

1
2
PC28
0.1U_0603_25V7K

4.7U_1206_25V6K

-INE1

ACOFF

PC34

18

2
PQ11

4.7U_1206_25V6K

VCC

PR56

2
PR59

PC25
1
2
0.1U_0603_25V7K

CS

22

PQ9
AO4407_SO8
ACOFF#

CS

3
2
1

+INE2

N18

5
6
7
8

PR50 1

PC24
0.022U_0402_16V7K
1
2

IREF

25.5K_0402_1%

162K_0402_1%
1
2

23

PQ13

3K_0402_1%

OUTC2 GND

VIN

PACIN

2
G
3

1SS355_SOD323
PR57
PACIN
1
2

D 2N7002-7-F_SOT23-3

47K_0402_5%
PR48
1K_0402_5%

PD8
ACOFF#1
2

PC30
PR54
1
2 1
2
1K_0402_5%
1000P_0402_50V7K

24

2N7002-7-F_SOT23-3

PC27
PR52
2 1
2
10K_0402_5%
4700P_0402_25V7K

0.1U_0402_16V7K

PC29
1

100K_0402_1%

DTC115EUA_SC70

PC26
2
1

1
PQ12

PR53

PQ10

2
G

12.7K_0402_1%

0.1U_0402_16V7K
PR51
2
1

DTA144EUA_SC70

+INC2

1
100K_0402_5%

-INC2

2
PR49

ADP_I

PR45

PR47

PU4

47K

PC23

47K

PQ8
0.1U_0603_25V7K

PR46
47K_0402_5%

200K_0402_1%

2
1

PQ39
PR62

DOCKIN#

PR176

PR63

4.2V

150K_0603_0.1%

300K_0603_0.1%

47K_0402_5%
PD13

DKN_B+

PQ40

PQ16
AO4407_SO8

3
1

DTC115EUA_SC70

Adapter

Iadp

PR50

75W

4.7A

25.5K_0402_1%

90W

5.52A

20K_0402_1%

8
7
6
5

1SS355_SOD323

+3VALWP

CS

PQ14

PR68
499K_0402_1%

LM358ADR_SO8

1
A

PC38
0.01U_0402_25V7Z

105K_0402_1%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2.2K_0402_5%

DTC115EUA_SC70

PR70

LM358ADR_SO8

PQ17

PR69

8
P
G

0
4

DKN_B+_ON

(BAT_OVP=0.1111 *VMB)

OVP voltage : LI
3S3P : 13.5V--> BATT_OVP= 1.5V

2
8
P

PU5A
+ 3

BATT_AOVP

10K_0402_1%

VS

DTC115EUA_SC70

PR67

PC37
1U_1206_25V7K

1 2

DTC115EUA_SC70

PU5B
+ 5

PR65
340K_0402_1%

PQ15

B+

2
2

FSTCHG

PR66
27K_0402_1%
1
2

VMB_A

PR64
47K_0402_5%

1
2
3

DOCKING_CTRL

B+

DTC115EUA_SC70

2005/06/23

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

SCHEMATIC, M/B LA-3011


Size
B
Date:

Document Number

Rev
A

401395
, 01, 2005

Sheet
D

42

of

48

+3.3VALWP/+5VALWP

B+++

B+++

PD11
DAP202U_SOT323

PC55
4.7U_0805_6.3V6K

1
2

5
6
7
8
D
D
D
D

1 PR171

1
2

150U_V_6.3VM_R18

PC53

1
2

+LDO3

PR90
0_0805_5%

@ 0_0805_5%

2
G

2
G

EC_ON

2 AC IN
G

PQ24
@ RHU002N06_SOT323

Compal Electronics, Inc.

Compal Secret Data


2005/06/23

Issued Date

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

G
S
S
S
2

10

25

23
PC54
2
1

+3VALWP

Security Classification

4
3
2
1
5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1
2

PR77
43.2K_0402_1%

1
2

FB3

@
PQ23
RHU002N06_SOT323

PQ22
@RHU002N06_SOT323

PR93
100K_0402_5%
PC56
@ 0.047U_0603_16V7K

PL5

DL_3V

MAX8734AEEI+_QSOP28
PR88
0_0402_5%
1
2

LDO3P

LDO3P

PC50
0.1U_0603_25V7K
2
1

POK
0.22U_0603_16V7K

1
PR91

PR92
@ 0_0402_5%
2
1

0_0603_5%
LX_3V

VL

LX_3V

PR86
6.81K_0402_1%

REF

7
2

FB3
PGOOD

PR82
BST_3V
DH_3V

SI4810BDY-T1-E3_SO8

PR81
0_0603_5%

ILIM5

28
26
24
27
22

PR80
499K_0402_1%

11

ILIM5
BST3
DH3
DL3
LX3
OUT3

PR76
118K_0402_1%

1
2
ILIM3

PR79
499K_0402_1%

PQ20

PR89
10K_0402_1%

SKIP#

PC43
4.7U_1206_25V6K
2
1

1
2
PC46
1U_0603_10V6K

2
VCC

TON

17

20

13

V+

ILIM3

1
12

2VREF_8734

806K_0603_1%

1
SHDN#
ON5
ON3

PC52
@ 1U_1206_25V7K

PR172

MAINPWON

PR85
10K_0402_5%
100K_0402_5%

2
PR87
6.81K_0402_1%

ACIN

PR84
47K_0402_5%

6
4
3

PR83
10.5K_0402_1%

PD12
RLZ5.1B_LL34

1
2

LX5
DL5
OUT5
FB5
N.C.

SI4800BDY-T1-E3_SO8

PRO#

FB5

PC51

150U_V_6.3VM_R18

DH5

15
19
21
9
1

18

DL_5V

2VREF_8734

LDO3

LX_5V

VS

16

LD05

0_0603_5%
PU6
1 BST_5V14 BST5

PR78
2

GND

S
S
S
G
1
2
3
4

PC49
0.1U_0603_25V7K
2
1

PC44
0.1U_0402_16V7K

PQ18

4.7U_LF919AS-4R7M-P3_5.2A_20%

+5VALWP

PC47
4.7U_0805_6.3V6K
2
1

8
7
6
5
D
D
D
D

DH_5V

2
1
PR73
10_1206_5%
1 PC48
0.1U_0603_25V7K

VL

PQ21
SI4810BDY-T1-E3_SO8

PL4
4.7U_LF919AS-4R7M-P3_5.2A_20%

PR74
0_0805_5%

PR75
0_0603_5%
1
2

PC45
4.7U_1206_25V6K
PR72
10_1206_5%
2
1
2
1

@ 0_0805_5%

S
S
S
G
1
2
3
4

SI4800BDY-T1-E3_SO8

PR71
47_0402_5%

8
7
6
5

PR170

B+++

+LDO5
PQ19

PC42
4.7U_1206_25V6K
2
1

VL

D
D
D
D

PC41
2200P_0402_50V7K
2
1

JUMP_43X118
@

PC40
4.7U_1206_25V6K
2
1

PC39
4.7U_1206_25V6K
2
1

B+

PJP3

Title

SCHEMATIC, M/B LA-3011


Size Document Number
Custom
401395
Date:

, 01, 2005

Rev
A
Sheet
1

43

of

48

B+

PR94

FBMA-L18-453215-900LMA90T_1812
PC60
2

+5VALW

PC59

0_1206_5%
2

4.7U_1206_25V6K

PC58

4.7U_1206_25V6K

PC57

PL6
1

2
1

5
6
7
8
D
D
D
D

PHASE2

25

ISEN1

ISEN2

22

LGATE2

27

0_0603_5%

+1.5VSP

LX_1.5V

ISE_1.8V
2
2K_0402_1%
DL_1.8V

LGATE1

PR103
1
2
1.4K_0402_1%

ISE_1.5V

D
D
D
D

PR102
1

4.7U_LF919AS-4R7M-P3_5.2A_20%
2
PL8

5
6
7
8

SI4810BDY-T1-E3_SO8
PR101
0_0402_5%

+1.5VSP

SI4800BDY-T1-E3_SO8

DH_1.5V

PQ28
SI4810DY-T1-E3_SO8
G
S
S
S

PR104

4
3
2
1

0_0402_5%

OCSET2

18

SUSP

PR107 10K_0402_1%

PC72
1

13

PC70
220U_D2_4VM_R15

VSE_1.5V
1

ISL6227CAZ-T_SSOP28

PR109

@ 0.1U_0402_16V7K

PR112

PR110
10K_0402_1%
2

@ 0_0402_5%

100K_0402_1%

PR113
100K_0402_1%

OCSET1

11

@ 0.1U_0402_16V7K

DL_1.5V

20
19
21
16

VOUT2
VSEN2
EN2
PG2/REF

DDR

VOUT1
VSEN1
EN1
PG1

2
PR111
@ 0_0402_5%

PR106
47K_0402_1%
PC73

PR108
10K_0402_1%

PGND2

9
10
8
15

SYSON

PGND1

26

GND

VSE_1.8V

0.01U_0402_25V
PC71

PHASE1

1 PR99

PR105
2

UGATE2

DH_1.5V-1

6.81K_0402_1%

UGATE1

24

1
2
3
4

0_0603_5%

0_0603_5% 0.1U_0402_16V7K

DH_1.8V-1

PQ26

BOOT2

0.01U_0402_25V7Z
PR97
PC67
BST_1.5V-2
1
2 2
1
23

1 PR98
S
S
S
G

PQ27

BOOT1

PC65
1

17

PC66
PR96
2
1
1
2BST_1.8V-2 6
0.1U_0402_16V7K
0_0603_5%

SOFT2

G
S
S
S

SOFT1

28

14

PU7
12

0.01U_0402_25V7Z
2

1
2

PC69

1
PR100
220U_D2_4VM_R15

10K_0402_1%

D
D
D
D

PC68

PC64
2
1

0.01U_0402_25V7Z
8
7
6
5

DH_1.8V-2

LX_1.8V

PL7

2.2U_0805_10V6K

4
3
2
1

2.2_0603_5%

VCC

VIN

BST_1.8V-1

D
D
D
D
S
S
S
G
1.8U_D104C-919AS-1R8N_9.5A_30%

1
2
3
4

+1.8VP

PC62
0.1U_0603_25V7K

PC63

BST_1.2V-1

SI4800BDY-T1-E3_SO8

8
7
6
5

PQ25

+1.8VP

DAP202U_SOT323

4.7U_1206_25V6K
PR95

1
2

PD14

PC61
4.7U_0805_6.3V6K

4.7U_1206_25V6K

Compal Secret Data

Security Classification
Issued Date

2005/06/23

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size Document Number


Custom
401395
Date:

, 01, 2005

R ev
A
Sheet

44

of

48

PL9
D

2
PHASE_VCCPP
UG_VCCPP
PR114
1

0_0603_5%

PC78 0.1U_0402_16V7K
+5VS

BOOT_VCCPP

PC77
10U_1206_25V6M

FBMA-L18-453215-900LMA90T_1812

PC76
10U_1206_25V6M

B+

5
6
7
8
D
D
D
D

13

2
BOOT
PVCC

12

LG

11

PR1152

2.2U_0603_6.3V6K
6269_VCC

PC80
2.2U_0603_6.3V6K

PR116
2

PGND

10

PL10

D
D
D
D
ISEN

+VCCPP

1
+

PQ30
SI4810BDY-T1-E3_SO8

PC81
220U_D2_4VM_R15

11.5K_0402_1%

4
3
2
1

VO

FSET
7

FB

1
PC83

PR117
1ISEN_VCCPP
2

+1.05V

1.8UH_SIL104R-1R8PF_9.5A_30%
2

G
S
S
S

EN

2
0_0402_5%

FCCM

0_0402_5%

COMP

SUSP#

PR173

VCC

SI4800BDY-T1-E3_SO8

LG_VCCPP

5
6
7
8

PQ29

6269_VCC

4.7_0603_5%
1
2 PC79

G
S
S
S

UG

4
3
2
1

VIN

PHASE

PGOOD

14

PU8

15

16

PR169
@4.7_0603_5%

ISL6269CRZ-T_QFN16

PR119
2

1
1

PR118
49.9K_0402_1%

22P_0402_50V8J

PC85

0.1U_0402_16V7K

PC84
0.01U_0402_25V7Z

57.6K_0402_1%
PC86
6800P_0402_25V7K
PR120
1

2.26K_0402_1%
PR121
3K_0402_1%

+1.8V
B

+3VS

2
2

PU9

2
3

VOUT

FB

VIN

NC

VREF

NC

VOUT

NC

TP

PR122
1K_0402_1%

+2.5VSP

+0.9VSP

PR126

1
PC95

PQ31

1
PC97
@0.1U_0402_16V7K

2
G

0_0402_5%
1
2

SUSP

PC92
@ 150U_D_6.3VM

0.01U_0402_25V7Z
PR127
1K_0402_1%

PR125

PC96
10U_1206_6.3V7K

1
2

2
APL5912-KAC-TRL_SO8~N

+
2

PC89
1U_0603_6.3V6M

APL5331KAC-TRL_SO8

1
22U_1206_6.3V6M

PC93

PC91
2

PR124
2.15K_0402_1%

PU10

GND

EN

+3VALWP

1
2

PC88
10U_1206_6.3V7K

PC90
22U_1206_6.3V6M

VCNTL

GND

2N7002-7-F_SOT23-3 1K_0402_1% 0.1U_0402_16V7K


A

VOUT

PC94
@ 0.1U_0402_16V7K

0_0402_5%
1
2
1

SUSP#

VIN

VIN

PR123

6
POK

VCNTL

1U_0603_6.3V6M

PJ10
@ JUMP_43X118

PC87

PJ11
JUMP_43X79
@

+5VS

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/06/23

2006/06/23

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

SCHEMATIC, M/B LA-3011


Size Document Number
Custom
401395
Date:

Rev
A

@, 01, 2005

Sheet
1

45

of

48

+5VS

CPU_VID0

PVCC

31

1
PC119
1
2

PR152 1_0603_5%
PC120
1U_0603_6.3V6M

1
2

PC111
10U_1206_6.3V7K

PR151 @ 0_0603_5%
1
2

0.22U_0603_10V7K
ISEN2

+VCC_CORE

PC123 10_0603_5%

2
PC124 0.018U_0603_50V7K
1
2

VCC_PRM
PC129
0.22U_0603_10V7K

PR161

PC130 0.33U_0603_10V7K
2
1

PR166 5.62K_0402_1%
PC128 33N_0603_50V8J
1
2

10K_0603_1%_TH11-4H104FT

PH4

PR165 1K_0402_1%

PR164

20_0402_5%

1
2
PR162 0_0402_5%
PC127 180P_0402_50V8J
1
2

PR163

11K_0402_1%

PR160 20_0402_5%

2.61K_0402_1%

VSUM
PC126
0.018U_0603_50V7K

PC125
@0.018U_0603_50V7K

0_0402_5%

0.01U_0402_25V7Z

VSSSENSE

1_0402_5%

VSUM

IRF8113PBF_SO8

PR150

VCC_PRM

PR159

PC117
680P_0603_50V8J

PR157

PR158 1.82K_0402_1%

+5VS

3
2
1

@ 0_0402_5%

PQ36
4

ISEN1
ISEN2
2

PR154
@ 0_0402_5%
PR155

1
PR137

PQ37
PR146
IRF8113PBF_SO8
@ 4.7_1206_5%

PL13

PR148
10K_0402_1%
2
1

ISEN1

0.22U_0603_10V7K

PU11

24

ISEN2
23

22

VDD

GND
21

VIN
20

VSUM
19

VO
18

DFB

DROOP

0_0603_5%

25

3.65K_0402_1%

NC

FB2

PR149

12

P_0.36H_ETQP4LR36WFC_24A_20%

UGATE_CPU2
PR145
PC114
BOOT_CPU2
1
2
1
2

26

PR138
2
PC110
10U_1206_6.3V7K
2
1

27

BOOT2

UGATE2

FB

1 2

COMP

11

PC122 470P_0402_50V7K
1
2

PR1561

PC101
10U_1206_6.3V7K
2
1

PC100
10U_1206_6.3V7K
2
1

5
3
2
1
5

10

PHASE_CPU2

+CPU_B+

3
2
1

28

PQ35
SI7840DP_SO8

5
6
7
8

PHASE2

ISL6262CRZ-T_QFN48

IRF8113PBF_SO8

LGATE_CPU2

+VCC_CORE

PR140
1_0402_5%

PR141 @ 0_0603_5%
1
2
PC109
1
2
VCC_PRM
ISEN1
0.22U_0603_10V7K

VSUM

3
2
1

VW

390P_0402_50V7K

3.4K_0402_1%
1
2

5
6
7
8

IRF8113PBF_SO8

PL12

LGATE_CPU1

5
6
7
8

30

PR139
10K_0402_1%
2
1

32

3.65K_0402_1%

LGATE1

29

PR153 61.9K_0402_1% PC118 1500P_0402_50V7K


1
2
2
1

B+

P_0.36H_ETQP4LR36WFC_24A_20%
2
1

4.7_1206_5%
680P_0603_50V8J

PHASE_CPU1

33

1 2

34

PGND1

PC108

PHASE1

UGATE_CPU1

3
2
1

35

PC116 5600P_0402_25V7K

PC99
10U_1206_6.3V7K

UGATE1

3
2
1

36

PGND2

13

+CPU_CORE
1

PQ34

BOOT1

LGATE2

17

1
2
1000P_0402_50V7K PC115
PR147 3.57K_0402_1%
1
2

VCCSENSE

PQ33

VID0

VID1

OCSET

VID2

SOFT

VID3

VID4

NTC

VID5

VID6

VR_TT#

VR_ON

DPRSLPVR

RBIAS

DPRSTP#

PGD_IN

RTN

@ 470K_0603_1%_TH11-4H104FT
1
2
PC112
0.015U_0603_25V7K PC113
1
2

PC105
1U_0603_6.3V6M

0.01U_0402_25V7Z

37

38

39

40

41

42

43

45

44

46

48
3

CLK_EN#

3V3

PC121

5
6
7
8

2
PSI#

16

2 1

PR144 13K_0402_1%
1
2

15

@ 0.015U_0402_16V7K

PH3

PGOOD

VSEN

VR_TT#
@ 4.22K_0402_1%
1

VDIFF

PR143

PR142 147K_0402_1%
1
2

FBMA-L18-453215-900LMA90T_1812
PC98
220U_25V_M

PQ32
SI7840DP_SO8

PC107
2 1
2

0_0603_5% 0.22U_0603_10V7K

14

PGD_IN

PC104
2
1

PC103
1U_0603_6.3V6M
2
1

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

PR134

2
H_PSI#

BOOT_CPU1

1
VGATE

PL11

1
1

PR132

0_0402_5%
2

PC106
1U_0603_16V6M

1
499_0402_1%

1.91K_0402_1%

PR135

PR136

0_0402_5%
2

47

PR133
1

+3VS

0_0402_5%
2

PR131
1

CLK_EN#

+3VS

0_0402_5%
1
2

PR130
1

H_DPRSTP#

PC102
0.01U_0402_25V7Z
2
1

DPRSLPVR

+CPU_B+

PR128
1_0603_5%

0_0402_5%

PR129

CPU_VID6

VR_ON

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2005/06/23

Issued Date

Deciphered Date

2006/06/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SCHEMATIC, M/B LA-3011


Size Document Number
Custom
401395
Date:

@, 01, 2005

Rev
A
Sheet
1

46

of

48

NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-3011

Size

Document Number

Rev
A

401395
Date:

, 01, 2005

Sheet

47

of

48

U6

945GM
GM@

U41

U41

82573E
82573E@

82562
82562@

ZZZ

PCB ZKU LA-3011 REV0

U13

PCI8412
PCI8412@

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF
Size
R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5

SCHEMATIC, M/B LA-3011


Document Number

Rev
A

401395
, 01, 2005

Sheet
1

48

of

48