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ADF4350
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
10-BIT R
COUNTER
2
DOUBLER
VP
RSET
VVCO
MULTIPLEXER
2
DIVIDER
MUXOUT
LOCK
DETECT
SW
FLO SWITCH
LD
CLK
DATA
LE
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
INTEGER
REG
FRACTION
REG
VTUNE
VREF
VCOM
VCO
CORE
MODULUS
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
TEMP
MULTIPLEXER
N COUNTER
MULTIPLEXER
CE
AGND
OUTPUT
STAGE
1/2/4/8/16
DGND
CPGND
SDGND
RFOUTA
PDBRF
OUTPUT
STAGE
ADF4350
AGNDVCO
RFOUTA+
RFOUTB+
RFOUTB
07325-001
REFIN
DVDD
AVDD
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADF4350
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 1 ..................................................................................... 18
Applications....................................................................................... 1
Register 2 ..................................................................................... 18
Register 3 ..................................................................................... 20
Register 4 ..................................................................................... 20
Register 5 ..................................................................................... 20
Specifications..................................................................................... 3
Modulus....................................................................................... 21
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Circuit Description......................................................................... 11
RF N Divider ............................................................................... 11
R Counter .................................................................................... 11
Phase Resync............................................................................... 24
Interfacing ................................................................................... 26
VCO.............................................................................................. 12
Output Stage................................................................................ 13
Register 0 ..................................................................................... 18
REVISION HISTORY
4/11Rev. 0 to Rev. A
Changes to Typical rms Jitter in Features Section........................ 1
Changes to Specifications ................................................................ 3
Changes Output Stage Section...................................................... 13
Changes to Figure 29...................................................................... 17
Changes to Fast LockAn Example Section.............................. 22
Changes to Direct Conversion Modulator Section and
Figure 34 ......................................................................................... 25
Changes to ADuC70xx Interface Section and ADSP-BF527
Interface Section ............................................................................. 26
Changes to Output Matching Section and Table 7..................... 27
Added Table 8.................................................................................. 28
Changes to Ordering Guide .......................................................... 29
11/08Revision 0: Initial Version
Rev. A | Page 2 of 32
ADF4350
SPECIFICATIONS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating
temperature range is 40C to +85C.
Table 1.
Parameter
REFIN CHARACTERISTICS
Input Frequency
Input Sensitivity
Input Capacitance
Input Current
PHASE DETECTOR
Phase Detector Frequency 2
CHARGE PUMP
ICP Sink/Source 3
High Value
Low Value
RSET Range
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
DVDD, VVCO, SDVDD, VP
DIDD + AIDD 4
Output Dividers
IVCO4
IRFOUT4
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
Maximum VCO Output Frequency
Minimum VCO Output Frequency
Minimum VCO Output Frequency
Using Dividers
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Harmonic Content (Second)
Harmonic Content (Third)
Minimum RF Output Power 5
Maximum RF Output Power5
Output Power Variation
Minimum VCO Tuning Voltage
Maximum VCO Tuning Voltage
Min
B Version
Typ
10
0.7
Max
Unit
Conditions/Comments
250
AVDD
60
MHz
V p-p
pF
A
32
MHz
10
10
2
1.5
2
1.5
0.6
1
3.0
DVDD 0.4
3.0
AVDD
21
6 to 24
70
21
7
33
1
90
19
13
20
10
4
5
1
0.5
2.5
V
V
A
pF
500
0.4
V
A
V
3.6
27
mA
mA
mA
mA
A
80
26
1000
4400
2200
137.5
mA
mA
k
%
%
%
MHz
MHz
MHz
MHz/V
MHz/V
kHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
V
V
Rev. A | Page 3 of 32
ADF4350
Parameter
NOISE CHARACTERISTICS
VCO Phase-Noise Performance 6
Min
B Version
Typ
Unit
Conditions/Comments
89
114
134
148
86
111
134
145
83
110
132
145
220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
111
97
0.5
70
40
dBc/Hz
dBc/Hz
ps
dBc
dBm
Max
Rev. A | Page 4 of 32
ADF4350
TIMING CHARACTERISTICS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t4
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
07325-002
t6
LE
Rev. A | Page 5 of 32
ADF4350
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VVCO to GND
VVCO to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
LFCSP JA Thermal Impedance
(Paddle-Soldered)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
1
Rating
0.3 V to +3.9 V
0.3 V to +0.3 V
0.3 V to +3.9 V
0.3 V to +0.3 V
0.3 V to VDD + 0.3 V
0.3 V to VDD + 0.3 V
0.3 V to VDD + 0.3 V
40C to +85C
65C to +125C
150C
27.3C/W
TRANSISTOR COUNT
24202 (CMOS) and 918 (bipolar)
ESD CAUTION
260C
40 sec
Rev. A | Page 6 of 32
ADF4350
32
31
30
29
28
27
26
25
SDVDD
SDGND
MUXOUT
REFIN
DVDD
DGND
PDBRF
LD
3
4
5
PIN 1
INDICATOR
ADF4350
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
AGND 9
AVDD 10
AGNDVCO 11
VREF
VCOM
RSET
AGNDVCO
VTUNE
TEMP
AGNDVCO
VVCO
07325-003
1
2
RFOUTA+ 12
RFOUTA 13
RFOUTB+ 14
RFOUTB 15
VVCO 16
CLK
DATA
LE
CE
SW
VP
CPOUT
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Mnemonic
CLK
DATA
LE
CE
5
6
SW
VP
CPOUT
8
9
10
CPGND
AGND
AVDD
11, 18, 21
12
13
AGNDVCO
RFOUTA+
RFOUTA
14
RFOUTB+
15
RFOUTB
16, 17
VVCO
19
TEMP
20
VTUNE
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device depending on the status of the power-down bits.
Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.
Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to
be placed as close as possible to this pin.
Charge Pump Output. When enabled, this provides ICP to the external loop filter. The output of the loop filter is
connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This is the ground return pin for CPOUT.
Analog Ground. This is a ground return pin for AVDD.
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are
to be placed as close as possible to this pin. AVDD must have the same value as DVDD.
VCO Analog Ground. These are the ground return pins for the VCO.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to these pins. VVCO must have the same value as AVDD.
Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as
possible to this pin.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
Rev. A | Page 7 of 32
ADF4350
Pin No.
22
Mnemonic
RSET
Description
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is
I CP =
23
VCOM
24
25
26
27
28
VREF
LD
PDBRF
DGND
DVDD
29
REFIN
30
MUXOUT
31
32
SDGND
SDVDD
33
EP
25.5
R SET
where:
RSET = 5.1 k
ICP = 5 mA
Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.
Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
Digital Ground. Ground return path for DVDD.
Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 k. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Sigma-Delta (-) Modulator Ground. Ground return path for the - modulator.
Power Supply Pin for the Digital - Modulator. Should be the same voltage as AVDD. Decoupling capacitors to
the ground plane are to be placed as close as possible to this pin.
Exposed Pad.
Rev. A | Page 8 of 32
ADF4350
TYPICAL PERFORMANCE CHARACTERISTICS
40
70
50
80
90
70
80
90
100
110
120
130
130
140
1M
10M
100M
170
1k
1M
10M
100M
40
70
50
80
60
FUND
DIV2
DIV4
DIV8
DIV16
90
PHASE NOISE (dBc/Hz)
70
80
90
100
110
120
130
100
110
120
130
140
150
140
100k
1M
10M
100M
FREQUENCY (Hz)
170
07325-029
10k
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
07325-032
160
150
40
70
50
80
60
FUND
DIV2
DIV4
DIV8
DIV16
90
PHASE NOISE (dBc/Hz)
70
80
90
100
110
120
130
100
110
120
130
140
150
140
160
10k
100k
1M
10M
FREQUENCY (Hz)
100M
07325-030
150
160
1k
100k
FREQUENCY (Hz)
160
1k
10k
07325-031
100k
07325-028
10k
FREQUENCY (Hz)
120
160
150
110
150
140
160
1k
100
170
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
07325-033
60
FUND
DIV2
DIV4
DIV8
DIV16
Rev. A | Page 9 of 32
20
20
40
40
60
80
100
120
10k
100k
FREQUENCY (Hz)
1M
10M
120
160
07325-034
1k
Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band,
RFOUT = 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4
Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz.
1k
20
20
40
40
60
80
100
120
10k
100k
FREQUENCY (Hz)
1M
10M
60
80
100
120
140
140
1k
10k
100k
FREQUENCY (Hz)
1M
10M
160
07325-035
160
Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band,
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz.
1k
3.02
20
3.01
FREQUENCY (GHz)
40
80
100
100k
FREQUENCY (Hz)
1M
10M
60
10k
07325-038
100
140
160
80
07325-037
140
60
120
CSR OFF
CSR ON
3.00
2.99
2.98
2.97
2.96
140
1k
10k
100k
FREQUENCY (Hz)
1M
10M
2.95
07325-036
160
Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz
100
200
300
TIME (s)
400
500
600
07325-039
ADF4350
Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with
CSR On and Of f, PFD = 25 MHz, ICP = 313 A, Loop Filter Bandwidth = 20 kHz
Rev. A | Page 10 of 32
ADF4350
CIRCUIT DESCRIPTION
RF N DIVIDER
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
FRAC
VALUE
07325-006
MOD
REG
100k
SW2
TO R COUNTER
BUFFER
SW3
NO
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by INT, FRAC and MOD
values, which build up this divider.
(1)
(2)
R COUNTER
The 10bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
D1
Q1
UP
U1
+IN
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
CLR1
DELAY
HIGH
U3
CHARGE
PUMP
CLR2
DOWN
D2
Q2
U2
IN
Rev. A | Page 11 of 32
CP
07325-007
SW1
07325-005
REFIN NC
TO PFD
N COUNTER
POWER-DOWN
CONTROL
NC
N = INT + FRAC/MOD
ADF4350
(R0) must be written to, to ensure the modulus value is loaded
correctly. Divider select in Register 4 (R4) is also double buffered, but only if DB13 of Register 2 (R2) is high.
VCO
The VCO core in the ADF4350 consists of three separate VCOs
each of which uses 16 overlapping bands, as shown in Figure 20,
to allow a wide frequency range to be covered without a large
VCO sensitivity (KV) and resultant poor phase noise and spurious performance.
DVDD
THREE-STATE OUTPUT
DVDD
DGND
R COUNTER OUTPUT
MUX
CONTROL
MUXOUT
N COUNTER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
VCO and band selection take 10 PFD cycles band select clock
divider value. The VCO VTUNE is disconnected from the output
of the loop filter and is connected to an internal reference voltage.
2.8
RESERVED
2.4
DGND
2.0
Control Bits
C2
0
0
1
1
0
0
C1
0
1
0
1
0
1
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
PROGRAM MODES
Table 5 and Figure 23 through Figure 29 show how the program
modes are to be set up in the ADF4350.
1.2
0.8
FREQUENCY (MHz)
4600
4400
4200
4000
3800
3600
3400
3200
3000
2800
2600
2400
2200
07325-009
0.4
2000
1.6
1800
VTUNE (V)
The R counter output is used as the clock for the band select
logic. A programmable divider is provided at the R counter
output to allow division by 1 to 255 and is controlled by
Bits [BS8:BS1] in Register 4 (R4). When the required PFD
frequency is higher than 125 kHz, the divide ratio should be
set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal
value of KV is 33 MHz/V when the N-divider is driven from the
VCO output or this value divided by D. D is the output divider
value if the N-divider is driven from the RF divider output
(chosen by programming Bits [D12:D10] in Register 4 (R4).
The ADF4350 contains linearization circuitry to minimize
any variation of the product of ICP and KV to keep the loop
bandwidth constant.
ADF4350
The VCO shows variation of KV as the VTUNE varies within the
band and from band-to-band. It has been shown for wideband
applications covering a wide frequency range (and changing
output dividers) that a value of 33 MHz/V provides the most
accurate KV as this is closest to an average value. Figure 21
shows how KV varies with fundamental VCO frequency along
with an average value for the frequency band. Users may prefer
this figure when using narrowband designs.
80
60
50
40
30
20
07325-133
10
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6
FREQUENCY (GHz)
Rev. A | Page 13 of 32
RFOUTA+
VCO
RFOUTA
BUFFER/
DIVIDE-BY1/2/4/8/16
07325-010
70
OUTPUT STAGE
ADF4350
REGISTER MAPS
RESERVED
REGISTER 0
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
DB2
DB1
DB0
PRESCALER
REGISTER 1
RESERVED
DBR1
CONTROL
BITS
DBR 1
PR1
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
M12
M11
M10
M9
M8
M7
M6
M5
M4
DB2
DB1
DB0
M3
M2
M1
COUNTER
RESET
CP THREESTATE
PD
LDP
PD
POLARITY
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
CONTROL
BITS
DBR 1
CHARGE
PUMP
CURRENT
SETTING
LDF
DBR 1
10-BIT R COUNTER
DOUBLE BUFF
MUXOUT
RDIV2
LOW
NOISE AND
LOW SPUR
MODES
REFERENCE
DOUBLER DBR 1
RESERVED
REGISTER 2
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
L2
L1
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3
CP2
CP1
U6
U5
U4
U3
U2
U1
DB2
DB1
DB0
RESERVED
CSR
RESERVED
RESERVED
REGISTER 3
CLK
DIV
MODE
CONTROL
BITS
F1
C2
C1
D12
D11
D10
D9
D8
D7
D6
AUX OUTPUT
ENABLE
MTLD
AUX OUTPUT
SELECT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
D5
D4
D3
D2
D1
DB2
DB1
DB0
DBB 2
DIVIDER
SELECT
AUX
OUTPUT
POWER
RF OUTPUT
ENABLE
RESERVED
VCO POWER
DOWN
FEEDBACK
SELECT
REGISTER 4
OUTPUT
POWER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
D13
D12
D11
D10
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
D9
D8
D7
D6
D5
D4
D3
D2
D1
CONTROL
BITS
DB2
DB1
DB0
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1 DBR
2 DBB
D15
D14
Rev. A | Page 14 of 32
DB2
DB1
DB0
LD PIN
MODE
RESERVED
RESERVED
REGISTER 5
RESERVED
ADF4350
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
F5
F4
DB5 DB4
F3
F2
DB3
F1
DB2
DB1
DB0
N16
N15
...
N5
N4
N3
N2
N1
F12
F11
..........
F2
F1
...
NOT ALLOWED
..........
...
NOT ALLOWED
..........
...
NOT ALLOWED
..........
...
...
..........
...
NOT ALLOWED
..........
...
23
..........
...
24
..........
...
...
..........
4092
...
65533
..........
4093
...
65534
..........
4094
...
65535
.........
4095
07325-012
CONTROL
BITS
PRESCALER
RESERVED
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
PR1
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
M12
M11
M10
M9
M8
M7
M6
DB7 DB6
M5
M4
P1
PRESCALER
P12
P11
..........
P2
P1
M12
M11
..........
M2
M1
4/5
..........
..........
8/9
..........
1 (RECOMMENDED)
..........
..........
..........
..........
..........
..........
..........
4092
..........
..........
..........
4093
..........
..........
4094
..........
4092
..........
4095
..........
4093
..........
4094
..........
4095
DB5 DB4
M3
M2
DB3
M1
DB2
DB1
DB0
07325-013
CONTROL
BITS
DBR
Rev. A | Page 15 of 32
COUNTER
RESET
CP THREESTATE
POWER-DOWN
PD
POLARITY
DBR
LDF
10-BIT R COUNTER
CHARGE
PUMP
CURRENT
SETTING
LDP
DBR
DOUBLE BUFF
MUXOUT
RDIV2
LOW
NOISE AND
LOW SPUR
MODES
REFERENCE
DOUBLER DBR
RESERVED
ADF4350
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
L2
L1
M3
M2
M1
RD2
RD1
R10
L1
L2
NOISE MODE
RD2
REFERENCE
DOUBLER
DISABLED
RESERVED
ENABLED
RESERVED
RD1
R8
R7
..........
..........
..........
..........
..........
1020
..........
1021
..........
1022
..........
1023
DVDD
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
RESERVED
R DIVIDER (R)
U2
U1
DISABLED
INT-N
ENABLED
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
U3
COUNTER
RESET
DISABLED
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
U4
U1
ENABLED
CP1
U5
FRAC-N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
U6
DB0
LDF
CP2
CP1
DB1
U6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DOUBLEBUFFER
R4 DB22-20
CP3
CP2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CP3
CP4
R1
OUTPUT
CP4
DISABLED
THREE-STATE OUTPUT
D1
ENABLED
R2
M1
R1
..........
R2
..........
M2
R3
ICP (mA)
5.1k
R4
REFERENCE DIVIDE BY 2
R9
R5
D1
M3
R6
DB2
CP
THREE-STATE
U5
LDP
U2
10ns
DISABLED
6ns
ENABLED
U4
PD POLARITY
U3
POWER DOWN
NEGATIVE
DISABLED
POSITIVE
ENABLED
07325-014
R10
R9
CONTROL
BITS
CLK
DIV
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
F1
C2
C1
CONTROL
BITS
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
DB3
D1
F1
CYCLE SLIP
REDUCTION
D12
D11
..........
D2
D1
..........
DISABLED
..........
ENABLED
..........
..........
..........
..........
..........
C2
C1
..........
4092
FAST-LOCK ENABLE
..........
4093
RESYNC ENABLE
..........
4094
RESERVED
..........
4095
Rev. A | Page 16 of 32
DB2
DB1
DB0
07325-015
CSR
RESERVED
RESERVED
RESERVED
AUX
OUTPUT
POWER
RF OUTPUT
ENABLE
AUX OUTPUT
ENABLE
AUX OUTPUT
SELECT
DIVIDER
SELECT DBB
MTLD
RESERVED
VCO POWERDOWN
FEEDBACK
SELECT
ADF4350
CONTROL
BITS
OUTPUT
POWER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
D13
D12
D11
D10
BS8
BS7
BS6
BS5
BS4
FEEDBACK
D13 SELECT
0
1
D12
D11
D10
16
D9
D8
D6
D5
D4
D3
D2
D1
DB2
DB1
DB0
D2
D1
OUTPUT POWER
-4
-1
+2
+5
D8
MUTE TILL
LOCK DETECT
MUTE DISABLED
D3
MUTE ENABLED
DISABLED
ENABLED
AUX OUTPUT
SELECT
DIVIDED OUTPUT
FUNDAMENTAL
RF OUT
D5
D4
-4
-1
AUX OUT
+2
DISABLED
+5
ENABLED
..........
BS2
BS1
..........
..........
D6
..........
..........
..........
..........
252
..........
253
..........
254
..........
255
07325-016
D7
BS7
BS8
D7
VCO POWERED UP
BS1
RF DIVIDER SELECT
BS2
VCO
POWER-DOWN
D9
DIVIDED
FUNDAMENTAL
BS3
LD PIN
MODE
RESERVED
RESERVED
RESERVED
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
D15
D14
D1 5
D1 4
LOW
LOW
HIGH
DB2
DB1
DB0
07325-017
DB3
Rev. A | Page 17 of 32
ADF4350
If neither the phase resync nor the spurious optimization
functions are being used, it is recommended the PHASE
word be set to 1.
REGISTER 0
Control Bits
With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.
Figure 24 shows the input data format for programming this
register.
REGISTER 1
Control Bits
With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed.
Figure 25 shows the input data format for programming
this register.
Prescaler Value
The dual modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the VCO output to the PFD input.
REGISTER 2
Control Bits
With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed.
Figure 26 shows the input data format for programming this
register.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4350 above 3 GHz, this must be set to 8/9. The prescaler
limits the INT value, where P is 4/5, NMIN is 23 and P is 8/9,
NMIN is 75.
For best noise performance, use the lowest noise setting option.
As well as disabling the dither, this setting also ensures that the
charge pump is operating in an optimum region for noise
performance. This setting is extremely useful where a narrow
loop filter bandwidth is available. The synthesizer ensures
extremely low noise and the filter attenuates the spurs. The
typical performance characteristics give the user an idea of
the trade-off in a typical W-CDMA setup for the different
noise and spur settings.
MUXOUT
These bits control what is loaded as the phase word. The word
must be less than the MOD value programmed in Register 1.
The word is used to program the RF output phase from 0 to
360 with a resolution of 360/MOD. See the Phase Resync
section for more information. In most applications, the phase
relationship between the RF signal and the reference is not
important. In such applications, the phase value can be used
to optimize the fractional and subfractional spur levels. See the
Spur Consistency and Fractional Spur Optimization section for
more information.
Reference Doubler
Setting DB25 to 0 feeds the REFIN signal directly to the 10bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding into the
10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
Rev. A | Page 18 of 32
ADF4350
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to
the REFIN duty cycle. The phase noise degradation can be as
much as 5 dB for the REFIN duty cycles outside a 45% to 55%
range. The phase noise is insensitive to the REFIN duty cycle
in the lowest noise mode and when the doubler is disabled.
The maximum allowable REFIN frequency when the doubler
is enabled is 30 MHz.
RDIV2
10Bit R Counter
Power-Down
Double Buffer
DB13 enables or disables double buffering of Bits [DB22:DB20]
in Register 4. The Divider Select section explains how double
buffering works.
DB6 sets the phase detector polarity. When a passive loop filter,
or noninverting active loop filter is used, this should be set to 1.
If an active filter with an inverting characteristic is used, it
should be set to 0.
LDF
Setting DB8 to 1 enables integerN digital lock detect,
when the FRAC part of the divider is 0; setting DB8 to 0
enables fractionalN digital lock detect.
Counter Reset
DB3 is the R counter and N counter reset bit for the ADF4350.
When this is 1, the RF synthesizer N counter and R counter are
held in reset. For normal operation, this bit should be set to 0.
Rev. A | Page 19 of 32
ADF4350
REGISTER 3
Control Bits
CSR Enable
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge pump current setting must also
be set to a minimum. See the Cycle Slip Reduction for Faster
Lock Times section for more information.
VCO Power-Down
DB11 powers the VCO down or up depending on the chosen value.
REGISTER 4
RF Output Enable
Control Bits
Output Power
Bits [DB4:DB3] set the value of the primary RF output power
level (see Figure 28).
Feedback Select
DB23 selects the feedback from the VCO output to the
N counter. When set to 1, the signal is taken from the VCO
directly. When set to 0, it is taken from the output of the output
dividers. The dividers enable covering of the wide frequency band
(137.5 MHz to 4.4 GHz). When the divider is enabled and the
feedback signal is taken from the output, the RF output signals
of two separately configured PLLs are in phase. This is useful in
some applications where the positive interference of signals is
required to increase the power.
REGISTER 5
Control Bits
With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.
Figure 29 shows the input data form for programming this
register.
Divider Select
Bits [DB22:DB20] select the value of the output divider (see
Figure 28).
Rev. A | Page 20 of 32
ADF4350
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power-up of the ADF4350 after the correct application of
voltages to the supply pins:
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF divider is the output divider that divides down the VCO
frequency.
(4)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
T is the reference divide-by-2 bit (0 or 1).
R is the RF reference division factor.
For example, in a UMTS system, where 2112.6 MHz RF
frequency output (RFOUT) is required, a 10 MHz reference
frequency input (REFIN) is available, and a 200 kHz channel
resolution (fRESOUT) is required on the RF output. Note that
the ADF4350 operates in the frequency range of 2.2 GHz to
4.4 GHz. Therefore, the RF divider of 2 should be used (VCO
frequency = 4225.2 MHz, RFOUT = VCO frequency/RF divider =
4225.2 MHz/2 = 2112.6 MHz).
It is also important where the loop is closed. In this example,
the loop is closed (see Figure 30).
RFOUT
N
DIVIDER
07325-027
(6)
VCO
MODULUS
PFD
(5)
where:
INT = 422
FRAC = 13
fPFD
Rev. A | Page 21 of 32
ADF4350
The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is a
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly to the PFD, and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz).
The modulus needs to be reprogrammed to 65 for GSM 1800
operation (13 MHz/65 = 200 kHz).
As outlined in the Low Noise and Low Spur Mode section, the
ADF4350 contains a number of features that allow optimization
for noise performance. However, in fast locking applications,
the loop bandwidth generally needs to be wide, and therefore,
the filter does not provide much attenuation of the spurs. If
the cycle slip reduction feature is enabled, the narrow loop
bandwidth is maintained for spur attenuation but faster lock
times are still possible.
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared to the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically.
The ADF4350 contains a cycle slip reduction feature that extends
the linear range of the PFD, allowing faster lock times without
modifications to the loop filter circuitry.
When the circuitry detects that a cycle slip is about to occur,
it turns on an extra charge pump current cell. This outputs a
constant current to the loop filter, or removes a constant
current from the loop filter (depending on whether the VCO
tuning voltage needs to increase or decrease to acquire the new
frequency). The effect is that the linear range of the PFD is
increased. Loop stability is maintained because the current
is constant and is not a pulsed current.
If the phase error increases again to a point where another cycle
slip is likely, the ADF4350 turns on another charge pump cell.
This continues until the ADF4350 detects the VCO frequency
has gone past the desired frequency. The extra charge pump
cells are turned off one by one until all the extra charge pump
cells have been disabled and the frequency is settled with the
original loop filter bandwidth.
Rev. A | Page 22 of 32
ADF4350
FAST LOCKLOOP FILTER TOPOLOGY
To use fast-lock mode, the damping resistor in the loop filter
is reduced to of its value while in wide bandwidth mode. To
achieve the wider loop filter bandwidth, the charge pump
current increases by a factor of 16 and to maintain loop stability the damping resistor must be reduced a factor of .
To enable fast lock, the SW pin is shorted to the GND pin by
settings Bits [DB16:DB15] in Register 3 to 0, 1. The following
two topologies are available:
R2
CP
C1
C2
VCO
C3
R1
Repeat
Length
2 MOD
3 MOD
6 MOD
MOD
Spur Interval
Channel step/2
Channel step/3
Channel step/6
Channel step
In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes
the quantization error spectrum look like broadband noise.
This may degrade the in-band phase noise at the PLL output
by as much as 10 dB. For lowest noise, dither disabled is a better
choice, particularly when the final loop bandwidth is low
enough to attenuate even the lowest frequency fractional spur.
SW
Another mechanism for fractional spur creation is the interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
point of a fractional-N synthesizer) spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth, therefore, the name integer boundary spurs.
07325-018
R1A
ADF4350
R2
CP
C1
C2
R1A
R1
VCO
C3
SW
07325-019
Reference Spurs
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4350.
Fractional Spurs
The fractional interpolator in the ADF4350 is a third-order
- modulator (SDM) with a modulus (MOD) that is programmable to any integer value from 2 to 4095. In low spur mode
(dither enabled) the minimum allowable value of MOD is 50.
The SDM is clocked at the PFD reference rate (fPFD) that allows
PLL output frequencies to be synthesized at a channel step
resolution of fPFD/MOD.
Rev. A | Page 23 of 32
ADF4350
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization noise of the SDM also depends on the particular phase
word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4350.
LE
SYNC
(INTERNAL)
FREQUENCY
PLL SETTLES TO
INCORRECT PHASE
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
PHASE
100
07325-020
PHASE RESYNC
tSYNC
100
200 300
700
800
900 1000
Phase Programmability
Rev. A | Page 24 of 32
ADF4350
APPLICATIONS INFORMATION
This gives better performance than a single-ended LO driver
and eliminates the use of a balun to convert from a single-ended
LO input to the more desirable differential LO input for the
ADL5375. At LO frequencies below 3 GHz some harmonic
filtering may be necessary to ensure best single sideband
performance.
51
REFIO
MODULATED
DIGITAL
DATA
51
IOUTA
LOW-PASS
FILTER
IOUTB
AD9761
TxDAC
QOUTA
LOW-PASS
FILTER
QOUTB
FSADJ
51
51
2k
VVCO
16
17
VVCO
LOCK
DETECT
VDD
28
10
DVDD AV DD
26
30
25
4
6
32
CE PDB RF VP SDVDD MUXOUT LD
29 REF IN
51
RFOUTB+ 14
VVCO
IBBN
RFOUTB 15
1 CLK
2 DATA
3.9nH
3.9nH
3 LE
1nF
ADF4350
22 RSET
LOIP
RFOUTA+ 12
LPF
RFOUTA 13
4.7k
1nF
LOIN
QUADRATURE
PHASE
SPLITTER
RFO
LPF
DSOP
VTUNE 20
680
CPOUT
QBBP
7
39nF
SW 5
CPGND SDGND AGND AGNDVCO
8
31
11
18
21
10pF
0.1F 10pF
2700pF
1200pF
QBBN
360
VREF
24
0.1F 10pF
0.1F
Rev. A | Page 25 of 32
07325-021
ADL5375
IBBP
1nF 1nF
FREF IN
ADF4350
INTERFACING
ADSP-BF527 Interface
MOSI
ADuC70xx
I/O PORTS
CLK
GPIO
LE
ADF4350
CE
MUXOUT
(LOCK DETECT)
LE
ADF4350
CE
I/O FLAGS
MUXOUT
(LOCK DETECT)
DATA
07325-022
SCLOCK
CLK
DATA
ADSP-BF527
SCK
MOSI
07325-023
ADuC70xx Interface
Rev. A | Page 26 of 32
ADF4350
OUTPUT MATCHING
VVCO
50
50
07325-021
100pF
RFOUT
L (nH)
100
47
7.5
3.9
C (nF)
1
1
1
1
07325-025
C
50
C2
50
L1
RFOUTA
C1
VVCO
RFOUT
C1
07325-132
RFOUTA+
L1
Inductor L1 (nH)
100
51
30
18
12
5.6
3.3
2.2
Capacitor C1 (pF)
10
5.6
5.6
4
2.2
1.2
0.7
0.5
RF Choke
Inductor (nH)
390
180
120
68
39
15
10
10
Rev. A | Page 27 of 32
DC Blocking
Capacitor (pF)
1000
120
120
120
10
10
10
10
Measured Output
Power (dBm)
9
10
10
10
9
9
8
8
ADF4350
Table 9. RFOUTA+ S-Parameters (S11)
# GHz S MA R 50
FREQ
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
MAG
0.96
0.94
0.93
0.92
0.92
0.92
0.91
0.91
0.91
0.9
0.9
0.89
0.89
0.89
0.89
0.89
0.88
0.88
0.87
0.86
0.86
0.86
0.85
0.85
0.85
0.84
0.83
0.82
0.81
0.81
0.8
0.8
0.79
0.78
0.75
0.74
0.74
0.74
0.74
0.73
0.72
0.71
0.69
0.67
ANG
3.65
4.41
4.52
4.41
4.82
5.25
5.74
6.3
7.32
8.22
9.4
10.61
10.96
11.68
12.3
12.84
13.55
14.13
14.84
15.76
16.63
17.51
18.43
19.38
20.4
21.61
22.63
22.92
23.82
24.82
25.58
26.71
28.05
29.63
30.12
29.82
30.3
31.36
32.63
33.78
35.08
36.83
37.98
38.42
# GHz S MA R 50
FREQ
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
3.80
3.85
3.90
3.95
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
Rev. A | Page 28 of 32
MAG
0.65
0.64
0.63
0.62
0.61
0.6
0.59
0.58
0.57
0.57
0.55
0.54
0.52
0.51
0.49
0.48
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.4
0.38
0.37
0.36
0.35
0.34
0.33
0.32
0.31
0.3
0.28
0.27
0.26
0.26
0.25
0.25
0.24
0.23
0.22
0.21
ANG
38.78
39.43
40.44
41.55
42.55
43.8
44.97
45.93
46.5
47.11
47.7
48.54
49.63
50.71
51.89
53.42
54.56
55.71
56.38
56.99
57.9
58.92
60.17
61.49
63.02
64.37
65.52
66.53
67.53
69.16
70.75
72.04
73.73
75.85
78.25
81.03
83.45
85.67
87.63
89.61
91.6
93.91
97.18
ADF4350
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12 MAX
17
16
0.80 MAX
0.65 TYP
0.30
0.23
0.18
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
011708-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
32
25
24
ORDERING GUIDE
Model 1
ADF4350BCPZ
ADF4350BCPZ-RL
ADF4350BCPZ-RL7
EVAL-ADF4350EB1Z
EVAL-ADF4350EB2Z
1
Temperature Range
40C to +85C
40C to +85C
40C to +85C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board, Primary RF Output Available
Evaluation Board, Primary and Auxiliary RF Outputs Available
Rev. A | Page 29 of 32
Package Option
CP-32-2
CP-32-2
CP-32-2
ADF4350
NOTES
Rev. A | Page 30 of 32
ADF4350
NOTES
Rev. A | Page 31 of 32
ADF4350
NOTES
Rev. A | Page 32 of 32