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COMPONENTS:

i.

2:1 MUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:45:04 04/05/2014
// Module Name: two_one_mux
//////////////////////////////////////////////////////////////////////////////////
module two_one_mux(a,b,s,y);
input a,b,s;
output y;
assign y = (~s & a) | (s & b) ;
endmodule

2:1 MUX RTL SCHEMATIC


ii.

4:1 MUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:47:32 04/05/2014
// Module Name: four_one_mux
//////////////////////////////////////////////////////////////////////////////////
module four_one_mux(a,b,c,d,s,y);

input a,b,c,d;
input [1:0]s;
output reg y;
always @(*)
begin
y = ((~s[1])&(~s[0])&a) | ((~s[1])&s[0]&b) | (s[1]&(~s[0])&c) |
(s[1]&s[0]&d) ;
end
endmodule

1:4 MUX RTL SCHEMATIC

iii.

2:1 DEMUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.

// Create Date: 15:32:19 04/06/2014


// Module Name: two_one_demux
//////////////////////////////////////////////////////////////////////////////////
module two_one_demux(in,s,y0,y1);
input in,s;
output reg y0,y1;
always @(*)
begin
y0 = 1'bx;
y1 = 1'bx;
case(s)
1'b0 : y0 = in;
1'b1 : y1 = in;
endcase
end
endmodule

1:2 DEMUX RTL SCHEMATIC


iv.

4:1 DEMUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 13:10:06 04/06/2014

// Module Name: four_one_demux


//////////////////////////////////////////////////////////////////////////////////
module four_one_demux(in,s,y0,y1,y2,y3);
input in;
input [1:0]s;
output reg y0,y1,y2,y3;
always @(*)
begin
y0 = 1'bx;
y1 = 1'bx;
y2 = 1'bx;
y3 = 1'bx;
case(s)
2'b00 : y0 =
2'b01 : y1 =
2'b10 : y2 =
2'b11 : y3 =
endcase
end

in;
in;
in;
in;

endmodule

1:4 DEMUX RTL SCHEMATIC

STAGE 1:
i.

ii.

INPUT AND OUTPUT LINES:

INTERNAL BLOCKS:

Stage 1 Verilog Code:


//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 14:59:19 04/08/2014
// Module Name: stage1_p
//////////////////////////////////////////////////////////////////////////////////
module stage1_p(clock,jmp_disp,op,inst_f,PC);
wire [7:0]wire_add1, wire_add2;
output [15:0]inst_f;
reg [7:0]PC_add;
input [2:0]jmp_disp;
input clock;
input [3:0]op;
output [7:0]PC;
wire en;
initial
begin
PC_add <= 8'b1111_1111; //initial value of PC
end
//-------combinational block for select line of mux-------//
and(en,PC_add[0],PC_add[1],PC_add[2],PC_add[3],PC_add[4],PC_a
dd[5],PC_add[6],PC_add[7]); //initially en will be 1
wire w1 = op[3]&op[2]&(~op[1])&(~op[0]);
jmp oc
wire w2 = ~w1;
wire w3;
assign w3 = w2 | en;

/// for
//mux select line

adder_IF_8 add1(PC_add,8'b0000_0001,wire_add1); //increment


PC by 1
adder_IF_8 add2(PC_add,{5'b00000,jmp_disp},wire_add2);
//increment
PC by jmp
//displacement
two_one_mux t1[7:0](wire_add2,wire_add1,w3,PC); //select
increment value
INSTRUCT_MEM fetch(PC,inst_f);

always @(posedge clock)


begin
PC_add <= PC;
end
endmodule

STAGE 1 RTL SCHEMATIC

a) INCREMENTER:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 00:48:03 04/06/2014
// Design Name:
// Module Name: adder_IF_8
//////////////////////////////////////////////////////////////////////////////////
module adder_IF_8(a,b,y);
input [7:0]a,b;
output [7:0]y;
assign

y = a+b;

endmodule

INCREMENTER

b) INSTRUCTION MEMORY:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 00:58:03 04/08/2014
// Module Name: INSTRUCT_MEM
//////////////////////////////////////////////////////////////////////////////////
module INSTRUCT_MEM(a,r);
input [7:0]a;
output [15:0]r;
output
reg [15:0]rom[19:0];
(2^8 * 16)

//Memory Address
//Memory data

//declaration of 256X16 memory

initial
begin
$readmemh("hazard.list.txt",rom);
//Read and copy hex code from text file to memory
end
assign r = rom[a];
memory
endmodule

//Read from

INSTRUCTION MEMORY
STAGE 2:
i.

INPUTS AND OUTPUT LINES:

ii.

Internal Blocks:
Stage 2 Verilog Code:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 12:33:30 04/06/2014
// Module Name: STAGE_2
//////////////////////////////////////////////////////////////////////////////////
module STAGE_2(clock, inst,
wD, aD, w_en, rT, rS,
regwren,memwren,sel,alu_ctrl,ctrl,edp,
shift,aMem,aDest,
jmp_disp,
MviData,
aS,aT
);
input clock;
input [15:0]inst;
via buffer
wire [8:0]inst_copy,mvi;
output [7:0]MviData;

//instruction fetched from stage 1

wire [3:0]oc;
wire [1:0]rb;
wire control;
output [1:0] regwren,sel;
output memwren;
output [3:0] alu_ctrl;
output ctrl;
output edp;
output reg[2:0] aS;
output reg[2:0] aT;
input [2:0] aD;
input [15:0] wD;
input [1:0] w_en;
output [15:0] rS;
output [15:0] rT;

//source 1
//source 2
//dest. register address
//data to be written
//active low write enable
//scr1 o/p
//scr2 o/p

output [2:0]shift, aMem;


output reg [2:0]aDest;
output [2:0]jmp_disp;
wire [2:0]source2;

assign
assign
assign
assign

oc = inst[15:12]; //opcode
rb = inst[10:9];
//reconfig bits
control = inst[11];
//control bit
jmp_disp = inst[2:0]; // jump displacement to stage 1

wire mvi_w =
alu_ctrl[3]&
alu_ctrl[2]&(
~alu_ctrl[1])
&alu_ctrl[0]
&ctrl; /*sele
ct
line to mvi mux*/
two_one_demux td [8:0](inst[8:0],mvi_w,inst_copy,mvi);
//to
select MVIdata
or //instruction
copy
assign MviData = mvi[7:0];
//to select 8 bit MVIdata
//---always block to select address of source 1---//
always @(*)
begin
aS = inst_copy[5:3] ;
case(oc)
4'b1011 :
begin
if(ctrl == 1'b0)
aS = 3'bxxx;
// load
end
4'b1100 : aS = 3'bxxx;
4'b1110 : aS = 3'bxxx;
4'b1111 : aS = 3'bxxx;
endcase
end

// jmp
// nop
// edp

wire demux1 = alu_ctrl[3]&(~alu_ctrl[2])&alu_ctrl[0]; ////to select


between mem
address/shift & other instructions
wire demux2 = alu_ctrl[1];
or shift
wire [2:0] w;

// to select between mem address

two_one_demux t1 [2:0] (inst_copy[2:0],demux1, source2, w);


two_one_demux t2 [2:0] (w,demux2, shift, aMem);

//---always block to select address of source 2---//


always @(*)
begin
aT = source2 ;
case(oc)
4'b0010 : aT = 3'bxxx;
4'b0011 : aT = 3'bxxx;
4'b0111 : aT = 3'bxxx;
4'b1101 : aT = 3'bxxx;

// incr
// decr
// rep and not
// mov

4'b1100 : aT = 3'bxxx; // jmp


4'b1110 : aT = 3'bxxx; // nop
4'b1111 : aT = 3'bxxx; // edp
endcase
end
reg_file call_reg (aS,aT,clock,aD,wD,rS,rT,w_en);
register file

//call to

ctrl_unit
call_control(oc,control,rb,regwren,memwren,alu_ctrl,ctrl,edp,sel);
//call to control unit
//---always block for destination address---//
always @(*)
begin
aDest = inst_copy[8:6];
case(oc)
4'b1101 :
begin
if(ctrl)
aDest = 3'b000;
end
4'b1011 :
begin

// mvi

if(ctrl)

// store
aDest = 3'bxxx;

end
4'b1100 : aDest = 3'bxxx;
4'b1110 : aDest = 3'bxxx;
4'b1111 : aDest = 3'bxxx;
endcase
end
endmodule

CONTROL
UNIT
REGISTER

// jmp
// nop
// edp

STAGE 2 RTL SCHEMATIC

a) REGISTER FILE:
/////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 22:11:31 04/05/2014
// Module Name: reg_file
//////////////////////////////////////////////////////////////////////////////////
module reg_file(aS,aT,clk,aD,wD,rS,rT,w_en);
input clk;
//input [1:0] rb;
//active low reconfigurable bits
input [2:0] aS;
//source 1
input [2:0] aT;
//source 2
input [2:0] aD;
//dest. register
input [15:0] wD;
//data to be written
input [1:0] w_en;
//active low write enable
output reg [15:0] rS;
//scr1 o/p
output reg [15:0] rT;
//scr2 o/p
reg [15:0]gpr[7:0];
always@(negedge clk)
begin
rS<=gpr[aS];
rT<=gpr[aT];
end
always@(posedge clk)
begin
if(w_en == 2'b00)
gpr[aD] <= wD;

//read the data


//at negative edge

//write at positive
//edge
//16 bit write

else if(w_en == 2'b10)


gpr[aD][7:0] <= wD[7:0]; //lower byte write
else if(w_en == 2'b01)
gpr[aD][15:8] <= wD[15:8];
//higher byte write
end
endmodule

b) Control Unit:

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 01:47:50 04/06/2014
// Module Name: ctrl_unit
//////////////////////////////////////////////////////////////////////////////////
module
ctrl_unit(oc,control,rb,regwren,memwren,alu_ctrl,ctrl,edp,sel);
input [3:0]oc;
input [1:0]rb;
input control;
output reg [1:0] regwren,sel;
output reg memwren;
output reg[3:0] alu_ctrl;
output ctrl;
output reg edp;
initial
begin
regwren = 2'b11;
edp = 1'b1;
end

// assign opcode to alu_ctrl signal


always @(*)
begin
alu_ctrl <= oc;
end
assign ctrl = control;
// assigning value to edp signal(active low)
always @(*)
begin
edp = ~(oc[3]&oc[2]&oc[1]&oc[0]);
end
// write enable signals(active low)
always @(*)
begin
memwren = 1'b1;
regwren = rb;
case(oc)
4'b1000 :
// multiply
begin
memwren = 1'b1;
regwren = 2'b00;
end
4'b1001 :
// shift
begin
memwren = 1'b1;
regwren = 2'b00;
end
4'b1011 :
begin
if(ctrl)

// memory

// store
begin
memwren = 1'b0;
regwren = 2'b11;
end
else
// load
begin
memwren = 1'b1;

regwren = 2'b00;
end
end
4'b1110 :
begin
memwren = 1'b1;
regwren = 2'b11;
end

// nop

4'b1100 :
// jump
begin
memwren = 1'b1;
regwren = 2'b11;
end
4'b1111 :
begin
memwren = 1'b1;
regwren = 2'b11;
end

// edp

endcase
end
// for sel signal
always @(*)
begin
sel = 2'b00;
case(oc[3:0])
4'b1011 : sel = 2'b01;
4'b1101 :
begin
if(ctrl)
sel = 2'b10;
else
sel = 2'b11;
end
endcase
end
endmodule

// alu
// mem load,store

/// mvi
/// mov

MEMORY WRITE ENABLE LOGIC


UNIT

REGISTER WRITE ENABLE


LOGIC UNIT

SELECT LINE LOGIC UNIT

CONTROL UNIT RTL SCHEMATIC


c) HAZARD UNIT:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 00:12:22 04/07/2014
// Module Name: hazard_unit_final
//////////////////////////////////////////////////////////////////////////////////

module
hazard_unit_final(aD_e,aD_m,aS,aT,cmp_mem_S,cmp_mem_T,c
mp_exe_S,cmp_exe_T);
input [2:0] aD_e,aD_m,aS,aT;
output reg
cmp_mem_S,cmp_mem_T,cmp_exe_S,cmp_exe_T;
initial
begin
cmp_mem_S = 1'b0;
cmp_mem_T = 1'b0;
cmp_exe_S = 1'b0;
cmp_exe_T = 1'b0;
end
always @(*)
begin
cmp_mem_S = 1'b0;
cmp_mem_T = 1'b0;
cmp_exe_S = 1'b0;
cmp_exe_T = 1'b0;
if(aD_e == aS) //comparing src1 addr with dest addr of
exe stage
cmp_exe_S = 1'b1;
if(aD_e == aT) //comparing src2 addr with dest addr of
exe stage
cmp_exe_T = 1'b1;
if(aD_m == aS)
//comparing src1 addr with dest
addr of mem stage
cmp_mem_S = 1'b1;
if(aD_m == aT)
//comparing src2 addr with dest
addr of mem stage
cmp_mem_T = 1'b1;
end
endmodule

HAZARD UNIT RTL SCHEMATIC

STAGE 3: EXECUTION UNIT


INPUT AND OUTPUT LINES:

I/O LINES OF EXECUTION UNIT

i.

INTERNAL BLOCKS OF EXECUTION UNIT:


VERILOG CODE FOR EXECUTION UNIT:

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:27:46 04/08/2014
// Module Name: stage3
//////////////////////////////////////////////////////////////////////////////////
module stage3(
rT_e, rS_e, sel_e,alu_ctrl_e,ctrl_e, shift_e,
MviData_e,
cmp_exe_S_e, cmp_mem_S_e, cmp_exe_T_e,
cmp_mem_T_e,
regwren_e, regwren_m,regwren_wb, frwd_mem, frwd_wb,
out_e
);
input [15:0] rT_e, rS_e;
input cmp_exe_S_e, cmp_mem_S_e, cmp_exe_T_e,
cmp_mem_T_e;
wire
wire
wire
wire

[7:0]w1_s,w2_s,w3_s,w4_s;
cmp1,cmp2,cmp3,cmp4;
[7:0]w1_t,w2_t,w3_t,w4_t;
cmp5,cmp6,cmp7,cmp8;

input [1:0]regwren_e,regwren_m,regwren_wb,sel_e;
wire [15:0]MovData_e;
wire [15:0]MemData_e;
input [7:0]MviData_e;
output [15:0]out_e;
wire [15:0] A,B,Y;
input
input
input
input

[3:0]alu_ctrl_e;
ctrl_e;
[2:0]shift_e;
[15:0]frwd_mem, frwd_wb;

assign cmp1 = cmp_exe_S_e & (~regwren_m[0]);


//
sel lines for mux to select between forwarded data
assign cmp2 = cmp_mem_S_e & (~regwren_wb[0]); // or
previous data considering higher & lower bytes
assign cmp3 = cmp_exe_S_e & (~regwren_m[1]);
//
using destn addr, src addr & regwren signals for src 1
assign cmp4 = cmp_mem_S_e & (~regwren_wb[1]);

two_one_mux e_m_1 [7:0] (rS_e[7:0],frwd_mem[7:0],cmp1,w1_s);


two_one_mux e_m_2 [7:0] (w1_s,frwd_wb[7:0],cmp2,w2_s);
// to
select source 1 data
two_one_mux e_m_3 [7:0]
(rS_e[15:8],frwd_mem[15:8],cmp3,w3_s);
two_one_mux e_m_4 [7:0] (w3_s,frwd_wb[15:8],cmp4,w4_s);
four_one_demux e_dm_1 [15:0] ({w4_s,w2_s},sel_e,A,MemData_e,
, MovData_e ); //to seperate src1 data depending on select line
assign cmp5 = cmp_exe_T_e & (~regwren_m[0]);
//sel
lines for mux to select between forwarded data
assign cmp6 = cmp_mem_T_e & (~regwren_wb[0]); // or
previous data considering higher & lower bytes
assign cmp7 = cmp_exe_T_e & (~regwren_m[1]);
//
using destn addr, src addr & regwren signals for src 1
assign cmp8 = cmp_mem_T_e & (~regwren_wb[1]);
two_one_mux e_m_5 [7:0] (rT_e[7:0],frwd_mem[7:0],cmp5,w1_t);
two_one_mux e_m_6 [7:0] (w1_t,frwd_wb[7:0],cmp6,w2_t); // to
select source 2 data
two_one_mux e_m_7 [7:0]
(rT_e[15:8],frwd_mem[15:8],cmp7,w3_t);
two_one_mux e_m_8 [7:0] (w3_t,frwd_wb[15:8],cmp8,w4_t);
assign B = {w4_t,w2_t};
ALU_processor
call_stage3(A,B,alu_ctrl_e,ctrl_e,regwren_e,Y,shift_e); //
alu
four_one_mux e_fm_1 [15:0] (Y,MemData_e,
{MviData_e,MviData_e},MovData_e,sel_e,out_e);

endmodule

call to

ALU UNIT

EXECUTION STAGE RTL SCHEMATIC

i.

ALU UNIT:

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 15:55:31 04/05/2014
// Module Name: ALU_processor
//////////////////////////////////////////////////////////////////////////////////
module ALU_processor(a,b,alu_ctrl,ctrl,rb,y,shift);
input [15:0] a;
input [15:0] b;
output [15:0] y;
input [2:0] shift;
input [3:0] alu_ctrl;
input ctrl;
input [1:0] rb;
wire [15:0] w0,w1;
arith a1 (a,b,alu_ctrl,ctrl,rb,shift,w0);

//arithmetic unit

logic_unit l1 (a,b,rb,alu_ctrl[1:0],ctrl,w1); //logical unit


two_one_mux m1 [15:0](w0,w1,alu_ctrl[2],y);
between two units
endmodule

//to select

ALU RTL SCHEMATIC

a) ARITHMATIC UNIT:

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 13:11:19 04/05/2014
// Module Name: arith
//////////////////////////////////////////////////////////////////////////////////
module arith(a,b,alu_ctrl,ctrl,rb,shift,yarith);
input [15:0] a;
input [15:0] b;
output [15:0] yarith;
input [2:0] shift;
input [3:0] alu_ctrl;
input ctrl;
input [1:0] rb;
wire [15:0] w0,w1,w7,w10,w11,w12;
wire [7:0] w2,w3,w4,w5,w6,w8,w9;
wire [15:0] i0;

four_one_mux f1 [15:0] (b,(~b+16'b1),16'b1,


{16{1'b1}},alu_ctrl[1:0],w0); //to select
addition,substraction,inc,dec
cla16 adder1(a,w0,1'b0,w1); //16 bit adder
two_one_mux t1 [7:0] (a[15:8],a[7:0],rb[1],w2); // to select
higher byte or lower byte for 8 bit operation
four_one_mux f2 [7:0] (b[15:8],(~b[15:8]+8'b1),8'b1,
{8{1'b1}},alu_ctrl[1:0],w3); //to select
addition,substraction,inc,dec
// for higher 8 bits
four_one_mux f3 [7:0] (b[7:0],(~b[7:0]+8'b1),8'b1,
{8{1'b1}},alu_ctrl[1:0],w4);
//to select
addition,substraction,inc,dec
// for lower 8 bits
two_one_mux t2 [7:0] (w3,w4,rb[1],w5);
cla8 adder2(w2,w5,1'b0,w6);
two_one_mux i0_mux [15:0]({w6,8'b0000_0000},
{8'b0000_0000,w6},rb[1],i0);
// to convert 8 bit op into 16
bit data
two_one_mux t3 [15:0] (w1,i0,(rb[0]^rb[1]),w7);
//
two_one_mux t4 [7:0] (a[7:0],a[15:8],ctrl,w8);
//to select lower or higher byte for mul
two_one_mux t5 [7:0] (b[7:0],b[15:8],ctrl,w9);
//to select lower or higher byte for mul
eight_unsigned multiplier(w8,w9,w10);
shifter s1 (a,shift,ctrl,w11);

two_one_mux t6 [15:0] (w10,w11,alu_ctrl[0],w12); // mul or


shift
two_one_mux t7 [15:0] (w7,w12,(alu_ctrl[3]|alu_ctrl[2]),yarith);
//final op
endmodule

ARITHMATIC UNIT RTL SCHEMATIC

COMPONENTS OF ARITHMATIC UNIT:

1. 4BIT CLA:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 03:13:55 04/07/2014
// Module Name: cla_4
//////////////////////////////////////////////////////////////////////////////////
module cla_4(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [3:0]g,p,c;
assign
assign
assign
assign
assign
assign
assign
assign

g[0]
p[0]
g[1]
p[1]
g[2]
p[2]
g[3]
p[3]

=
=
=
=
=
=
=
=

a[0]&b[0];
a[0]^b[0];
a[1]&b[1];
a[1]^b[1];
a[2]&b[2];
a[2]^b[2];
a[3]&b[3];
a[3]^b[3];

assign c[0] = g[0] | (p[0]&cin);


assign c[1] = g[1] | (p[1]&g[0]) | (p[1]&p[0]&cin);
assign c[2] = g[2] | (p[2]&g[1]) | (p[2]&p[1]&g[0]) |
(p[2]&p[1]&p[0]&cin) ;
assign cout = g[3] |(p[3]&g[2]) |(p[3]&p[2]&g[1]) |
(p[3]&p[2]&p[1]&g[0]) | (p[3]&p[2]&p[1]&p[0]&cin);
assign
assign
assign
assign

s[0]
s[1]
s[2]
s[3]

endmodule

=
=
=
=

p[0]^cin;
p[1]^c[0];
p[2]^c[1];
p[3]^c[2];

4BIT CLA RTL


2. 16BIT CLA:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 03:13:55 04/07/2014
// Module Name: cla_4
//////////////////////////////////////////////////////////////////////////////////
module cla_4(a,b,cin,s,cout);
input [3:0]a,b;

input cin;
output [3:0]s;
output cout;
wire [3:0]g,p,c;
assign
assign
assign
assign
assign
assign
assign
assign

g[0]
p[0]
g[1]
p[1]
g[2]
p[2]
g[3]
p[3]

=
=
=
=
=
=
=
=

a[0]&b[0];
a[0]^b[0];
a[1]&b[1];
a[1]^b[1];
a[2]&b[2];
a[2]^b[2];
a[3]&b[3];
a[3]^b[3];

assign c[0] = g[0] | (p[0]&cin);


assign c[1] = g[1] | (p[1]&g[0]) | (p[1]&p[0]&cin);
assign c[2] = g[2] | (p[2]&g[1]) | (p[2]&p[1]&g[0]) |
(p[2]&p[1]&p[0]&cin) ;
assign cout = g[3] |(p[3]&g[2]) |(p[3]&p[2]&g[1]) |
(p[3]&p[2]&p[1]&g[0]) | (p[3]&p[2]&p[1]&p[0]&cin);
assign
assign
assign
assign

s[0]
s[1]
s[2]
s[3]

endmodule

=
=
=
=

p[0]^cin;
p[1]^c[0];
p[2]^c[1];
p[3]^c[2];

16 BIT CLA RTL SCHEMATIC

3. 8BIT CLA:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 03:19:16 04/07/2014
// Module Name: cla8
//////////////////////////////////////////////////////////////////////////////////
module cla8(a,b,cin,s);

input [7:0]a,b;
input cin;
output [7:0]s;
wire c1,c2;
cla_4 add1(a[3:0],b[3:0],cin,s[3:0],c1);
cla_4 add2(a[7:4],b[7:4],c1,s[7:4],c2);
endmodule

8BIT CLA RTL SCHEMATIC

4. 8 BIT UNSIGNED MULTIPLIER:

a) HALF ADDER:
//////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 10:35:06 03/08/2014
// Module Name: ha
//////////////////////////////////////////////////////////////////////////////
module ha(a,b,s,cout);
input a;
input b;
output s;
output cout;
assign s= a^b;
assign cout= a&b;
endmodule

HALF ADDER RTL SCHEMATIC


b) FULL ADDER:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 10:37:46 03/08/2014

// Module Name: fa
//////////////////////////////////////////////////////////////////////////////////
module fa(a,b,cin,s,cout);
input a;
input b;
input cin;
output s;
output cout;
assign s= a^b^cin;
assign cout= (a&b)|(b&cin)|(a&cin);
endmodule

FULL ADDER RTL SCHEMATIC


5. SHIFTER UNIT:
//////////////////////////////////////////////////////////////////////////////////

// Engineer: Harshad, Ritesh, Sanjog, Rohit.


// Create Date: 15:09:29 04/05/2014
// Module Name: shifter
//////////////////////////////////////////////////////////////////////////////////
module shifter(a,shift,ctrl,y);
input [15:0] a;
input [2:0] shift;
input ctrl;
output [15:0] y;
wire [15:0] w1,w2;
assign w1 = a<<shift;
assign w2 = a>>shift;
two_one_mux m1 [15:0] (w1,w2,ctrl,y);
endmodule

SHIFTER UNIT RTL SCHEMATIC


b) Logic Unit:

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 16:59:43 04/06/2014
// Module Name: logic_unit
//////////////////////////////////////////////////////////////////////////////////
module logic_unit(a,b,rb,alu_ctrl,ctrl,y);
input [15:0]a,b;
input [1:0]rb,alu_ctrl;
input ctrl;
output [15:0]y;
wire [15:0]w_and, w_or, w_exor, w_out,w1;
assign w_and = a & b;
assign w_or = a | b;
assign w_exor = a ^ b;
four_one_mux mux_logic [15:0]
(w_and,w_or,w_exor,a,alu_ctrl,w_out);

two_one_mux mux_gate [15:0] (w_out,(~w_out),ctrl,w1);


four_one_mux m2 [15:0] (w1,{w1[15:8],8'b00000000},
{8'b00000000,w1[7:0]},w1,rb,y);
endmodule

LOGIC UNIT RTL SCHEMATIC

STAGE 4: MEMORY WRITE:


i.

ii.

INPUT OUTPUT LINES:

INTERNAL BLOCKS OF MEMORY WRITE:


INSTRUCTION MEMORY:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date:

22:00:24 04/05/2014

// Module Name:

data_memory

//////////////////////////////////////////////////////////////////////////////////
module data_memory(a,w,clock,w_en,r);
parameter N=3,M=16; //N => memory address size, M =>
Memory data size

input[N-1:0]a; //memory address


input[M-1:0]w;
input clock;

//memory write data input

input w_en;

//write Enable

output reg[M-1:0]r;

//Memory read output

reg [M-1:0]mem[2**N-1:0];
[2^(N) - 1 : 0]

always @(posedge clock)

//declaration of 8x16 memory

//write on positive clk edge

begin
if(w_en == 1'b0)
mem[a] <= w;

// write data in memory

end
always @(negedge clock

//Mem read on negative clk edge

begin
r <= mem[a];
end
endmodule

// read data from memory

DATA MEMORY AND EDP INST. LOGIC RTL SCHEMATIC


VERILOG CODE FOR MEMORY WRITE STAGE:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:53:14 04/09/2014
// Module Name: stage4
//////////////////////////////////////////////////////////////////////////////////
module stage4(clock, in_m, memwren_m,
sel_m,aMem_m,out_mem
);
input
input
input
input
input

clock;
[15:0] in_m;
[1:0] sel_m;
memwren_m;
[2:0]aMem_m;

output [15:0] out_mem;


wire [15:0]readMem_m;

data_memory
data(aMem_m,in_m,clock,memwren_m,readMem_m); // call
data memory
wire m1 = ~sel_m[1]&sel_m[0];// MemData 01
two_one_mux m_1 [15:0](in_m,readMem_m, m1,out_mem); // to
sel between read memory data and out_mem
endmodule

MEMORY WRITE STAGE RTL SCHEMATIC

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