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i.
2:1 MUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:45:04 04/05/2014
// Module Name: two_one_mux
//////////////////////////////////////////////////////////////////////////////////
module two_one_mux(a,b,s,y);
input a,b,s;
output y;
assign y = (~s & a) | (s & b) ;
endmodule
4:1 MUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:47:32 04/05/2014
// Module Name: four_one_mux
//////////////////////////////////////////////////////////////////////////////////
module four_one_mux(a,b,c,d,s,y);
input a,b,c,d;
input [1:0]s;
output reg y;
always @(*)
begin
y = ((~s[1])&(~s[0])&a) | ((~s[1])&s[0]&b) | (s[1]&(~s[0])&c) |
(s[1]&s[0]&d) ;
end
endmodule
iii.
2:1 DEMUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
4:1 DEMUX:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 13:10:06 04/06/2014
in;
in;
in;
in;
endmodule
STAGE 1:
i.
ii.
INTERNAL BLOCKS:
/// for
//mux select line
a) INCREMENTER:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 00:48:03 04/06/2014
// Design Name:
// Module Name: adder_IF_8
//////////////////////////////////////////////////////////////////////////////////
module adder_IF_8(a,b,y);
input [7:0]a,b;
output [7:0]y;
assign
y = a+b;
endmodule
INCREMENTER
b) INSTRUCTION MEMORY:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 00:58:03 04/08/2014
// Module Name: INSTRUCT_MEM
//////////////////////////////////////////////////////////////////////////////////
module INSTRUCT_MEM(a,r);
input [7:0]a;
output [15:0]r;
output
reg [15:0]rom[19:0];
(2^8 * 16)
//Memory Address
//Memory data
initial
begin
$readmemh("hazard.list.txt",rom);
//Read and copy hex code from text file to memory
end
assign r = rom[a];
memory
endmodule
//Read from
INSTRUCTION MEMORY
STAGE 2:
i.
ii.
Internal Blocks:
Stage 2 Verilog Code:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 12:33:30 04/06/2014
// Module Name: STAGE_2
//////////////////////////////////////////////////////////////////////////////////
module STAGE_2(clock, inst,
wD, aD, w_en, rT, rS,
regwren,memwren,sel,alu_ctrl,ctrl,edp,
shift,aMem,aDest,
jmp_disp,
MviData,
aS,aT
);
input clock;
input [15:0]inst;
via buffer
wire [8:0]inst_copy,mvi;
output [7:0]MviData;
wire [3:0]oc;
wire [1:0]rb;
wire control;
output [1:0] regwren,sel;
output memwren;
output [3:0] alu_ctrl;
output ctrl;
output edp;
output reg[2:0] aS;
output reg[2:0] aT;
input [2:0] aD;
input [15:0] wD;
input [1:0] w_en;
output [15:0] rS;
output [15:0] rT;
//source 1
//source 2
//dest. register address
//data to be written
//active low write enable
//scr1 o/p
//scr2 o/p
assign
assign
assign
assign
oc = inst[15:12]; //opcode
rb = inst[10:9];
//reconfig bits
control = inst[11];
//control bit
jmp_disp = inst[2:0]; // jump displacement to stage 1
wire mvi_w =
alu_ctrl[3]&
alu_ctrl[2]&(
~alu_ctrl[1])
&alu_ctrl[0]
&ctrl; /*sele
ct
line to mvi mux*/
two_one_demux td [8:0](inst[8:0],mvi_w,inst_copy,mvi);
//to
select MVIdata
or //instruction
copy
assign MviData = mvi[7:0];
//to select 8 bit MVIdata
//---always block to select address of source 1---//
always @(*)
begin
aS = inst_copy[5:3] ;
case(oc)
4'b1011 :
begin
if(ctrl == 1'b0)
aS = 3'bxxx;
// load
end
4'b1100 : aS = 3'bxxx;
4'b1110 : aS = 3'bxxx;
4'b1111 : aS = 3'bxxx;
endcase
end
// jmp
// nop
// edp
// incr
// decr
// rep and not
// mov
//call to
ctrl_unit
call_control(oc,control,rb,regwren,memwren,alu_ctrl,ctrl,edp,sel);
//call to control unit
//---always block for destination address---//
always @(*)
begin
aDest = inst_copy[8:6];
case(oc)
4'b1101 :
begin
if(ctrl)
aDest = 3'b000;
end
4'b1011 :
begin
// mvi
if(ctrl)
// store
aDest = 3'bxxx;
end
4'b1100 : aDest = 3'bxxx;
4'b1110 : aDest = 3'bxxx;
4'b1111 : aDest = 3'bxxx;
endcase
end
endmodule
CONTROL
UNIT
REGISTER
// jmp
// nop
// edp
a) REGISTER FILE:
/////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 22:11:31 04/05/2014
// Module Name: reg_file
//////////////////////////////////////////////////////////////////////////////////
module reg_file(aS,aT,clk,aD,wD,rS,rT,w_en);
input clk;
//input [1:0] rb;
//active low reconfigurable bits
input [2:0] aS;
//source 1
input [2:0] aT;
//source 2
input [2:0] aD;
//dest. register
input [15:0] wD;
//data to be written
input [1:0] w_en;
//active low write enable
output reg [15:0] rS;
//scr1 o/p
output reg [15:0] rT;
//scr2 o/p
reg [15:0]gpr[7:0];
always@(negedge clk)
begin
rS<=gpr[aS];
rT<=gpr[aT];
end
always@(posedge clk)
begin
if(w_en == 2'b00)
gpr[aD] <= wD;
//write at positive
//edge
//16 bit write
b) Control Unit:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 01:47:50 04/06/2014
// Module Name: ctrl_unit
//////////////////////////////////////////////////////////////////////////////////
module
ctrl_unit(oc,control,rb,regwren,memwren,alu_ctrl,ctrl,edp,sel);
input [3:0]oc;
input [1:0]rb;
input control;
output reg [1:0] regwren,sel;
output reg memwren;
output reg[3:0] alu_ctrl;
output ctrl;
output reg edp;
initial
begin
regwren = 2'b11;
edp = 1'b1;
end
// memory
// store
begin
memwren = 1'b0;
regwren = 2'b11;
end
else
// load
begin
memwren = 1'b1;
regwren = 2'b00;
end
end
4'b1110 :
begin
memwren = 1'b1;
regwren = 2'b11;
end
// nop
4'b1100 :
// jump
begin
memwren = 1'b1;
regwren = 2'b11;
end
4'b1111 :
begin
memwren = 1'b1;
regwren = 2'b11;
end
// edp
endcase
end
// for sel signal
always @(*)
begin
sel = 2'b00;
case(oc[3:0])
4'b1011 : sel = 2'b01;
4'b1101 :
begin
if(ctrl)
sel = 2'b10;
else
sel = 2'b11;
end
endcase
end
endmodule
// alu
// mem load,store
/// mvi
/// mov
module
hazard_unit_final(aD_e,aD_m,aS,aT,cmp_mem_S,cmp_mem_T,c
mp_exe_S,cmp_exe_T);
input [2:0] aD_e,aD_m,aS,aT;
output reg
cmp_mem_S,cmp_mem_T,cmp_exe_S,cmp_exe_T;
initial
begin
cmp_mem_S = 1'b0;
cmp_mem_T = 1'b0;
cmp_exe_S = 1'b0;
cmp_exe_T = 1'b0;
end
always @(*)
begin
cmp_mem_S = 1'b0;
cmp_mem_T = 1'b0;
cmp_exe_S = 1'b0;
cmp_exe_T = 1'b0;
if(aD_e == aS) //comparing src1 addr with dest addr of
exe stage
cmp_exe_S = 1'b1;
if(aD_e == aT) //comparing src2 addr with dest addr of
exe stage
cmp_exe_T = 1'b1;
if(aD_m == aS)
//comparing src1 addr with dest
addr of mem stage
cmp_mem_S = 1'b1;
if(aD_m == aT)
//comparing src2 addr with dest
addr of mem stage
cmp_mem_T = 1'b1;
end
endmodule
i.
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 23:27:46 04/08/2014
// Module Name: stage3
//////////////////////////////////////////////////////////////////////////////////
module stage3(
rT_e, rS_e, sel_e,alu_ctrl_e,ctrl_e, shift_e,
MviData_e,
cmp_exe_S_e, cmp_mem_S_e, cmp_exe_T_e,
cmp_mem_T_e,
regwren_e, regwren_m,regwren_wb, frwd_mem, frwd_wb,
out_e
);
input [15:0] rT_e, rS_e;
input cmp_exe_S_e, cmp_mem_S_e, cmp_exe_T_e,
cmp_mem_T_e;
wire
wire
wire
wire
[7:0]w1_s,w2_s,w3_s,w4_s;
cmp1,cmp2,cmp3,cmp4;
[7:0]w1_t,w2_t,w3_t,w4_t;
cmp5,cmp6,cmp7,cmp8;
input [1:0]regwren_e,regwren_m,regwren_wb,sel_e;
wire [15:0]MovData_e;
wire [15:0]MemData_e;
input [7:0]MviData_e;
output [15:0]out_e;
wire [15:0] A,B,Y;
input
input
input
input
[3:0]alu_ctrl_e;
ctrl_e;
[2:0]shift_e;
[15:0]frwd_mem, frwd_wb;
endmodule
call to
ALU UNIT
i.
ALU UNIT:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 15:55:31 04/05/2014
// Module Name: ALU_processor
//////////////////////////////////////////////////////////////////////////////////
module ALU_processor(a,b,alu_ctrl,ctrl,rb,y,shift);
input [15:0] a;
input [15:0] b;
output [15:0] y;
input [2:0] shift;
input [3:0] alu_ctrl;
input ctrl;
input [1:0] rb;
wire [15:0] w0,w1;
arith a1 (a,b,alu_ctrl,ctrl,rb,shift,w0);
//arithmetic unit
//to select
a) ARITHMATIC UNIT:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 13:11:19 04/05/2014
// Module Name: arith
//////////////////////////////////////////////////////////////////////////////////
module arith(a,b,alu_ctrl,ctrl,rb,shift,yarith);
input [15:0] a;
input [15:0] b;
output [15:0] yarith;
input [2:0] shift;
input [3:0] alu_ctrl;
input ctrl;
input [1:0] rb;
wire [15:0] w0,w1,w7,w10,w11,w12;
wire [7:0] w2,w3,w4,w5,w6,w8,w9;
wire [15:0] i0;
1. 4BIT CLA:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 03:13:55 04/07/2014
// Module Name: cla_4
//////////////////////////////////////////////////////////////////////////////////
module cla_4(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [3:0]g,p,c;
assign
assign
assign
assign
assign
assign
assign
assign
g[0]
p[0]
g[1]
p[1]
g[2]
p[2]
g[3]
p[3]
=
=
=
=
=
=
=
=
a[0]&b[0];
a[0]^b[0];
a[1]&b[1];
a[1]^b[1];
a[2]&b[2];
a[2]^b[2];
a[3]&b[3];
a[3]^b[3];
s[0]
s[1]
s[2]
s[3]
endmodule
=
=
=
=
p[0]^cin;
p[1]^c[0];
p[2]^c[1];
p[3]^c[2];
input cin;
output [3:0]s;
output cout;
wire [3:0]g,p,c;
assign
assign
assign
assign
assign
assign
assign
assign
g[0]
p[0]
g[1]
p[1]
g[2]
p[2]
g[3]
p[3]
=
=
=
=
=
=
=
=
a[0]&b[0];
a[0]^b[0];
a[1]&b[1];
a[1]^b[1];
a[2]&b[2];
a[2]^b[2];
a[3]&b[3];
a[3]^b[3];
s[0]
s[1]
s[2]
s[3]
endmodule
=
=
=
=
p[0]^cin;
p[1]^c[0];
p[2]^c[1];
p[3]^c[2];
3. 8BIT CLA:
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 03:19:16 04/07/2014
// Module Name: cla8
//////////////////////////////////////////////////////////////////////////////////
module cla8(a,b,cin,s);
input [7:0]a,b;
input cin;
output [7:0]s;
wire c1,c2;
cla_4 add1(a[3:0],b[3:0],cin,s[3:0],c1);
cla_4 add2(a[7:4],b[7:4],c1,s[7:4],c2);
endmodule
a) HALF ADDER:
//////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 10:35:06 03/08/2014
// Module Name: ha
//////////////////////////////////////////////////////////////////////////////
module ha(a,b,s,cout);
input a;
input b;
output s;
output cout;
assign s= a^b;
assign cout= a&b;
endmodule
// Module Name: fa
//////////////////////////////////////////////////////////////////////////////////
module fa(a,b,cin,s,cout);
input a;
input b;
input cin;
output s;
output cout;
assign s= a^b^cin;
assign cout= (a&b)|(b&cin)|(a&cin);
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Harshad, Ritesh, Sanjog, Rohit.
// Create Date: 16:59:43 04/06/2014
// Module Name: logic_unit
//////////////////////////////////////////////////////////////////////////////////
module logic_unit(a,b,rb,alu_ctrl,ctrl,y);
input [15:0]a,b;
input [1:0]rb,alu_ctrl;
input ctrl;
output [15:0]y;
wire [15:0]w_and, w_or, w_exor, w_out,w1;
assign w_and = a & b;
assign w_or = a | b;
assign w_exor = a ^ b;
four_one_mux mux_logic [15:0]
(w_and,w_or,w_exor,a,alu_ctrl,w_out);
ii.
22:00:24 04/05/2014
// Module Name:
data_memory
//////////////////////////////////////////////////////////////////////////////////
module data_memory(a,w,clock,w_en,r);
parameter N=3,M=16; //N => memory address size, M =>
Memory data size
input w_en;
//write Enable
output reg[M-1:0]r;
reg [M-1:0]mem[2**N-1:0];
[2^(N) - 1 : 0]
begin
if(w_en == 1'b0)
mem[a] <= w;
end
always @(negedge clock
begin
r <= mem[a];
end
endmodule
clock;
[15:0] in_m;
[1:0] sel_m;
memwren_m;
[2:0]aMem_m;
data_memory
data(aMem_m,in_m,clock,memwren_m,readMem_m); // call
data memory
wire m1 = ~sel_m[1]&sel_m[0];// MemData 01
two_one_mux m_1 [15:0](in_m,readMem_m, m1,out_mem); // to
sel between read memory data and out_mem
endmodule