EXP:1 VHDL PROGRAM

D FLIP FLOP:
1

library ieee;
use ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (clk)
begin
IF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;

SR FF:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity sr_flip_flop is
port(
s : in STD_LOGIC;
r : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC );
end sr_flip_flop;

architecture behave of sr_flip_flop is

signal t1 :std_logic :='0';
begin
process (s,r,clk,reset) is
begin
if (reset='1') then

t1 <= '0';
elsif (clk='1' and clk 'event) then
if (s='0' and r='0') then
t1 <= '1';
elsif (s='0' and r='1') then
t1 <= '0';
elsif (s='1' and r='0') then
t1 <='1';
elsif (s='1' and r='1') then
t1 <='Z';
end if;
end if;
end process;
q<=t1;qb<=not t1;
end behave;

TFF:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
ENTITY tff IS
PORT ( t, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END tff;
ARCHITECTURE behavior OF tff IS
BEGIN
PROCESS (t,clk)
begin
IF (clk'EVENT AND clk='1') THEN
q <= not t;
END IF;
END PROCESS;
END behavior;

JKFF

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity JKFF is
port(
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC );
end JKFF;

architecture behave of JKFF is

signal qnxt :std_logic :='0';
begin
process (j,k,clk) is
begin
if (clk='1' and clk 'event) then

qnxt<=(j and(not qnxt))or((not k) and qnxt);

end if;
end process;
q<=qnxt;qb<=not qnxt;
end behave;