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A

MODEL NAME : VAW00


PROJECT CODE : ANRVAW0000
PCB NO : LA-9104P (Thames XT )
DA60000VV00 LA-9104P M/B
DA40001FO00 LS-9101P POWER BUTTON/B
DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B

ZZZ

R1@

ZZZ

GCER3@

ZZZ

TRIR3@

PCB VAW00 LA-9104P LS-9101P/9102P/9103P

PCB VAW00 LA-9104P LS-9101P/9102P/9103P GOLD A31 !

PCB VAW00 LA-9104P LS-9101P/9102P/9103P TRIPOD A31 !

DAZ0SZ00200

DAZ0SZ00201

DAZ0SZ00202

ZZZ

ZZZ

HANNR3@

ZDTR3@

PCB VAW00 LA-9104P LS-9101P/9102P/9103P HANNSTARB A31 !

PCB VAW00 LA-9104P LS-9101P/9102P/9103P ZDT A31 !

DAZ0SZ00203

DAZ0SZ00204

Dell / Compal Confidential


Schematic Document

Intel Chief River


Ivy Bridge(BGA) + Panther Point
OAK 15" UMA/DIS AMD Thames XT
2012-08-22
Rev: 1.0

46@ : for 46 level


@ : Nopop Component
CONN@ : Connector Component
KB9012@ : ENE KB9012 Implemented
UMA@ : Only for UMA
EMC@ : EMI/ESD parts

i3R1@ : CPU i3-3217 1.8G


i3VOSR1@ : CPU i3-2365 1.4G
i5R1@ : CPU i5-3317 1.7G
i7R1@ : CPU i7-3517 1.9G
CELR1@ : CPU Celeron 887 1.5G
PENR1@ : CPU Pentium 997 1.6G

R1@ : R1 P/N
R3@ : R3 P/N

GCLK@ : Green CLK implemented


GCLKUMA@ : Green CLK for UMA
GCLKDIS@ : Green CLK for DIS
XTAL@ : X'tal implemented
XTALDIS@ : X'tal with DIS implemented

DIS@ : Only for Discrete


TH@/THR1@ : Thames-XT
MS@/MSR1@ : Mars Pro
X76@ :
SPI-ROM & VRAM Group

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

Compal Electronics, Inc.


Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-9104P

Date:

Wednesday, August 29, 2012


E

Sheet

of

57

64M*16

128M*16

P.40

Intel
Ivy Bridge
Processor
17W DC

64bit

64M*16

AMD
Thames-XT
24-26 W P.24~29

VRAM * 4
P.31
DDR3
128M*16

VRAM * 4
P.31
DDR3

64bit

PEG 2.0 x8

Memory Bus (DDR3)

CPU XDP
Conn. P.6

Fan Control

VRAM * 4
VRAM * 4
P.30 DDR3
P.30
DDR3
1

DDRIII-DIMM X2

Dual Channel

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P.11~12

1.5V DDR3 1333 MHz

8GB Max

BGA 1023
P.5~10

AMD Thames XT, 128b,


Radeon HD7670M,
P5500
1GB DDR3 (8-64Mx16),
2GB DDR3 (8-128Mx16)

FDI x8

DMI x4

100MHz
2.7GT/s

100MHz
5GB/s

SATA3.0

Port 0

SATA HDD Conn.

LVDS

P.35

LVDS Conn.

P.21

Port 2

HDMI

SATA ODD Conn.

HDMI Conn.

Intel
Panther Point
PCH HM76

USB 3.0
USB2.0

Port 2

Mini Card
WLAN/BT4.0
Half
P.38
3

Port 1,2
Port 0,1
Port 2,3

BGA 989 Balls

PCI-E x1

Ethernet
RTL8105E
P.32

USB 3.0 Conn. 1


USB 3.0 Conn. 2

P.36

USB 3.0 Conn. 3


USB 2.0 Conn. 4

P.37

Port 11

Digital Camera
(With Digital MIC) P.21

Port 8

Mini Card
WLAN (Half)

P.38

Card Reader
RTS5179

P.34

Port 1

RJ45

Port 10

P.32

Touch Screen

P13~20

Power On/Off CKT.

SPI ROM
P.44

4MB

3 in 1 Socket

P.34

P.21

2MB

Digital Mic.

SPI

P.13

SPI ROM

P.40

Daughter board

Port 9

HD Audio

RTC CKT.

P.35
2

P.22

Audio Codec

LPC Bus

ALC3221

33MHz

SPI

P.33

Headphone Jack / Mic. Jack combo

P.33

Int. Speaker R / L

P.33

P.13

ENE KBC
KB9012 P.39

DC/DC Interface CKT.

P.41

PS/2
4

Int.KBD
P.40

Touch Pad
P.40

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Block diagram
Size

Document Number

Rev
1.0

LA-9104P
Date:

Wednesday, August 29, 2012


E

Sheet

of

57

Compal Confidential
Project Code : VAW00
File Name : LA-9104P
LS-9101P (PWR/B)
1

Lid

SW1
(SN100004Y00)

UE5
(SA00003VQ00)

4 pin-Hot Bar

PBATT
Battery

JMINI

PWR-BTN FFC

MINI Card

4 pin

JLVDS
40 pin

PJPDC
5 pin

LS-9102P (USB/B)

JTP
6 pin

JHDMI

JKB
30 pin

HDMI

JODD

JTOUCH JPWR
6 pin
4 pin JFAN
3 pin

JLAN

JUSB1

USB

USB-DB FFC

XDP

RJ-45

8 pin

JXDP

LA-9104P M/B

USB
RTC

JUSB2

USB

JUSB3

USB

JDB
8 pin

Top Side
Bottom Side

JRTC
2 pin

JUSB4

8 pin
Hot Bar

JHDD

(OAK 15")
JREAD
JSPK
4 pin

JHP

Card
Reader

HP

TP-MB FFC
6 pin

Led1

Led2

Led3

Led4

TP-Module

TP-BTN FFC

4 pin
LS-9103P (TP-BTN/B)

Issued Date

SW2

SW3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

4 pin
Hot Bar

2012/08/22

2013/08/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DB block diagram
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012

Sheet
E

of

57

Board ID Table for AD channel


Vcc
Ra
Board ID

0
1
2
3
4
5
6
7

3.3V +/100K +/Rb


0
8.2K +/18K +/33K +/56K +/100K +/200K +/NC

5%
5%

5%
5%
5%
5%
5%
5%

BOARD ID Table
V AD_BID min
0 V
0.168 V
0.375 V
0.634 V
0.958 V
1.372 V
1.851 V
2.433 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0.155 V
0.362 V
0.621 V
0.945 V
1.359 V
1.838 V
2.420 V
3.300 V

ID
0
1
2
3
4
5
6
7

EC AD3
0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

Project ID Table

PCB Revision
0.1
0.1
0.1
0.2
0.2
0.2
0.3
0.3
0.3
1.0
1.0
1.0
UMA

THM

Project Revision

ID
0
1
2
3
4
5
6
7

USB PORT#

UMA
DIS THAMES
DIS MARS PRO

MARS

SMBUS Control Table


SOURCE
EC_SMB_CK1
EC_SMB_DA1

KB9012

EC_SMB_CK2
EC_SMB_DA2

KB9012

PCH_SML0CLK
PCH_SML0DATA

PCH

PCH_SML1CLK
PCH_SML1DATA

PCH

MEM_SMBCLK
MEM_SMBDATA

PCH

MINI1

MINI2

BATT

SODIMM

Express
Card

Thermal
Sensor

FFS

VGA Thermal
VGA
Sensor

XDP

Charger

PCH

V
V

V
Link

DIFFERENTIAL

DESTINATION

V
FLEX CLOCKS

V
DESTINATION

DESTINATION

USB conn.2

USB conn.1

USB conn.3

USB conn.4 (DB)

NC

NC

NC

NC

MINI CARD (WLAN)

Touch Screen

10

Card Reader

11

Camera

12

NC

13

NC

CLK

CLKOUT_PCIE0

10/100 LAN

CLKOUTFLEX0

None

CLKOUT_PCIE1

MINI CARD WLAN

CLKOUTFLEX1

None

CLKOUT_PCIE2

None

CLKOUTFLEX2

None

CLKOUT_PCIE3

None

CLKOUTFLEX3

None

CLKOUT_PCIE4

None

CLKOUT_PCIE5

None

CLKOUT_PCIE6

None

CLKOUT
PCI0
CLKOUT_PCIE7

None

CLKOUT_PEG_B

None

Symbol Note :

: means Digital Ground

DESTINATION
PCH_LOOPBACK

PCI1

EC LPC

PCI2

None

PCI3

None

PCI4

None

SATA

DESTINATION

PCI EXPRESS

DESTINATION

SATA0

HDD

Lane 1

10/100 LAN

SATA1

None

Lane 2

MINI CARD (WLAN)

SATA2

ODD

Lane 3

None

SATA3

None

Lane 4

None

SATA4

None

Lane 5

None

SATA5

None

Lane 6

None

Lane 7

None

Lane 8

None

: means Analog Ground


Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012

Sheet

of

57

UC1

i3R1@

UC1

SA00005L52L

UC1

i5R3@

i3VOSR3@

SA00005UH2L

AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

AV8062701313000-SR0U3-J1-1.4G_BGA1023~D

UC1

UC1

i7R1@

i7R3@

SA00005K53L

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
UC1

UC1

SA00005UH1L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D

SA00005K62L

(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC1.
(2)PEG_ICOMPO use 12mil connect to RC1

i3VOSR1@

SA00005L53L

AV8063801058401-SR0N9-L1-1.8G_BGA1023~D
UC1

i3R3@

CELR1@

SA00005K52L

AV8063801057605-SR0N6-L1-1.9G_BGA1023~D
UC1

AV8063801057605-SR0N6-L1-1.9G_BGA1023~D

CELR3@

PEG_RCOMPO (G4)

width 4 mils

PEG_ICOMPI (G3)
Trace length
Max is 500 mils

SA00006021L

R_COMP place close to CPU

width 12 mils

PEG_ICOMPO (G1)

VCC_IO

SA00006022L

AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D

AV8062701085401-SR0VA-Q0-1.5G_BGA1023~D

UC1

UC1

PENR1@

PENR3@

R_COMP
SA00005ZZ1L

SA00005ZZ2L

+VCCP

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

RC2
24.9_0402_1%

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

<15>
<15>
<15>
<15>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

<15>
<15>
<15>
<15>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<15>
<15>

FDI_FSYNC0
FDI_FSYNC1

FDI_FSYNC0
FDI_FSYNC1

<15>

FDI_INT

FDI_INT

<15>
<15>

FDI_LSYNC0
FDI_LSYNC1

FDI_LSYNC0
FDI_LSYNC1

N3
P7
P3
P11
K1
M8
N4
R2
K3
M7
P4
T3

U7
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1 W11
FDI_CTX_PRX_N2 W1
FDI_CTX_PRX_N3 AA6
FDI_CTX_PRX_N4 W6
V4
FDI_CTX_PRX_N5
Y2
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7 AC9
U6
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1 W10
FDI_CTX_PRX_P2 W3
FDI_CTX_PRX_P3 AA7
FDI_CTX_PRX_P4 W7
T4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6 AA3
FDI_CTX_PRX_P7 AC8
AA11
AC12
U11
AA10
AG8

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC

+VCCP

1
RC36
2
RC158

2
+EDP_COM
24.9_0402_1%
1
10K_0402_5%

AG4
AF4
AC3
AC4
AE11
AE7
AC1
AA4
AE10
AE6

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

eDP

eDP_COMPIO and ICOMPO signals should be shorted near


balls and routed with typical impedance <25 mohms

AF3
AD2
AG11

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PCI EXPRESS -- GRAPHICS

<15>
<15>
<15>
<15>

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

Intel(R) FDI

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

DMI

M2
P6
P1
P10

<15>
<15>
<15>
<15>

i5R1@

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

G3
G1
G4

UC1I

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_COMP

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_ICOMPI and RCOMPO signals should be shorted and routed


with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms

PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

CC9
CC10
CC11
CC12
CC13
CC14
CC15
CC16

CC25
CC26
CC27
CC28
CC29
CC30
CC31
CC32

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K
220nF_0402_16V7K

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>

i5R1@

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

@
RC20

1K_0402_5%

NCTF

UC1A

SA00005K63L

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(1/6) DMI,FDI,PEG
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

of

57

+VCCP

+VCCP

+3VALW

<15,40>

PCH_PWROK

<15>

SYS_PWROK

+3V_PCH
+3VS

H_CPUPWRGD
<15,40>

PBTN_OUT#

<8> CFG0
<15,52> VGATE

<13>

<11,12,14,38>
<11,12,14,38>
PCH_JTAG_TCK

1K_0402_5%
0_0402_5%

1
1

@
@

2 RC22
2 RC31

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

1K_0402_5%
0_0402_5%

1
1

@
@

2 RC38
2 RC34

XDP_HOOK2
SYS_PWROK_XDP

PCH_SMBDATA
PCH_SMBCLK

2 RC30

0_0402_5%

XDP_TCK1
XDP_TCK_R

1
2

2
1

1
2

VDDPWRGOOD

2
200_0402_1%

Place near JXDP1

RC8
CRB 1.1K
CHECK LIST 0.7 --> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev -->200

RC28
39_0402_1%

CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_R
XDP_DBRESET#

CLK_CPU_ITP <14>
CLK_CPU_ITP#
<14>

1
@
RC55

XDP_TDO
RC33 1
XDP_TRST#_R
XDP_TDI
RC37 1
XDP_TMS_R RC39 1

2
1K_0402_5%

PLT_RST#

<10,35>

RUN_ON_CPU1.5VS3#

RUN_ON_CPU1.5VS3#

QC1 @
2N7002K_SOT23-3

G
S

2 0_0402_5%

PCH_JTAG_TDO

@
@

2 0_0402_5%
2 0_0402_5%

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

<13>

+3VALW

SAMTE_BSH-030-01-L-D-A
CONN@

SP02000L900

RC59
75_0402_5%
C

+VCCP

CC34
0.1U_0402_16V7K

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

74AHC1G09GW TSSOP 5P

RC5

+3V_PCH

B
VCC
A
GND
Y

UC3
<16,32,38,40>

1
2
3

PLT_RST#

NC VCC
A
GND
Y

RC58
1
2
43_0402_1%

BUFO_CPU_RST#

BUF_CPU_RST#

@
+VCCP

2
@
UC1B

<17>

F49

H_SNB_IVB#

RC124

110K_0402_5%

H_CATERR#

<17,40>

A48

H_PECI

H_PECI
@ CC151
0.1U_0402_10V7K~D

PROC_DETECT#

<40,46>

1
RC57

H_PROCHOT#

2 H_PROCHOT#_R
56_0402_1%

place RC57 near CPU

2
<17>

1
RC130

H_THERMTRIP#

C45

PECI

PROCHOT#

300mils ~1530mils
2 H_THERMTRIP#_R
0_0402_1%

D45

BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
BCLK_ITP
BCLK_ITP#

J3
H2
AG3
AG1

CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

CLK_CPU_DMI
CLK_CPU_DMI#

<14>
<14>

RC65 1
RC77 1

2 1K_0402_1%
2 1K_0402_1%

PU/PD for JTAG signals

+VCCP

Remove DPLL Ref clock (for eDP only)

+VCCP

N59
N58

CATERR#

VR1 TOPOLOGY

1
B

C49

PROC_SELECT#

THERMAL

PROC_DETECT (Processor Detect): pulled to


ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this
signal to determine if the processor is present

C57

@
RC62
0_0402_5%

i5R1@

CLOCKS

2
H_THERMTRIP#
56_0402_1%
2
H_CATERR#
49.9_0402_1%~D
2
H_PROCHOT#
62_0402_5%~D

SM_DRAMRST#

DDR3
MISC

MISC

1
RC127
1
RC128
1
RC44

CC63
0.1U_0402_16V7K

SN74LVC1G07DCKR_SC70-5~D

XDP_BPM#6
XDP_BPM#7

2
UC2

1
2
3

RC8
200_0402_1%

XDP_BPM#4
XDP_BPM#5

2D_PWG
@
0_0402_1%

+1.5V_CPU_VDDQ

CFG10_R
CFG11_R

1
RC11

PM_DRAM_PWRGD

1 RC13
1 RC15

@
@

<15>

@
RC6
10K_0402_5%

2
2

0_0402_5%
0_0402_5%

CFG10
CFG11

RC132
0_0402_1%
@

<8>
<8>

XDP_BPM#2
XDP_BPM#3

RC129

+VCCP

CC36
0.1U_0402_16V7K

SYS_PWROK_XDP

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

CC35
0.1U_0402_16V7K

XDP_BPM#0
XDP_BPM#1

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

0_0402_5%
1
2

XDP_PREQ#_R
XDP_PRDY#_R

@
RC49
1K_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

CC33
0.1U_0402_16V7K

JXDP

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

AT30

H_DRAMRST#

BF44
BE43
BG43

SM_RCOMP0 140_0402_1% 1
SM_RCOMP1 25.5_0402_1%1
SM_RCOMP2 200_0402_1% 1

H_DRAMRST#

H_DRAMRST#

<7>

2 RC86
2 RC83
2 RC85

DDR3 Compensation Signals

@
CC143
0.1U_0402_25V6K

51_0402_5% 1

XDP_TDI_R

51_0402_5% 1

2 RC47

XDP_PREQ#

51_0402_5% 1

XDP_TDO

51_0402_5% 1

2 RC106

XDP_TCK_R

51_0402_5% 1

2 RC105

XDP_TRST#_R 51_0402_5% 1

2 RC104

2 RC46
@

2 RC48

Place close to CPU

THERMTRIP#

XDP_TMS_R

Place on BOTTOM(-4059,5169) area.

<17>

H_PM_SYNC

H_PM_SYNC

1
RC25

H_CPUPWRGD

2 VCCPWRGOOD_0_R
1K_0402_5%

PRDY#
PREQ#

C48

B46

PM_SYNC

UNCOREPWRGOOD

RC64
VDDPWRGOOD 1
VDDPWRGOOD_R
@
CC142
0.1U_0402_25V6K

CC141

VDDPWRGOOD_R

BE45

SM_DRAMPWROK

130_0402_1%
@

0.1U_0402_25V6K

BUF_CPU_RST#

D44

RESET#

Place close to CPU

PWR MANAGEMENT

<15>

250mils~2530 mils

JTAG & BPM

place RC129 near CPU

ESD request to reserve CC141

TCK
TMS
TRST#
TDI
TDO

N53
N55

XDP_PRDY#
XDP_PREQ#

RC125
RC135

1
1

@
@

2 0_0402_5%
2 0_0402_5%

XDP_PRDY#_R
XDP_PREQ#_R

L56
L55
J58

XDP_TCK
XDP_TMS
XDP_TRST#

RC136
RC137
RC126

1
1
1

@
@
@

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

M60
L59

XDP_TDI_R
XDP_TDO_R

RC50
RC92

1
1

@
@

2 0_0402_5%
2 0_0402_5%

XDP_TDI
XDP_TDO

+3VS
RC42

XDP_DBRESET#_R

DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

K58 XDP_DBRESET#_R RC89

G58
E55
E59
G55
G59
H60
J59
J61

2 0_0402_5%

XDP_DBRESET#

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

RC95
RC91
RC101
RC102
RC103
RC97
RC88
RC87

1
1
1
1
1
1
1
1

@
@
@
@
@
@
@
@

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

RC90
RC96
RC93
RC94

1
1
1
1

@
@
@
@

2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

XDP_DBRESET#

XDP_DBRESET#_R

<15>

1K_0402_5%

1
CC144
0.1U_0402_25V6K

1
VCCPWRGOOD_0_R
10K_0402_5%

2
RC45

Place close to CPU

Avoid stub in the PWRGD path


while placing resistors RC25 & RC130

CFG12
CFG13
CFG14
CFG15

<8>
<8>
<8>
<8>

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(2/6) PM,XDP,CLK
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

of

57

UC1C

UC1D
<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

<11>
<11>
<11>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

<11>
<11>
<11>

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

i5R1@

DDR_A_D[0..63]

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

DDR SYSTEM MEMORY A

<11>

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AU36
AV36
AY26

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

AT40
AU40
BB26

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

BB40
BC41

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

AY40
BA41

M_ODT0
M_ODT1

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

M_CLK_DDR1
<11>
M_CLK_DDR#1
<11>
DDR_CKE1_DIMMA
<11>

M_ODT0
M_ODT1

<11>
<11>

<11>
<11>

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

i5R1@

DDR_B_D[0..63]

M_CLK_DDR0
<11>
M_CLK_DDR#0
<11>
DDR_CKE0_DIMMA
<11>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

<11>

<11>

<11>

<12>
<12>
<12>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<12>
<12>
<12>

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

DDR SYSTEM MEMORY B

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

BA34
AY34
AR22

M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB

BA36
BB36
BF27

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

BE41
BE47

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AT43
BG47

M_ODT2
M_ODT3

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2
<12>
M_CLK_DDR#2
<12>
DDR_CKE2_DIMMB
<12>

M_CLK_DDR3
<12>
M_CLK_DDR#3
<12>
DDR_CKE3_DIMMB
<12>

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

<12>
<12>

<12>
<12>

DDR_B_DQS#[0..7]

<12>

DDR_B_DQS[0..7]

<12>

DDR_B_MA[0..15]

<12>

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

+1.5V

1
2
@
RC107
0_0402_5%
QC2

RC108
1K_0402_5%

H_DRAMRST#

H_DRAMRST#

<6>

BSS138_SOT23

DDR3_DRAMRST#

DDR3_DRAMRST#_R
RC110

2
1K_0402_5%

DDR3_DRAMRST#

<11,12>

2
1
RC111

RC109
4.99K_0402_1%

2
@
0_0402_1%

DRAMRST_CNTRL_PCH

@
CC145
0.1U_0402_25V6K

<14>
Place close to RC110

DRAMRST_CNTRL

DRAMRST_CNTRL

<11>

CC37
.047U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(3/6) DDRIII
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

of

57

CFG Straps for Processor


D

CFG2

RC116
1K_0402_1%

1
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE

H43
K43

VCC_VAL_SENSE
VSS_VAL_SENSE

@
RC123
50_0402_1%

H45
K45

VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

RC21

@
RC120
50_0402_1%

TP_VCC_DIESENSE
1K_0402_5%

PAD~D
PAD~D

T46@
T36@

PAD~D

T32 @

PAD~D
PAD~D

T34 @
T35 @

PAD~D

T40 @

PAD~D

T42 @

PAD~D
PAD~D

T47 @
T71 @

PAD~D
PAD~D
PAD~D
PAD~D

T72
T51
T68
T49

@
@
@
@

F48
H48
K48
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

VCC_DIE_SENSE

@ T14
@ T15
@ T16
@ T17

PAD~D
PAD~D
PAD~D
PAD~D

M13
M14
U14
W14
P13

@ T22
@ T21
@ T19
@ T20
@ T18

PAD~D
PAD~D
PAD~D
PAD~D
PAD~D

AT49
K24

@ T23

PAD~D

AH2
AG13
AM14
AM15

@ T28
@ T27
@ T25
@ T26

PAD~D
PAD~D
PAD~D
PAD~D

N50

@ T29

PAD~D

1:(Default) Normal Operation; Lane #


definition matches socket pin map definition

CFG2
@

RC117
1K_0402_1%

* 0:Lane Reversed

RC115
1K_0402_1%

CFG4
RC112
1K_0402_1%

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

Display Port Presence Strap

* 1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is


connected to the Embedded Display Port

RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

N42
L42
L45
L47

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

TP_DC_TEST_A4

@ T121 PAD~D

DC_TEST_C4_D3
TP_DC_TEST_D1
TP_DC_TEST_A58

@ T118 PAD~D
@ T119 PAD~D

CFG6
CFG5

DC_TEST_A59_C59
DC_TEST_A61_C61
TP_DC_TEST_D61
TP_DC_TEST_BD61

PAD~D
PAD~D

RSVD30
RSVD31
RSVD32
RSVD33

PEG Static Lane Reversal - CFG2 is for the 16x

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

RSVD28
RSVD29

RC114
1K_0402_1%
@ T120 PAD~D
@ T122 PAD~D

RC113
1K_0402_1%
@

@
RC119
50_0402_1%

@
RC121
50_0402_1%

<6>
<6>
<6>
<6>
<6>
<6>

+VCC_GFXCORE_AXG

PAD~D
PAD~D

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

+SA_DIMM_VREFDQ

+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ

+VCC_CORE

+SA_DIMM_VREFDQ

BE7
BG7

PAD~D

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

PAD~D

CFG0
T91 @
CFG2
T92 @
CFG4
CFG5
CFG6
CFG7
T66 @
T41 @
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
T69 @
T89 @

CFG0

RESERVED

<6>

i5R1@

UC1E

DC_TEST_BE59_BE61
DC_TEST_BG59_BG61
TP_DC_TEST_BG58
TP_DC_TEST_BG4

@ T132 PAD~D
@ T123 PAD~D

DC_TEST_BE3_BG3
DC_TEST_BE1_BG1
TP_DC_TEST_BD1

PCIE Port Bifurcation Straps


@ T124 PAD~D

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

* 10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

@
RC118
1K_0402_1%

CFG7

PEG DEFER TRAINING

CFG7

* 1: (Default) PEG Train immediately


following xxRESETB de assertion

0: PEG Wait for BIOS for training

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(4/6) RSVD,CFG
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

of

57

UC1F i5R1@

POWER

+VCCP

+VCC_CORE

8.5A

VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

Iccmax current changed for PDDG Rev0.7

CPU Power Rail Table


Voltage Rail

Voltage

VCC

0.65-1.3

VCCIO
VAXG

53

1.05/1

8.5

0.0-1.1

33

1.8

1.2

VDDQ

1.5

VCCSA

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

S0 Iccmax
Current (A)

VCCPLL

+1.5V_MEM

+VCCP

VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

0.65-0.9

1.5

12-16

Description

5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT

+3VS

VCCP_PWRCTRL Pull high on power side

W16
W17

VCCIO50
VCCIO51

RC141
10K_0402_5%

VCCIO_SEL

BC22

1
@ RC140

2
VCCP_PWRCTRL
0_0402_5%
+VCCP

+VCCP

RC147
130_0402_1%

RC145
75_0402_5%

A44
B43
C44

RC142 1
RC146 1
RC144 1

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

<BOM 2
Structure>
43_0402_1%
2 0_0402_1%
@
2 0_0402_1%
@

CAD Note: Place the PU


resistors close to CPU
RC147 close to CPU 300~1500mils

VR_SVID_ALRT#
<52>
VR_SVID_CLK
<52>
VR_SVID_DAT
<52>
+VCC_CORE

SVID

VIDALERT#
VIDSCLK
VIDSOUT

RC147 close to CPU

Note: Place the PU resistors close to CPU


RC145 close to CPU 300~1500mils
1

VCCPQE[1]
VCCPQE[2]

AM25
AN22

CC573
1U_0402_6.3V6K

QUIET
RAILS

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

CORE SUPPLY

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

PEG IO AND DDR IO

33A
ULV 17W , Max Current
in Turbo Mode or HFM

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

VCCIO_SENSE
VSS_SENSE_VCCIO

RC139 1
RC122 1

VCCSENSE_R
VSSSENSE_R

2
RC98

2 0_0402_1%
2 0_0402_1%

@
@

VCCSENSE
VSSSENSE

+VCCP

AN16
AN17

<52>
<52>

RC131
100_0402_1%

VCCIO_SENSE
<49>
VSSIO_SENSE_R
<49>

1
RC133
AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

1
10_0402_1%

F43
G43

VCC_SENSE
VSS_SENSE

SENSE LINES

RC138
100_0402_1%

2
10_0402_1%

Place RC98 close to CPU

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(5/6) PWR,BYPASS
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

of

57

+1.5V_CPU_VDDQ Source

RUN_ON_CPU1.5VS3#
@
CC40
0.1U_0402_10V7K~D

UC1G

<35,6>
i5R1@

33A

1
2

1 0.1U_0402_10V7K~D

CC150

1 0.1U_0402_10V7K~D

VREF
- 1.5V RAILS
DDR3

1
+

1U_0402_6.3V6K
CC259

1U_0402_6.3V6K
CC258

CC167

1U_0402_6.3V6K
CC257

330U_D2_2VM_R6M~D

1U_0402_6.3V6K
CC256

CC166
10U_0603_6.3V6M

1U_0402_6.3V6K
CC255

1U_0402_6.3V6K
CC254

1U_0402_6.3V6K
CC253

CC165
10U_0603_6.3V6M

+1.5V

CC164
10U_0603_6.3V6M

CC163
10U_0603_6.3V6M

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

1U_0402_6.3V6K
CC252

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VCCPLL[1]
VCCPLL[2]
VCCPLL[3]

VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]

QUIET RAILS
SENSE LINES

2
1
2

1 0.1U_0402_10V7K~D

CC149

6A
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

CC162
10U_0603_6.3V6M

6A

1U_0402_6.3V6K
CC260

1U_0402_6.3V6K
CC261

BB3
BC1
BC4

CC175
1U_0402_6.3V6K

1U_0402_6.3V6K
CC262

CC174
1U_0402_6.3V6K

1U_0402_6.3V6K
CC263

1U_0402_6.3V6K
CC264

10U_0603_6.3V6M
CC183

10U_0603_6.3V6M
CC168

10U_0603_6.3V6M
CC169

10U_0603_6.3V6M
CC170

10U_0603_6.3V6M
CC171

330U_D2_2VM_R6M~D
CC172

1 0.1U_0402_10V7K~D

1U_0402_6.3V6K
CC251

VAXG_SENSE
VSSAXG_SENSE

1.2A
CC176

330U_D2_2.5VM_R6M~D

+VCCSA

CC179

CC161
10U_0603_6.3V6M

+1.8VS

CC178

+1.5V_CPU_VDDQ

VCCDQ[1]
VCCDQ[2]

AM28
AN26
1

VDDQ_SENSE
VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

CC574
1U_0402_6.3V6K

F45
G45

RC100
100_0402_1%

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

+1.5V_CPU_VDDQ

VCC_AXG_SENSE
VSS_AXG_SENSE

+V_SM_VREF should
have 10 mil trace width

5A

@
RC76
100_0402_1%
2
1

RC99
100_0402_1%

+V_SM_VREF_CNT

RC78
1K_0402_1%

AY43

CC180
10U_0603_6.3V6M

SM_VREF
VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]

1U_0402_6.3V6K
CC250

+VCC_GFXCORE_AXG

RC81
1K_0402_1%

i5R1@

+V_SM_VREF_CNT

CC181
10U_0603_6.3V6M

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

+VCC_GFXCORE_AXG

UC1H

POWER

VCCSA VID
lines

<52>
<52>

RC84
1K_0402_1%

@ QC5
NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

1.8V RAIL

SA RAIL

RC148
0_0402_1%

2
0_0402_5%

GRAPHICS

CPU1.5V_S3_GATE

RC80
1K_0402_1%

SENSE
LINES

<40>

SUSP#

QC7A
2N7002DW-7-F_SOT363-6

+1.5V_CPU_VDDQ

1
@ RC134

<35,40,48,49,50>

RC149
0_0402_5%
1
2
@

+V_DDR_SMREF

RC150
2M_0402_5%~D

+1.5V

2
3

RUN_ON_CPU1.5VS3#

1
1
2

RUN_ON_CPU1.5VS3
CC39
0.1U_0603_50V_X7R

QC7B
2N7002DW-7-F_SOT363-6

1
2
3

RC151
470K_0402_5%

RC143
100K_0402_5%

+1.5V_CPU_VDDQ

8
7
6
5

RC152
20K_0402_5%

QC3
AO4304L_SO8

B+_BIAS

CC38
10U_0805_10V6K

+1.5V
+3VALW

BC43
BA43

U10

VCCSA_SENSE

<51>

D48
D49

VCCSA_VID0
VCCSA_VID1

<51>
<51>

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

VSS

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PROCESSOR(6/6) PWR,VSS
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

10

of

57

+1.5V

+1.5V
JDIMM1

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2

All VREF traces should


have 10 mil trace width

Layout Note:
Place near JDIMM1

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

+1.5V
DDR_A_D26
DDR_A_D27

CD6

CD5

1U_0402_6.3V6K

CD4

1U_0402_6.3V6K

1U_0402_6.3V6K

CD3

1U_0402_6.3V6K

<7>

DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

2
<7>

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
+1.5V

1
+

CD14
220U_2V_D2

M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

<7>

DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

<7>
<7>

DDR_A_WE#
DDR_A_CAS#

<7>
<7>

CD13

10U_0603_6.3V6M
CD12

10U_0603_6.3V6M
CD11

10U_0603_6.3V6M
CD10

10U_0603_6.3V6M
CD9

10U_0603_6.3V6M
CD8

10U_0603_6.3V6M
CD7

10U_0603_6.3V6M

DDR_A_MA3
DDR_A_MA1

<7>

DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#

DDR_CS1_DIMMA#

DDR_A_D42
DDR_A_D43

+0.75VS

DDR_A_D48
DDR_A_D49

DDR_A_D50
DDR_A_D51

DDR_A_D58
DDR_A_D59

+0.75VS

205

G1

G2

DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

<7>

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1
<7>
M_CLK_DDR#1
<7>

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 <7>
DDR_A_RAS#
<7>

DDR_CS0_DIMMA#
M_ODT0

DDR_CS0_DIMMA#
M_ODT0 <7>

M_ODT1

M_ODT1

+1.5V

<7>

RD4
1K_0402_1%

<7>
+VREF_CA

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

RD5
1K_0402_1%

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
@ RD8

M3

DDR_A_D54
DDR_A_D55

2 0_0402_5%
QD1
1 BSS138_NL_SOT23-3

+SA_DIMM_VREFDQ

DDR_A_D60
DDR_A_D61

+V_DDR_REFA

DDR_A_DQS#7
DDR_A_DQS7

<7>

DRAMRST_CNTRL

DRAMRST_CNTRL

DDR_A_D62
DDR_A_D63
@ RD9
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <12,14,38,6>
PCH_SMBCLK <12,14,38,6>

+0.75VS

2 0_0402_5%
QD2
1 BSS138_NL_SOT23-3

+SB_DIMM_VREFDQ

+V_DDR_REFB

206
G

2
10K_0402_5%
2
10K_0402_5%

DDR_A_D28
DDR_A_D29

1
RD6
1
RD7

DDR_A_D22
DDR_A_D23

CD21

CD22
2.2U_0603_6.3V6K

0.1U_0402_16V7K

+3VS

DDR_A_D20
DDR_A_D21

DDR_A_D56
DDR_A_D57

<12,7>

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

CD20
1U_0402_6.3V6K

CD19
1U_0402_6.3V6K

CD18
1U_0402_6.3V6K

CD17
1U_0402_6.3V6K

DDR_A_DQS#6
DDR_A_DQS6

DDR3_DRAMRST#

CD16

DDR_A_D40
DDR_A_D41

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D12
DDR_A_D13

CD15

DDR_A_D34
DDR_A_D35

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A_D6
DDR_A_D7

0.1U_0402_16V7K

DDR_A_DQS#4
DDR_A_DQS4

Layout Note:
Place near JDIMM1.203,204

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_DQS#0
DDR_A_DQS0

2.2U_0603_6.3V6K

DDR_A_D32
DDR_A_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_D4
DDR_A_D5

DDR_A_DQS#1
DDR_A_DQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D8
DDR_A_D9
RD3
1K_0402_1%

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

DDR_A_D2
DDR_A_D3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+V_DDR_REFA

DDR_A_MA[0..15]

DDR_A_D0
DDR_A_D1

1
CD2

DDR_A_D[0..63]

<7>

1
CD1

<7>

RD1
1K_0402_1%

0.1U_0402_16V7K

DDR_A_DQS[0..7]

2.2U_0603_6.3V6K

<7>
D

+V_DDR_REFA

+V_DDR_REFA

+1.5V

DDR_A_DQS#[0..7]

<7>

BELLW_80001-5021
CONN@

DRAMRST_CNTRL

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

SP07000LZ00
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DDRIII DIMMA
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

11

of

57

+1.5V

DDR_B_D8
DDR_B_D9

<7>

DDR_B_D[0..63]

<7>

DDR_B_MA[0..15]

DDR_B_DQS#1
DDR_B_DQS1
RD16
1K_0402_1%

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

<7>

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19

All VREF traces should


have 10 mil trace width

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

Layout Note:
Place near JDIMMB
<7>

DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

<7>

DDR_B_BS2

DDR_B_BS2

+1.5V

DDR_B_MA8
DDR_B_MA5

CD31

CD30

1U_0402_6.3V6K

CD29

1U_0402_6.3V6K

1U_0402_6.3V6K

CD28

1U_0402_6.3V6K

DDR_B_MA12
DDR_B_MA9

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

<7>

DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

<7>
<7>

DDR_B_WE#
DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

<7>
<7>

+1.5V
<7>

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

Layout Note:
Place near JDIMMB.203,204

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

+0.75VS

+3VS
+0.75VS

205
207
CD47

CD46

2.2U_0603_6.3V6K

0.1U_0402_16V7K

RD20
10K_0402_5%

RD19
10K_0402_5%

+3VS

CD45
1U_0402_6.3V6K

CD44
1U_0402_6.3V6K

CD43
1U_0402_6.3V6K

CD42
1U_0402_6.3V6K

DDR_B_D58
DDR_B_D59

GND1
BOSS1

GND2
BOSS2

DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#

DDR3_DRAMRST#

<11,7>

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

<7>

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3
<7>
M_CLK_DDR#3
<7>

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 <7>
DDR_B_RAS#
<7>

DDR_CS2_DIMMB#
M_ODT2

DDR_CS2_DIMMB#
M_ODT2 <7>

M_ODT3

M_ODT3

+1.5V

<7>

RD17
1K_0402_1%

<7>
+VREF_CB

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

RD18
1K_0402_1%

CD41

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D6
DDR_B_D7

CD40

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

DDR_B_DQS#0
DDR_B_DQS0

0.1U_0402_16V7K

DDR_B_D32
DDR_B_D33

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_B_D4
DDR_B_D5

2.2U_0603_6.3V6K

DDR_CS3_DIMMB#

CD39
220U_2V_D2

CD38

10U_0603_6.3V6M
CD37

10U_0603_6.3V6M
CD36

10U_0603_6.3V6M
CD35

10U_0603_6.3V6M
CD34

10U_0603_6.3V6M
CD33

10U_0603_6.3V6M
CD32

10U_0603_6.3V6M

DDR_B_MA13
DDR_CS3_DIMMB#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_B_D2
DDR_B_D3

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

DDR_B_D0
DDR_B_D1

1
CD26

CD27

RD15
1K_0402_1%
+V_DDR_REFB

0.1U_0402_16V7K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+V_DDR_REFB

+V_DDR_REFB
2.2U_0603_6.3V6K

<7>

+1.5V
JDIMM2

+1.5V

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PCH_SMBDATA
PCH_SMBCLK

PCH_SMBDATA <11,14,38,6>
PCH_SMBCLK <11,14,38,6>

+0.75VS

206
208

BELLW_80001-1021
CONN@

SP07000P700
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DDRIII DIMMB
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

12

of

57

+3VS

PCH_RTCX1
XTAL@

2
10M_0402_5%
YH1
2

PCH_RTCX2

+RTCVCC

close to YH1
32.768KHZ_12.5PF_9H03200019
XTAL@

CH1

<23>

PCH_RTCX1_R

18P_0402_50V8J

2
PCH_RTCX1
0_0402_5%

RH30

CH3
XTAL@

PCH_INTVRMEN RH13

PCH_INTVRMEN RH16

330K_0402_5%
1

RH10

1 10K_0402_5%

HDD_DET#

RH12

1 10K_0402_5%

PCH_SATALED#RH14

1 10K_0402_5%

CH2

HDA_SDOUT
10P_0402_50V8J

GCLK@

SERIRQ

HDA_BIT_CLK
10P_0402_50V8J

UH1

R3@

* LH
Integrated
Integrated

+3VS

330K_0402_5%

INTVRMEN

CH4 XTAL@
18P_0402_50V8J

+RTCVCC

2
RH2

Reserve for RF please close to UH1

2
1M_0402_5%

SM_INTRUDER#

VRM enable
VRM disable

SA00005FH2L

L34

HDA_SPKR

T10

HDA_RST#

K34

HDA_SDIN0

HDA_SDIN0

E34
G34
C34
A34

<40>

ME_EN

2
HDA_SDOUT
1K_0402_1%

RH11

A36

HDA_SDOUT
<33>

HDA_SDOUT_AUDIO

2
HDA_SDOUT
33_0402_5%

RH15

C36
N32

RH24
100_0402_1%

J3

PCH_JTAG_TMS_R

H7

PCH_JTAG_TDI_R

K5

PCH_JTAG_TDO_R

H1

PCH_JTAG_TMS

<6>

PCH_JTAG_TDI

<6>

PCH_JTAG_TDO

LPC

HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0

PCH_JTAG_TCK
PCH_JTAG_TMS

RH44
PCH_JTAG_TDI
RH48
PCH_JTAG_TDO

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

HDA_SDO
HDA_DOCK_EN# / GPIO33

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

HDA_DOCK_RST# / GPIO13
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

JTAG_TCK
JTAG_TMS
JTAG_TDI

SATAICOMPO
SATAICOMPI

JTAG_TDO
SATA3COMPI

2
PCH_JTAG_TCK

<6>

HDA_BCLK

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA3RCOMPO

PCH_SPI_CLK

T3

PCH_SPI_CS0#

Y14

PCH_SPI_CS1#

T1

<6>

SERIRQ

PCH_JTAG_TDI_R
RH26
100_0402_1%

RH25
100_0402_1%

PCH_JTAG_TCK

INTVRMEN

PCH_JTAG_TMS_R

PCH_JTAG_TDO_R

@
RH20
200_0402_1%

@
RH19
200_0402_1%

@
RH18
200_0402_1%

+3V_PCH

+3V_PCH

+3V_PCH

INTRUDER#

LDRQ0#
LDRQ1# / GPIO23

RH70

PCH_SPI_SI

V4

PCH_SPI_SO

U3

PCH_JTAG_TMS_R
0_0402_5%
PCH_JTAG_TDI_R
0_0402_5%
2
PCH_JTAG_TDO_R
0_0402_5%

SPI_CLK

SATA3RBIAS

D36

LPC_FRAME#

LPC_FRAME#

V5

SERIRQ

SERIRQ

1
1

<40>

<40>

HDA_SYNC

SATA_PRX_DTX_N0 <41>
SATA_PRX_DTX_P0 <41>
SATA_PTX_DRX_N0_C <41>
SATA_PTX_DRX_P0_C <41>

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

This signal has a weak internal pull-down


On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom

HDD

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

<41>
<41>
<41>
<41>

HDA_SYNC

ODD

1
1K_0402_5%

RH32

AB8
AB10
AF3
AF1

RTC Battery

Y7
Y5
AD3
AD1

+RTCBATT

Y3
Y1
AB3
AB1

1
RH21

2
37.4_0402_1%

1
SATA3_COMP
RH22

2
49.9_0402_1%

1
RBIAS_SATA3
RH28

2
750_0402_1%~D

SATA_COMP

W=20mils

+1.05VS_SATA3

AB12
AB13
AH1

RH34
1K_0402_5%

+CHGRTC

+1.05VS_VCC_SATA

Y11
Y10

SATALED#
SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

P3

PCH_SATALED#

V14

HDD_DET#_R

P1

BBS_BIT0_R

@
RH268 1

2
RH29

W=20mils
DH1
BAT54CW_SOT323-3

JP12

+CHGRTC

+3VLP

JUMP_43X39

+RTCVCC
W=20mils 1

SPI_MOSI

+3V_PCH
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SPI_CS0#
SPI_CS1#

1 1K_0402_5%

= Disabled
*Low
High = Enabled

H=>Flash Descriptor Security will be overridden

AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4

HDA_SDOUT RH23

L=>security measures defined in the Flash


Descriptor will be in effect (default)

E36
K36

AM3
AM1
AP7 SATA_PTX_DRX_N0 CH7
AP5 SATA_PTX_DRX_P0 CH8

+3V_PCH

ME debug mode , this signal has a weak internal PD

<40>
<40>
<40>
<40>

N34

HDA_SYNC

FWH4 / LFRAME#
SRTCRST#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

HDA_SPKR

HDA_BIT_CLK

RTCRST#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

K22
C17

RTCX2

RTC

G22

HDA_SYNC

<33>
QH1 BSS138_SOT23
1
2
@
RH9
0_0402_5%

2
1M_0402_5%

RH8

D20

PCH_SRTCRST#

HDA_SDO

C38
A38
B37
C37

<33>

PCH_RTCRST#

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

SATA 6G

RH7

2
HDA_SYNC_R
33_0402_5%

C20

SATA

2
HDA_RST#
33_0402_5%

PCH_RTCX2

RTCX1

IHDA

HDA_SYNC_AUDIO

RH6

A20

SPI

<33>

HDA_RST_AUDIO#

PCH_RTCX1

SM_INTRUDER#
CLRP2
PCH_INTVRMEN
SHORT PADS
ME CMOS
CLP1 & CLP2 place near DIMM

+5VS

<33>

2
HDA_BIT_CLK
33_0402_5%

RH5

HDA_BITCLK_AUDIO

<33>

CMOS
CLRP1
SHORT PADS

JTAG

CH6
1U_0603_10V6K

CH5
1U_0603_10V6K
1
2
RH3 20K_0402_5%
1
2
RH4 20K_0402_5%

+RTCVCC

UH1A

keep away hot spot

1 1K_0402_5%

LOW=Default
*HIGH=No Reboot

SA00005FH1L

R1@

HDA_SPKR RH17

BD82HM76-SLJ8E-C1_BGA989~D

1
RH1

PCH_SATALED#

2 0_0402_1%
1 10K_0402_5%

<38>
HDD_DET#

HDD_DET#

CH12
1U_0603_10V6K

<41>

+3VS

BD82HM76-SLJ8E-C1_BGA989~D

+3V_PCH
+3V_PCH
+3V_PCH

2
51_0402_5%

PCH_SPI_CS1#
PCH_SPI_SO

1
RH38

2 PCH_SPI_WP#
3.3K_0402_5%

1
RH40

2 PCH_SPI_HOLD#
3.3K_0402_5%

SPI ROM FOR WIN8( 2MByte )

@
RH263
3.3K_0402_5%

1
RH35

+3V_PCH

PCH_JTAG_TCK

@
RH33
3.3K_0402_5%

@
1 RH36
2 RH37

UH2

2 0_0402_1%
1 33_0402_5%

PCH_SPI_CS1#_R
PCH_SPI_SO_R
PCH_SPI_WP#

1
2
3
4

CS#
SO
WP#
GND

PCH_SPI_CS0#
PCH_SPI_SO

X76@

VCC
HOLD#
SCLK
SI

8
7
6
5

PCH_SPI_HOLD#
PCH_SPI_CLK_R
PCH_SPI_SI_R

2 RH27
2 RH39

133_0402_5%
133_0402_5%

@
1 RH264
2
RH265

SPI ROM FOR ME


( 4MByte )
UH6

2 0_0402_1%
1
33_0402_5%

PCH_SPI_CS0#_R 1
PCH_SPI_SO_L 2
3
PCH_SPI_WP#
4

PCH_SPI_CLK
PCH_SPI_SI

EON
EN25QH16-104HIP_SO8
ZZZ

SPIEON@

ZZZ

SPIWB@

CH99
10P_0402_50V8J

ZZZ SPIMXIC@

X7644031L08

PCH_SPI_HOLD#
PCH_SPI_CLK_L
PCH_SPI_SI_L

2 RH266
2
RH267

2012/08/22

Deciphered Date

Compal Electronics, Inc.


2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

X7644031L09

Date:

133_0402_5% PCH_SPI_CLK
1
PCH_SPI_SI
33_0402_5%

Compal Secret Data

Security Classification
Issued Date

X7644031L07

VCC
HOLD#
SCLK
SI/SIO0

8
7
6
5

EON
EN25Q32B-104HIP_SO8

1
@

X76@

EN25Q32B-104HIP_SO8

EN25QH16-104HIP_SO8

CS#
SO/SIO1
WP#
GND

CH98

0.1U_0402_16V7K

CH11
@
RH262
3.3K_0402_5%

+3V_PCH

0.1U_0402_16V7K

+3V_PCH

NEC flash issue.

PCH (1/8) SATA/HDA/SPI/LPC


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

13

of

57

1
RH45
1
RH46
1
SML0CLK
RH47
1
SML0DATA
RH49
1
SML1CLK
RH50
1
SML1DATA
RH51
1
SMBALERT#
RH52
1
PCH_HOT#
RH86
1
DRAMRST_CNTRL_PCH
RH53
SMBCLK

UH1B

J2

LAN_CLKREQ#
RH75 1
RH76 1
RH77 2

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
+3VS
WLAN_CLKREQ#

@
@

2 0_0402_1%
2 0_0402_1%
1 10K_0402_5%

AB49
AB47

PCIE_WLAN#
PCIE_WLAN
WLAN_CLKREQ#

M1
AA48
AA47

RH79 2

+3VS

1 10K_0402_5%

GPIO20

V10
Y37
Y36

RH74 2

+3V_PCH

GPIO25

A8
Y43
Y45

RH66 1

+3V_PCH

2 10K_0402_5%

GPIO26

L12

RH83 1

2 10K_0402_5%

GPIO44

+3V_PCH

RH84 1

2 10K_0402_5%

GPIO56

L14
AB42
AB40
E6
V40
V42

RH88 1

+3V_PCH

2 10K_0402_5%

GPIO45

T13
V38
V37

RH90 1

+3V_PCH

M7

RH91 1
RH92 1

CLK_CPU_ITP#
CLK_CPU_ITP

@
@

2 10K_0402_5%
2 0_0402_1%
2 0_0402_1%

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

P10

PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P

CLKIN_GND1_N
CLKIN_GND1_P

PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4# / GPIO26

M10

PEG_A_CLKRQ#

AB37
AB38

CLK_PEG_VGA#
CLK_PEG_VGA

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

+3VS

PEG_A_CLKRQ#

RH71
2.2K_0402_5%

CLK_CPU_DMI#
CLK_CPU_DMI

<6>
<6>

SMBCLK

BF18
BE18

CLKIN_DMI#
CLKIN_DMI

BJ30
BG30

CLKIN_DMI2#
CLKIN_DMI2

G24
E24

CLKIN_DOT96#
CLKIN_DOT96

AK7
AK5

CLKIN_SATA#
CLKIN_SATA

PCH_SMBCLK

SMBDATA

K12
AK14
AK13

CLKOUT_PCIE5N
CLKOUT_PCIE5P

REFCLK14IN

K45

CLK_PCH_14M

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

PCH_SMBCLK

RH41

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_14M_R

CLK_PCI_LPBACK

XTAL@

1
RH85

2
90.9_0402_1%

2
0_0402_1%
2
0_0402_1%

CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBCLK

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

TP_SMBCLK
TP_SMBDATA

+3VS

RH80
2.2K_0402_5%

+1.05VS_VCCDIFFCLKN

PCIECLKRQ6# / GPIO45

H47
K49

T53

PAD~D

1 RH125 2
@ T54
22_0402_5%
2
CLK_LAN_25M_R
@ 1
RH270
22_0402_5%
1
DGPU_PRSNT# 2
+3VS
RH269 10K_0402_5%
UMA@

PAD~D

<32>

TP_SMBCLK

DMN66D0LDW-7_SOT363-6
@
QH7A

CLK_LAN_25M

RH81
2.2K_0402_5%

SMBDATA

<39>

TP_SMBDATA

<39>

DMN66D0LDW-7_SOT363-6
@
QH7B

RH261
10K_0402_5%

+3V_PCH

@
@
CH25
RH63
22P_0402_50V8J
2
1
1
2
33_0402_5%

close to RH270
SML1CLK
<23>

LAN_X1

2
CLK_LAN_25M
0_0402_5%

PCH_SMLCLK

<40>

DMN66D0LDW-7_SOT363-6
QH3A

GCLK@

Reserve for EMI please close to


UH1

CH28
12P_0402_50V8J
XTAL@

1
RH31

SML1DATA

PCH_SMLDATA

<40>

DMN66D0LDW-7_SOT363-6
QH3B

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CLKOUT_PCIE6N
CLKOUT_PCIE6P

@
CH26
@
22P_0402_50V8J
RH65
1
1
2
CLK_PCI_LPBACK 2
33_0402_5%

<16>

XTAL25_OUT

1
OSC

OSC
GND

GND

YH2

1
RH87

PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP

<11,12,38,6>

25MHZ_10PF_7V25000014

XTAL@

PCH_SMBDATA

QH2B
RH82
1 @
2
0_0402_5%

+3VS

PCIECLKRQ5# / GPIO44

<11,12,38,6>

DMN66D0LDW-7_SOT363-6

PCH_SMBDATA

DIS@

XTAL25_IN

CH27
12P_0402_50V8J

RH72
2.2K_0402_5%

DMN66D0LDW-7_SOT363-6
QH2A
RH78
1 @
2
0_0402_5%

XTAL@

+3VS

<25>

CLK_PEG_VGA# <24>
CLK_PEG_VGA <24>

AM12
AM13

2
XTAL25_IN
0_0402_5%

CLK_PCH_14M

1
1M_0402_5%

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

GCLK@

2
RH89

2
2
2
2
2
2
2
2
2

No support iAMT

BD82HM76-SLJ8E-C1_BGA989~D
R1@

PCH_X1

1
1
1
1
1
1
1
1
1

If use extenal CLK gen, please place close to CLK gen


else, please place close to PCH

+3V_PCH

T11

RH64
10K_0402_5%

close to YH2
<23>

20090512
add double mosfet prevent
ATI M92 electric leakage

RH54
RH55
RH56
RH57
RH58
RH59
RH60
RH61
RH62

+3V_PCH

CLK_CPU_ITP#
CLK_CPU_ITP

CL_RST1#

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

RH93

V45
V46

<6>
<6>

PERN8
PERP8
PETN8
PETP8

CL_CLK1
CL_DATA1

<40>

*PCIE REQ power rail:


suspend: 0 3 4 5 6 7
core: 1 2

1 10K_0402_5%

PERN7
PERP7
PETN7
PETP7

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCH_HOT#

Total device

PERN6
PERP6
PETN6
PETP6

PCIECLKRQ0# / GPIO73

SML1DATA

Y40
Y39

PCIE_LAN#
PCIE_LAN

SML1CLK

M16

<38>

2 0_0402_1%
2 0_0402_1%
1 10K_0402_5%

PCH_HOT#

E14

<7>

<38>
<38>

@
@

C13

DRAMRST_CNTRL_PCH

<32>

WLAN (Mini Card)--->

RH67 1
RH68 1
2
RH69

CLK_PCIE_LAN#
CLK_PCIE_LAN
+3V_PCH
LAN_CLKREQ#

SML0DATA

<32>
<32>

10/100 LAN --->

SML1DATA / GPIO75

SML0CLK

G12

SML1CLK / GPIO58

DRAMRST_CNTRL_PCH

C8

BE38
BC38
AW38
AY38

SML1ALERT# / PCHHOT# / GPIO74

A12

MEMORY

BG40
BJ40
AY40
BB40

SML0CLK
SML0DATA

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

SML0ALERT# / GPIO60

SMBDATA

BJ38
BG38
AU36
AV36

PERN3
PERP3
PETN3
PETP3

SMBCLK

C9

BG37
BH37
AY36
BB36

SMBDATA

SMBALERT#

H14

BF36
BE36
AY34
BB34

PERN2
PERP2
PETN2
PETP2

E12

+3V_PCH

BG36
BJ36
AV34
AU34

SMBCLK

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
1K_0402_5%

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

SMBUS

CH21 1
CH22 1

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C

PERN1
PERP1
PETN1
PETP1

Link

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D

Controller

<38>
<38>
<38>
<38>

CH19 1
CH20 1

FLEX CLOCKS

WLAN (Mini Card)--->

PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1

CLOCKS

<32>
<32>
<32>
<32>

BG34
BJ34
AV32
AU32

PCI-E*

10/100 LAN --->

PCIE_PRX_LANTX_N1
PCIE_PRX_LANTX_P1
PCIE_PTX_LANRX_N1_C
PCIE_PTX_LANRX_P1_C

SMBDATA

PCH (2/8) PCIE/SMBUS/CLK


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

14

of

57

UH1C

<5>
<5>
<5>
<5>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

<5>
<5>
<5>
<5>

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

<5>
<5>
<5>
<5>

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT

+1.05VS

BJ24
1
RH99

2
DMI_IRCOMP
49.9_0402_1%
2
RBIAS_CPY
750_0402_1%~D

1
RH100

Reserve for ESD

BH21

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0

4mil width and place


within 500mil of the PCH

FDI_LSYNC1

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>

AW16

FDI_INT

AV12

FDI_FSYNC0

FDI_INT

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

UH1D

<21>

DSWVRMEN

<6>

C12

PAD~D T57

2 SYS_PWROK_R P12
0_0402_1%

SYS_PWROK

2
0_0402_1%

L22

PWROK

2
0_0402_1%

L10

RH106

B13

PM_DRAM_PWRGD

PM_DRAM_PWRGD
EC_RSMRST#

2PCH_RSMRST#_R C21
0_0402_1%

2
0_0402_1%

RH108

K16

SUSWARN#
Reserve for ESD
PBTN_OUT#

<40,6>

SYS_RESET#

PCH_PWROK

<40>

SUSACK#

1
SYS_PWROK
RH104
RH105

<6>

K3

XDP_DBRESET#

XDP_DBRESET#

PBTN_OUT#

RH110

E20

System Power Management

Please close to PCH

APWROK
DRAMPWROK
RSMRST#

DPWROK

A18

1
@

WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#

SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#

SLP_S3#
SLP_A#

B9

WAKE#

1
RH103

N3
G8

N14 SUSCLK 1
RH107

T58
@

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

T45
P39

CTRL_CLK
CTRL_DATA
LVDS_IBG
PAD~D

T56

<5>
<5>

FDI_LSYNC0

<5>

FDI_LSYNC1

<5>

AF37
AF36

<21>
<21>

LVDS_ACLKLVDS_ACLK+

<21>
<21>
<21>

LVDS_A0LVDS_A1LVDS_A2-

<21>
<21>
<21>

LVDS_A0+
LVDS_A1+
LVDS_A2+

<21>
<21>

LVDS_BCLKLVDS_BCLK+

<21>
<21>
<21>

LVDS_B0LVDS_B1LVDS_B2-

<21>
<21>
<21>

LVDS_B0+
LVDS_B1+
LVDS_B2+

LVDS_ACLKLVDS_ACLK+

AK39
AK40

LVDS_A0LVDS_A1LVDS_A2-

AN48
AM47
AK47
AJ48

LVDS_A0+
LVDS_A1+
LVDS_A2+

AN47
AM49
AK49
AJ47

LVDS_BCLKLVDS_BCLK+

AF40
AF39

LVDS_B0LVDS_B1LVDS_B2-

AH45
AH47
AF49
AF45

LVDS_B0+
LVDS_B1+
LVDS_B2+

AH43
AH49
AF47
AF43

PCH_RSMRST#_R

PCIE_WAKE#

<32,40>

PM_CLKRUN#
SUS_STAT#

T40
K47

LVDS_DDC_CLK
LVDS_DDC_DATA

AE48
AE47

FDI_FSYNC1

2
@
0_0402_1%
RH128
2
0_0402_5%

VGA_PWM

<21> LVDS_DDC_CLK
<21> LVDS_DDC_DATA

DSWODVREN

E22 PCH_DPWROK

P45

<5>

FDI_FSYNC0

J47
M45

ENBKL
PCH_ENVDD

<40> ENBKL
PCH_ENVDD

<21>

SYS_PWROK_R

0.1U_0402_16V7K

@
CH103
0.1U_0402_16V7K

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

PAD~D

2
0_0402_1%

SUSCLK_R
PM_SLP_S5#

<40>

PM_SLP_S4#

<40>

PM_SLP_S3#

<40>

<40>

N48
P49
T49
CRT_DDC_CLK
CRT_DDC_DATA

M47
M49

DH4
<25,40,45,46>

ACIN

AC_PRESENT_R H20

RB751V-40_SOD323-2
GPIO72

E10

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

G16

PM_SLP_SUS#

AP14

H_PM_SYNC

Place close to PCH

A10

RI#

RI#

SLP_LAN# / GPIO29

T39
M40

G10

K14

BD82HM76-SLJ8E-C1_BGA989~D

T59

PAD~D

H_PM_SYNC

CRT_IREF

<6>

Can be left NC when IAMT is


not support on the platfrom

If not using integrated


LAN,signal may be left as NC.

T43
T42

L_BKLTEN
L_VDD_EN

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

SDVO_STALLN
SDVO_STALLP

L_DDC_CLK
L_DDC_DATA

SDVO_INTN
SDVO_INTP

AP43
AP45
AM42
AM40
AP39
AP40

L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG

SDVO_CTRLCLK
SDVO_CTRLDATA

LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

HDMI

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD

mDP

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

CH105
2

BG25

DMI_ZCOMP

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

Digital Display Interface

BC24
BE20
BG18
BG20

LVDS

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

CRT

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

FDI

<5>
<5>
<5>
<5>

DMI

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

DMC

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

P38
M39

PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA

AT49
AT47
AT40

HDMI_DET

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

HDMI_DET

<22>
<22>

<22>

HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

<22>
<22>
<22>
<22>
<22>
<22>
<22>
<22>

P46
P42
AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

BD82HM76-SLJ8E-C1_BGA989~D
RH115
1K_0402_0.5%

Check EC for S3 S4 LED


+3V_PCH

R1@

R1@
B

GPIO72

RH116 1

2 10K_0402_5%

RI#

RH117 1

PCIE_WAKE#

RH118 1

AC_PRESENT_R

RH121 1

2 200K_0402_5%

DSWODVREN

RH119

SUSWARN#

RH124 1

2 10K_0402_5%

DSWODVREN

RH122

CH29
2
1

SUSCLK

2 10K_0402_5%
@

+RTCVCC

10P_0402_50V8J

2 10K_0402_5%
1 330K_0402_5%

Reserve for RF please close to UH1


RH120

1 330K_0402_5%

1
RH123

RH126 1

WAKE#

RH127 1

EC_RSMRST#

2 10K_0402_5%

2 10K_0402_5%

RH132

1
RH134

1
RH133
1
RH135
1
RH136 @
1
RH137
1
RH138
1
RH233
1
RH234
1
@
RH238
1
@
RH239

+3VS

1
CH30
0.1U_0402_16V7K

PCH_PWROK
VGATE

1
2

IN1
IN2

<52,6>

PCH_PWROK

GND

<40,6>

UH3

VCC

+3VS

DSWODVREN - On Die DSW VR Enable


H Enable
L Disable

OUT

SYS_PWROK

SYS_PWROK

<6>

2
2.2K_0402_5%
2
2.2K_0402_5%
2
8.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

2
10K_0402_5%
2
2.37K_0402_1%
2
100K_0402_5%
2
100K_0402_5%

PM_CLKRUN#
LVDS_IBG
PCH_ENVDD
ENBKL

CTRL_CLK
CTRL_DATA
PM_CLKRUN#
LVDS_DDC_CLK
LVDS_DDC_DATA
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
CRT_DDC_CLK
CRT_DDC_DATA

MC74VHC1G08DFT2G_SC70-5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PCH (3/8) DMI/FDI/PM/GFX/DP


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

15

of

57

+3VS

2 8.2K_0402_5%

PCI_PIRQA#

2 8.2K_0402_5%

PCI_PIRQD#

RH131

2 8.2K_0402_5%

PCI_PIRQB#

RH141

2 8.2K_0402_5%

PCI_PIRQC#

RH142

2 8.2K_0402_5%

GPIO51

RH146

2 8.2K_0402_5%

GPIO5

RH147

2 8.2K_0402_5%

GPIO52

RH148

2 8.2K_0402_5%

WL_OFF#

RH151

2 8.2K_0402_5%

ODD_DA#

UH1E

RH153

2 8.2K_0402_5%

GPIO4

RH154

2 8.2K_0402_5%

PXS_PWREN

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

+3VS

RH140

SSI:
Port 1
Port 2
Port 3

PT:
Port 1
Port 2
Port 3

USB Conn 1
USB Conn 2
USB Conn 3

1 10K_0402_5%

B21
M20
AY16
BG46

DGPU_HOLD_RST#

USB Conn JUSB2


USB Conn JUSB1
Cancel

<36>
<36>

USB3RN1_JUSB2
USB3RN2_JUSB1

<36>
<36>

USB3RP1_JUSB2
USB3RP2_JUSB1

<36>
<36>

USB3TN1_JUSB2
USB3TN2_JUSB1

<36>
<36>

USB3TP1_JUSB2
USB3TP2_JUSB1

USB3RN1_JUSB2
USB3RN2_JUSB1
USB3RP1_JUSB2
USB3RP2_JUSB1
USB3TN1_JUSB2
USB3TN2_JUSB1
USB3TP1_JUSB2
USB3TP2_JUSB1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
<24>

PXS_PWREN

WL_OFF#

D47
E42
F46

ODD_DA#
GPIO4
GPIO5

G42
G40
C42
D44

GPIO51
<38>

Reserve for ESD


CH104
2

<41>

K40
K38
H38
G38

C46
DGPU_HOLD_RST#
C44
GPIO52
E40
PXS_PWREN

DGPU_HOLD_RST#

<26,53>

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

WL_OFF#

ODD_DA#

PCH_PLTRST#

0.1U_0402_16V7K

PAD~D

Please close to PCH

<24>

K10

T60 @
PCH_PLTRST#

PCH_PLTRST#

C6

CLK_PCI_LPBACK
CLK_PCI_LPC

<14> CLK_PCI_LPBACK
<40> CLK_PCI_LPC

CH31
2
1

RH144
RH145

2
1

1 22_0402_5%
2 22_0402_5%
PAD~D T61 @
PAD~D T62 @
PAD~D T63 @

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

CLK_PCI1

H49
H43
J48
K42
H40

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

TP21
TP22
TP23
TP24

RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

RSVD28
RSVD29

USB

RH130

RSVD

RH129

PCI

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS

AY7
AV7
AU3
BG4

AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

*
+1.8VS

@ RH139 1

NV_ALE

2 1K_0402_5%

AT8
AY5
BA2
AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_JUSB2_N0
USB20_JUSB2_P0
USB20_JUSB1_N1
USB20_JUSB1_P1
USB20_JUSB3_N2
USB20_JUSB3_P2
USB20_USBDB_N3
USB20_USBDB_P3

C33

USBRBIAS

USB20_MINI1_N8
USB20_MINI1_P8
USB20_TOUCH_N9
USB20_TOUCH_P9
USB20_CR_N10
USB20_CR_P10
USB20_CAM_N11
USB20_CAM_P11

USB20_JUSB2_N0
USB20_JUSB2_P0
USB20_JUSB1_N1
USB20_JUSB1_P1
USB20_JUSB3_N2
USB20_JUSB3_P2
USB20_USBDB_N3
USB20_USBDB_P3

<36>
<36>
<36>
<36>
<37>
<37>
<37>
<37>

USB20_MINI1_N8
<38>
USB20_MINI1_P8
<38>
USB20_TOUCH_N9
<41>
USB20_TOUCH_P9
<41>
USB20_CR_N10
<34>
USB20_CR_P10
<34>
USB20_CAM_N11
<21>
USB20_CAM_P11 <21>

USB Conn JUSB2


USB Conn JUSB1
USB Conn JUSB3

Mini Card (WLAN)


Touch panel
Card Reader

Within
500 2mils
1
RH143

22.6_0402_1%

+3V_PCH

PME#
PLTRST#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

A14
K20
B17
C16
L16
A16
D14
C14

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

<36>
<36>
<37>
<37>

USB_OC0#

10K_0402_5%

1 RH156

USB_OC1#

10K_0402_5%

1 RH158

USB_OC2#

10K_0402_5%

1 RH160

USB_OC3#

10K_0402_5%

1 RH166

USB_OC6#

10K_0402_5%

1 RH167

USB_OC5#

10K_0402_5%

1 RH170

USB_OC4#

10K_0402_5%

1 RH189

USB_OC7#

10K_0402_5%

1 RH211

2
0_0402_5%

+3VS

@
RH150
10K_0402_5%

CH101
2
0.1U_0402_25V6K

IN1

O
3

IN2

PCH_PLTRST#

SN74AHC1G08DCKR_SC70-5

PLT_RST#

UH5

1
<32,38,40,6>

USB Conn JUSB2


USB Conn JUSB1
USB Conn JUSB3
USB Conn 4 (DB)
Mini Card (WLAN)
Touch panel
Card Reader
Camera

B33

Reserve for RF please close to PCH


1
@
RH149

PT:
Port 0
Port 1
Port 2
Port 3
Port 8
Port 9
Port 10
Port 11

Camera

10P_0402_50V8J

+3VS

USB Conn 1
USB Conn 4 (DB)
USB Conn 2
USB Conn 3
Mini Card (WLAN)
Card Reader
Camera

USB Conn 4 (DB)

BD82HM76-SLJ8E-C1_BGA989~D
R1@

SSI:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 6
Port 12

RH155
100K_0402_5%

RH157
10K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PCH (4/8) PCI/USB/NVRAM


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

16

of

57

UH1F
+3V_PCH

RH241

GPIO6

H36

<40>

EC_SCI#

EC_SCI#

E38

<40>

EC_SMI#

EC_SMI#

C10

EC_LID_OUT#

EC_LID_OUT# 1
RH73

2 PCH_LID_SW_IN#
0_0402_1%

TACH6 / GPIO70

TACH3 / GPIO7

TACH7 / GPIO71

G2

GPIO15

A20GATE
PECI

SATA4GP / GPIO16

PCH_GPIO39

PCH_GPIO38

<38>

BT_ON#

@
RH225
10K_0402_5%

<41>

ODD_DETECT#

@
RH202
10K_0402_5%

@
RH179
10K_0402_5%

System ID
PCH_GPIO57

PCH_GPIO39

PCH_GPIO38

LOW

VAW00 15''

INSPIRON

Entry

HIGH

VAW10 17''

VOSTRO

Mainstream

T5

KB_DET#

E8

PCH_GPIO27

E16

PCH_GPIO28

P8

BT_ON#

K1

GPIO35

K4

ODD_DETECT#

V8

PCH_GPIO37

M5

PCH_GPIO38

N2

PCH_GPIO39

M3

PCH_GPIO48

V13

GPIO49

V3

PCH_GPIO57

D6

TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24 / MEM_LED
GPIO27

TS_VSS1
TS_VSS2
TS_VSS3
SATA2GP / GPIO36
TS_VSS4
SLOAD / GPIO38

BD1
BD49
BE1
BE49
BF1

On-Die PLL Voltage Regulator


This signal has a weak internal pull up

BF49

voltage regulator enable


On-Die
On-Die PLL Voltage Regulator disable
1

@ RH165

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_5

A6

B47

NC_1

SDATAOUT1 / GPIO48

VSS_NCTF_4

B3

GPIO28

A40

P4

GATEA20

AU16

PCH_PECI_R

P5

KB_RST#

AY11
AY10
T14
AY1

<40>

1
2
@
0_0402_5%
RH161

PCH_PECI_R
KB_RST#

H_CPUPWRGD
H_THERMTRIP#_C 1
390_0402_5%
INIT3_3V#

H_PECI

<40,6>

<40>

<6>

2
RH162

H_THERMTRIP#

H_THERMTRIP#

<6>

@
CH102
0.1U_0402_10V7K~D

Place CH102 close to RH161


& PCH.

DF_TVS

AH8
AK11

@
RH163
10K_0402_5%

AH10
AK10

INIT3_3V

This signal has weak internal


PU, can't pull low

P37

SDATAOUT0 / GPIO39

A5

GPIO1

+3VS

C41

SATA3GP / GPIO37

A46

H
L

DF_TVS

GPIO35

A45

INIT3_3V#

STP_PCI# / GPIO34

A44

2 RH164 1

THRMTRIP#

GPIO28

A4

10K_0402_5%

PROCPWRGD

VSS_NCTF_18

+3VS

<41>

PAD~D

PCH_GPIO22

GPIO

D40

VGA_PWRGD

CPU/MISC

@
RH181
10K_0402_5%

@
RH182
10K_0402_5%

KB_DET#

1
2

@
RH244
10K_0402_5%
PCH_GPIO57

VGA_PWRGD

+3VS

NCTF

<53>
+3VS

ODD_EN#
@ T64

RH159
10K_0402_5%

RCIN#

+3V_PCH

ODD_EN#
GPIO69

LAN_PHY_PWR_CTRL / GPIO12

U2

GPIO16

TACH5 / GPIO69

TACH2 / GPIO6

B41

GPIO8

C4
<40>

TACH1 / GPIO1

C40

VSS_NCTF_22
VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2
BG48
BH3

PLACE RH150 CLOSE TO THE BRANCHING POINT


( TO CPU and NVRAM CONNECTOR)

BH47

Due to remove VCCDFERM


jumper(PJP66), need to
change the power rail to
+1.8V_RUN for D12" only

BJ4
BJ44
BJ45

+1.8VS

RH149 need to close to CPU


1

1
PCH_GPIO28
10K_0402_5%

TACH4 / GPIO68

BJ46

RH152
2.2K_0402_5%

BJ5
BJ6

1
PCH_LID_SW_IN#
1K_0402_5%

A42

2
RH240

GPIO1

BMBUSY# / GPIO0

T7

<6>

C2

H_SNB_IVB#

2
DF_TVS
1K_0402_1%

RH358

C48
D1
D49

DMI & FDI Termination Voltage

E1
E49

Set to Vss when LOW

DF_TVS

F1

Set to Vcc when HIGH


B

F49

BD82HM76-SLJ8E-C1_BGA989~D
R1@

+3VS

PCH_GPIO28

1K_0402_5%
ODD_DETECT#

GPIO16

2 200K_0402_5%
RH171

2 10K_0402_5%
RH172

BT_ON#

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

@ RH173

PCH_GPIO27
10K_0402_5%

2 8.2K_0402_5%
RH174

KB_RST#

2 10K_0402_5%
RH175

+3V_PCH

LOW - Tx, Rx terminated


to same voltage
(DC Coupling Mode)

VGA_PWRGD

2 10K_0402_5%
RH242

PCH_GPIO22

2 10K_0402_5%
RH176

+3VS

GPIO35

GPIO49

2 10K_0402_5%
RH177

RH168

RH169

1 1K_0402_5%

PCH_GPIO37

PCH_GPIO37

PCH_GPIO28 needs to be connected to XDP_FN8


PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

10K_0402_5%

2 10K_0402_5%
RH180

GPIO6

Please refer to Huron River Debug Board DG 0.5

2 10K_0402_5%
RH184

EC_SMI#

2 10K_0402_5%
RH183
PCH_GPIO48

ODD_EN#

2 10K_0402_5%
RH245

2 10K_0402_5%

RH178

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PCH (5/8) GPIO/CPU/MISC


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

17

of

57

Reserve for LVDS issue


+VCCA_LVDS
D

CH106

1U_0402_6.3V6K

+1.05VS

+1.05VS

+1.05VS

RH186

1
U47
2

VCCTX_LVDS[1]
VCCTX_LVDS[2]

60mA VCCTX_LVDS[3]
VCCTX_LVDS[4]

AK36

+VCCA_LVDS

AN16
AN17

2@
+1.05VS

AN21
AN26
AN27
AP21

AP24

CH49
1U_0402_6.3V6K

CH48
1U_0402_6.3V6K

CH47
1U_0402_6.3V6K

CH46
1U_0402_6.3V6K

+3VS

CH45
10U_0805_4VAM~D

AP23
1

AP26
AT24
AN33

VCCIO[15]
VCCIO[16]

Near AP43

AM37

+VCCTX_LVDS
CH39 1
0.01U_0402_16V7K

AM38
AP36

VCCIO[19]

+1.8VS
LH2
2
1
0.1UH_MLF1608DR10KT_10%_1608

CH41

1
1
22U_0805_6.3V6M
CH40
0.01U_0402_16V7K
2
2

VCC3_3[6]

V33

Place CH53 Near BG6 pin

2925mA

V34
2

VCCVRM[3]

2@

+1.05VS

@
1

+1.05VS_VCCAPLL_FDI

BG6

2+1.05VS_VCCDPLL_FDI
0_0805_1%

AP17

AT16

AU20

0.001

V5REF_Sus

0.001

Vcc3_3

3.3

0.266

VccADAC

3.3

0.001

VccADPLLA

1.05

0.08

VccADPLLB

1.05

0.08

VccCore

1.05

+3VS

1.3

VccDMI

1.05

0.042

VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCDMI[1]

20mA VCCCLKDMI

AT20

CH43
0.1U_0402_10V7K~D

@
1

+VCCP_VCCDMI

1
AB36

@
1

+1.05VS_VCC_DMI_CCI

RH191

+VCCP

RH190

VCCDFTERM[1]

190mAVCCDFTERM[2]

VCC3_3[3]

VCCVRM[2]
VccAFDIPLL

VCCDFTERM[3]
VCCDFTERM[4]

VCCIO[27]

AG16

VCCDMI[2]

2.925
1.01

VccSPI

3.3

0.02

VccDSW

3.3

0.003

VccpNAND

1.8

0.19

VccRTC

3.3

6 uA

VccSus3_3

3.3

0.119

+1.05VS

2 1U_0402_6.3V6K

+VCCPNAND
@
1

AJ16

AJ17

RH193

0_0805_1%
2
+1.8VS

1
RH196

+3V_VCCPSPI

VccSusHDA

3.3 / 1.5

VccVRM

1.8 / 1.5

VccCLKDMI

20mA VCCSPI

1.05
1.05

0_0805_1%

0_0805_1%
CH50
1U_0402_6.3V6K

AG17

V1

VccIO
VccASW

CH44

VCCIO[25]
VCCIO[26]

+VCCAFDI_VRM

RH195

+VCCP_VCCDMI

+VCCP_VCCDMI

FDI

1
0_0603_5%~D

0.001

0_0805_1%

1
VCC3_3[7]

RH188
@

+3VS_VCC3_3_6

CH52
0.1U_0402_10V7K~D

AP16

+VCCAFDI_VRM

1.05

V5REF

0.1uH inductor, 200mA

AP37

VCCIO[20]

0.1U_0402_10V7K~D

CH53
1U_0402_6.3V6K

VCCIO[18]

DFT / SPI

BH29

S0 Iccmax
Current (A)

+3VS
RH185
1
@

VCCIO[17]

CH51

2
RH194

Voltage

V_PROC_IO

CH34
10U_0805_4VAM~D

0_0805_1%

VCCAPLLEXP

+1.05VS

AK37

AN34
+3VS_VCCA3GBG

LH1
2
1
4.7UH_LQM18FN4R7M00D_20%

VCCIO[28]

HVCMOS

Place CH40 Near BJ22 pin

CH33
0.1U_0402_10V7K~D

+VCCADAC

CH32
0.01U_0402_16V7K

CRT

VSSADAC

VSSALVDS

DMI

BJ22

+VCCAPLLEXP

RH192
0_0805_1%

VCCADAC

1mA VCCALVDS

VCCIO

1+VCCAPLLEXP_R 1
2
1UH_LB2012T1R0M_20%~D
0_0603_5%~D
CH42
10U_0805_4VAM~D

2
RH187

AN19

+1.05VS_VCCDPLLEXP

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

U48

@ LH3

@
C

2 0_0603_1%

Voltage Rail
1mA

LVDS

+3VS

1300mA

VCC CORE

CH38
1U_0402_6.3V6K

CH37
1U_0402_6.3V6K

CH36
1U_0402_6.3V6K

CH35
10U_0805_4VAM~D

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

PCH Power Rail Table

POWER

UH1G

2
0_0805_1%

+3V_PCH

1
0_0603_5%~D

+3VS

1.05

0.01
0.16
0.02

VccSSC

1.05

0.095

VccDIFFCLKN

1.05

0.055

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

BD82HM76-SLJ8E-C1_BGA989~D

2
RH243

R1@

+1.5VS

CH54
1U_0402_6.3V6K

+VCCAFDI_VRM
@ RH197
1

0_0603_1%

+VCCAFDI_VRM

CH100
1U_0402_6.3V6K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PCH (6/8) PWR


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

18

of

57

VCC3_3 = 266mA detal waiting for newest spec

+1.05VS
@

@
CH62
1U_0402_6.3V6K

AA21

+1.05VS

CH66
22U_0805_6.3V6M

CH65
22U_0805_6.3V6M

AA24
1

AA26
AA27
AA29
AA31

CH70
1U_0402_6.3V6K

CH69
1U_0402_6.3V6K

+3VS

CH68
1U_0402_6.3V6K

AC26
C

AC27
AC29
AC31
AD29

1
RH215

2
0_0805_1%

AD31
W21

LH5
10UH_LBR2012T100M_20%
1
2

W23

W24

CH75
1U_0402_6.3V6K

+3VS_VCC_CLKF33
1

CH74
10U_0805_10V6K

VCCSUS3_3[8]
VCCIO[14]
DCPSUS[3]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]

AA19

W26
W29
W31
W33

VCCASW[1]
VCCASW[2]

VCCIO[34]

1010mA

1mA V5REF_SUS

VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]

DCPSUS[4]
VCCSUS3_3[1]

1mA V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]

VCCASW[16]

VCC3_3[4]

N16

+VCCRTCEXT
@

2
RH219

1
0_0603_5%~D

+1.05VM_VCCSUS

Y49

+VCCAFDI_VRM

CH79
0.1U_0402_10V7K~D

VCC3_3[2]

VCCASW[20]

+1.05VS_VCCA_A_DPL

BD47

+1.05VS_VCCA_B_DPL

BF47

+VCCDIFFCLK

VCCVRM[4]

VCCIO[13]

+1.05VS_VCCDIFFCLKN
+1.05VS_SSCVCC

AG33

+1.05VS_VCCDIFFCLKN

1U_0402_6.3V6K

1
RH223

AF17
AF33
AF34
AG34

2
0_0603_1% 1

+1.05VS

+VCCP

1
CH84
1U_0402_6.3V6K

CH85
0.1U_0402_10V7K~D

2
0_0603_1%

+V_CPU_IO

1
CH87
4.7U_0603_6.3V6K

LH7
10UH_LBR2012T100M_20%
1
2

+1.05VS

A22

+
A

+1.05VS_VCCAUPLL

M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

+3V_VCCPSUS_1

P34

+PCH_V5REF_RUN

RH209

2
0_0603_1%
1

N20
N22
P20

1
@

AF13

VCCSSC

VCCIO[4]

95mA

1
+

V_PROC_IO 1mA

VCCASW[22]
VCCASW[23]
VCCASW[21]

+1.05VS_SATA3

1
RH218

2
0_0805_1%

AF14

@ LH6
10UH_LBR2012T100M_20%
1
2 +VCCSATAPLL_R

+VCCSATAPLL
+VCCAFDI_VRM

+VCCAFDI_VRM
+1.05VS_VCC_SATA

+1.05VS_VCC_SATA

AC17

AD17

+1.05VS

CH78
1U_0402_6.3V6K

@
RH221

+1.05VS

0_0805_5%
@ CH81
10U_0805_10V6K

2
2
+1.05VS
0_0805_1%

+1.05VS

T21
V21
T19

VCCRTC

10mA VCCSUSHDA

P32

RH229

0.1U_0402_10V7K~D

CH93

R1@

+VCCSUSHDA

BD82HM76-SLJ8E-C1_BGA989~D

2
0_0603_1%

+3V_PCH

If it support 3.3V audio signals


POP:RH244
Depop RH245 / RH246
If it support 1.5V audio signals
POP:RH245 / RH246
Depop R244

Issued Date

Compal Electronics, Inc.

Compal Secret Data


2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

RH203
20K_0402_5%

Security Classification

2
0_0603_1%

+1.05VS_SATA3

CH77
0.1U_0402_10V7K~D

DCPSST
DCPSUS[1]
DCPSUS[2]

CH72
1U_0603_10V6K

+3VS

RH216

AH13
AH14

+PCH_V5REF_RUN

CH76
0.1U_0402_10V7K~D

2
2
0_0603_1%

DH3
RB751S40T1_SOD523-2~D

CH73
0.1U_0402_10V7K~D

AC16

RH212
100_0402_1%

2
0_0805_1%

+3VS_VCCPPCI

CH64
0.1U_0603_25V7K

+3VS

+3VS

1
RH214

+VCC3_3_2

+PCH_V5REF_SUS

2
+3V_PCH
0_0603_1%

RH222

VCCIO[2]

DH2
RB751S40T1_SOD523-2~D

W16

AF11

RH208
100_0402_1%

+3V_PCH

CH71
1U_0402_6.3V6K

AA16

AK1

+3V_PCH

+5VS

+3VS_VCCPCORE
1

AJ2

2
0_0603_1%

RH213

P22

T34

+1.05VS

RH210
1

+3V_VCCPSUS

+5V_PCH

+VCCA_USBSUS

CH97
1U_0402_6.3V6K

CH95
220U_B2_2.5VM_R35

LH8
10UH_LBR2012T100M_20%

+1.05VS_VCCA_B_DPL
CH96
1U_0402_6.3V6K

@
CH86
1U_0402_6.3V6K

+1.05VS_VCCA_A_DPL

CH94
220U_B2_2.5VM_R35

2 +VCCA_DPLL_L
0_0805_1%

T26

2
+3V_PCH
0_0603_1%
1
2
@
+3V_PCH
0_0603_1%

+RTCVCC

1
RH232

T17
V19

BJ8

CH89
0.1U_0402_10V7K~D

CH88
0.1U_0402_10V7K~D

2
1
RH227

RH206

2
V16

CH92
1U_0402_6.3V6K

P24

+1.05VM_VCCSUS

CH91
0.1U_0402_10V7K~D

2
0_0603_1%

CH90
0.1U_0402_10V7K~D

VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCIO[3]
CH82
1U_0402_6.3V6K

+VCCSST

1
RH224

VCCAPLLSATA
VCCVRM[1]

MISC

+1.05VS

VCCADPLLB 80mA

CH80

HDA

VCCIO[6]
VCCADPLLA 80mA

CPU

2
DCPRTC

SATA

2
0_0603_1%

V23
V24

RH205
+3V_VCCAUBG

RH217

VCCASW[19]

RTC

VCCASW[18]

+1.05VS

1
RH220

+3V_VCCPUSB

T24

+3VS

VCCIO[12]

T23

VCCASW[17]

VCCIO[5]
+1.05VS

CH57
0.1U_0402_10V7K~D

AL24

+VCCSUS1

RH207

119mA VCCSUS3_3[7]
VCCAPLLDMI2

AL29

VCC3_3[5]

+VCCDPLL_CPY

PCH_PWR_EN#

2 0_0603_1%

<35>

T29

CH56
1U_0402_6.3V6K

T27

BH23

+1.05VS

P28

+VCCAPLL_CPY_PCH

VCCIO[33]

RH231
150_0402_1%
2
1

VCCIO[32]

USB

CH59
10U_0805_10V6K
@

0_0805_5%

@ CH58
0.1U_0402_10V7K~D

DCPSUSBYP

PCI/GPIO/LPC

@ RH204
1
2

Clock and Miscellaneous

@ LH4
10UH_LBR2012T100M_20%
2
+VCCAPLL_CPY 1

+5V_PCH

QH5
AO3419L_SOT23-3
1

T38

VCCIO[31]
+1.05VS

2
3
0_0603_1%

+3VS_VCC_CLKF33

VCCIO[30]

VCCDSW3_3 3mA

V12

RH200

P26

CH63
1U_0402_6.3V6K

T16

+PCH_VCCDSW

VCCIO[29]

RH201

+1.05VS

+VCCPDSW

VCCACLK

2
0_0603_1%

CH61
0.1U_0402_10V7K~D

1
1

+1.05VS_VCCUSBCORE

CH67

CH55
0.1U_0402_10V7K~D

+5VALW

N26

CH83
1U_0402_6.3V6K

AD49

2 0_0603_1%

RH199

VCCDMI = 42mA detal waiting for newest spec

POWER

UH1J

0.1U_0402_10V7K~D

+3V_PCH

1
+VCCACLK
0_0603_5%~D

CH60
0.1U_0402_10V7K~D

2
RH198

PCH (7/8) PWR


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

19

of

57

UH1I

UH1H

H5
D

AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

BD82HM76-SLJ8E-C1_BGA989~D
R1@

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

BD82HM76-SLJ8E-C1_BGA989~D
R1@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PCH (8/8) VSS


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

20

of

57

+3VS

RV13

4.7K_0402_5%

BKOFF#

BKOFF#

RV17
56K_0402_5%
2
1

2
G
3

PCH_ENVDD

EC_ENVDD

EC_ENVDD

QV5
BSS138_SOT23~D

RV18
10K_0402_5%

W=60mils

1
1

<16>

+LCDVDD
+LCDVDD

1
CV20
4.7U_0805_10V4Z

USB20_CAM_P11

<16>

LVDS_A0LVDS_A0+

LVDS_A0LVDS_A0+

<15>
<15>

LVDS_A1LVDS_A1+

LVDS_A1LVDS_A1+

5P_0402_50V8C
CV17
@
1
2

<15>
<15>

LVDS_A2LVDS_A2+

LVDS_A2LVDS_A2+

CV18

<15>
<15>

LVDS_ACLKLVDS_ACLK+

LVDS_ACLKLVDS_ACLK+

<15>
<15>

LVDS_B0LVDS_B0+

LVDS_B0LVDS_B0+

USB20_CAM_N11

<15>
<15>

LVDS_B1LVDS_B1+

LVDS_B1LVDS_B1+

<15>
<15>

LVDS_B2LVDS_B2+

USB20_CAM_P11_R

USB20_CAM_N11_R

1
LV24
1
RV210

CV21
0.1U_0402_16V7K

<15>
<15>

LVDS_BCLKLVDS_BCLK+

5P_0402_50V8C @
1

WCM-2012HS-900T_4P
4
3
4
3

2
EMC@
2
@ 0_0402_5%

1
RV208

CE_EN_R

CE_EN_R only for reserve.


DBC_EN_R

2
0_0402_5%

<33>
<33>

MIC_DATA
MIC_CLK

MIC_DATA
MIC_CLK

LVDS_B2LVDS_B2+

USB20_CAM_P11_R
USB20_CAM_N11_R

MIC_CLK_R

RV30
0_0402_5%

+3VS_CAM

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

LVDS_BCLKLVDS_BCLK+

W=60mils

BAT54C-7-F_SOT23-3

<40>

2
G

CV19
0.1U_0402_16V7K

<15>

QV4
AO3419L_SOT23-3

DV7

PCH_ENVDD

CH751H-40PT_SOD323-2~D

QV3
2N7002BKW_SOT323-3~D

<15>
<15>

10K_0402_5%
RV16

2
1

1 1

JLVDS
DISPOFF#

DV6

W=60mils

RV15
47K_0402_5%

RV14
100_0402_1%

CH751H-40PT_SOD323-2~D

+3VS

<40>

+5VALW

DV5
+LCDVDD

LVDS Conn.

LCD PWR CTRL

+LCDVDD
+3VS

MIC_CLK_R

@
CV29
470P_0402_50V7K~D

MIC_DATA
<15>
<15>

LVDS_DDC_CLK
LVDS_DDC_DATA

RV19 @
RV20 @

LCD_TEST
EDID_CLK_LCD
EDID_DATA_LCD
INV_PWM
DISPOFF#

<40> LCD_TEST
1
1 0_0402_1%
0_0402_1%

2
2

@
CE_EN

CE_EN

RV62 1

2 0_0402_5%

CE_EN_R

DBC_EN

RV99 1

2 0_0402_5%

DBC_EN_R

1
2

2
5P_0402_50V8C
1

5P_0402_50V8C
1

CV27

CV28

LVDS_BCLK@

DV8
LVDS_BCLK+

MIC_CLK_R

1
D

2
G

2 0_0805_5%

QV7
2N7002BKW_SOT323-3~D

1
RV29

VGA_PWM

2
0_0402_1%

USB20_CAM_N11_R

1
3 2

5
4

@
QV9B

+LCDVDD_R

47K_0402_5%
CV31
0.1U_0402_16V7K

2N7002DW-7-F_SOT363-6

@
QV9A

RV209
2

@
G

@2

1000P_0402_50V7K

RV33
100K_0402_5%
@

3
1

@
RV32
820_0805_1%

+3VS_CAM

QV8
SI2301CDS-T1-GE3_SOT23-3

CV319

680P_0402_50V7K

+INV_PWR_SRC

+3VS

CV30

+5VALW

2N7002DW-7-F_SOT363-6

RV231
@

* Reserved for LCD


sequence tuning

+3VS_CAM

0_0603_1%

V I/O

USB20_CAM_P11_R

2
+3VS

CMOS_ON#

V I/O

1
2

INV_PWM

RV230
100K_0402_5%

Webcam PWR CTRL

<40>

V I/O

V BUS Ground

@
<15>

V I/O

IP4223CZ6_SO6~D
@

+INV_PWR_SRC

RV34
100K_0402_5%

5
MIC_DATA

RV27 1

2
+LCDVDD_R
@
0_0402_1%
RV31
0_0402_5%
2
1

* Reserved for EMI/ESD/RF


need to close to JLVDS

+5VS

2
+LCDVDD

1
RV28

1
EN_INVPWR

<40>

SP01000XE00

+INV_PWR_SRC

PWR_SRC_ON

B+

STARC_107K40-000001-G2
CONN@

CV24
10U_0805_10V6K

2
0_0805_1%

CV26
0.1U_0603_50V_X7R

RV26
100K_0402_5%

41
42
43
44
45
46

1
RV24

CV22

60mil

RV25
100K_0402_5%

CV25
1000P_0402_50V7K

+INV_PWR_SRC

G1
G2
G3
G4
G5
G6

Place close to JLVDS

QV6
SI3457CDV-T1-E3_TSOP6~D
+INV_PWR_SRC_R
6
4
5
2
1

B+

W=60mils

+LCDVDD

0.1U_0402_16V7K
CV23

60mil

@
RV216
0_0402_5%

RV100
0_0402_5%

LCD backlight PWR CTRL

+3VS

0.1U_0402_16V7K

DBC_EN

<40>
<40>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

LVDS/webcam
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

21

of

57

W=40mils

Place close to JHDMI1

RV36 0_1206_5%~D
2
1

HDMI_A0N_VGA
HDMI_A0P_VGA

<15>
<15>

HDMI_A1N_VGA
HDMI_A1P_VGA

<15>
<15>

HDMI_A2N_VGA
HDMI_A2P_VGA

CV36 2
CV37 2

1 0.1U_0402_10V7K~D TMDS_TX0N
1 0.1U_0402_10V7K~D TMDS_TX0P

CV38 2
CV39 2

1 0.1U_0402_10V7K~D TMDS_TX1N
1 0.1U_0402_10V7K~D TMDS_TX1P

CV40 2
CV41 2

4
LV7

2 0_0402_5%

2 0_0402_5%

TMDS_TX0P

TMDS_L_TXCP

1.5A_6V_1206L150PR~D
+3VS

RV38 1
TMDS_TX0N

FV1

@
BAT1000-7-F_SOT23-3~D

EMC@

RV37 1

1 0.1U_0402_10V7K~D TMDS_TX2N
1 0.1U_0402_10V7K~D TMDS_TX2P

DV9
2
3 NC

+5VS

WCM-2012HS-900T_4P
2
1
2

1
2

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

680_0402_1%

RV49

RV48

RV47

RV46

RV45

RV44

RV43

RV42

2 0_0402_5%

RV41 1

2 0_0402_5%

TMDS_TX1N

TMDS_TX1P

1
3

WCM-2012HS-900T_4P
2
1
2

4
LV9

RV50 1

RV39
10K_0402_5%

TMDS_L_TX0P

JHDMI

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_HPLUG

DDC_DAT_HDMI
DDC_CLK_HDMI
TMDS_L_TXCN
TMDS_L_TX1N

TMDS_L_TXCP
TMDS_L_TX0N

TMDS_L_TX1P

TMDS_L_TX0P
TMDS_L_TX1N

EMC@
@

TMDS_L_TX1P
TMDS_L_TX2N

2 0_0402_5%
TMDS_L_TX2P

2
G

@
RV53
100K_0402_5%

QV11
RV52 1

2N7002_SOT23-3

CV35

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

LOTES_ABA-HDM-022-K01
CONN@

2 0_0402_5%

TMDS_TX2P

WCM-2012HS-900T_4P
1
2
1
2

TMDS_L_TX2P

TMDS_TX2N

TMDS_L_TX2N

DC232000B00

RV51

+3VS

TMDS_L_TX0N

EMC@

RV40 1

0_0402_1%
1
2

4
LV8

10U_0603_6.3V6M

<15>
<15>

TMDS_TXCP

TMDS_L_TXCN

HDMI_A3N_VGA
HDMI_A3P_VGA

WCM-2012HS-900T_4P
2
1
2

+VDISPLAY_VCC

CV34

<15>
<15>

1 0.1U_0402_10V7K~D TMDS_TXCN
1 0.1U_0402_10V7K~D TMDS_TXCP

2 0_0402_5%

0.1U_0402_10V7K~D

TMDS_TXCN
CV32 2
CV33 2

RV35 1

4
LV10

RV54 1

EMC@

2 0_0402_5%

TMDS_TXCN

@ CV358

2 100P_0402_50V8J

TMDS_L_TXCN

CV349

2 3.3P_0402_50V8C~D

TMDS_TXCP

@ CV360

2 100P_0402_50V8J

TMDS_L_TXCP

CV350

2 3.3P_0402_50V8C~D

TMDS_TX0N

@ CV362

2 100P_0402_50V8J

TMDS_L_TX0N

CV351

2 3.3P_0402_50V8C~D

TMDS_TX0P

@ CV363

2 100P_0402_50V8J

TMDS_L_TX0P

CV352

2 3.3P_0402_50V8C~D

TMDS_TX1N

@ CV359

2 100P_0402_50V8J

TMDS_L_TX1N

CV353

2 3.3P_0402_50V8C~D

TMDS_TX1P

@ CV357

2 100P_0402_50V8J

TMDS_L_TX1P

CV354

2 3.3P_0402_50V8C~D

TMDS_TX2N

@ CV361

2 100P_0402_50V8J

TMDS_L_TX2N

CV355

2 3.3P_0402_50V8C~D

TMDS_TX2P

@ CV364

2 100P_0402_50V8J

TMDS_L_TX2P

CV356

2 3.3P_0402_50V8C~D

20111024 EMI ADD

20110805 EMI ADD

+3VS

2
B

3
1
RV58

DDC_DAT_HDMI

1
RV60

CV42
220P_0402_50V8J
2
DV11
BAV99-7-F_SOT23-3
@

2
+5V_HDMI_DDC
2.2K_0402_5%

DDC_CLK_HDMI

@
RV59
200K_0402_5%
RV55
100K_0402_5%

2
PCH_SDVO_CTRLCLK

QV12A
DMN66D0LDW-7_SOT363-6

HDMI_HPLUG

<15>

HDMI_DET

<15>
@
0_0402_1%
RV56

@
DV10
RB751V-40_SOD323-2

RV57
1
2
150K_0402_5%

QV13
MMBT3904_NL_SOT23-3

+5VS
+3VS

<15>

PCH_SDVO_CTRLDATA

+3VS

2
2.2K_0402_5%

QV12B
DMN66D0LDW-7_SOT363-6
A

46@

ROYALTY HDMI W/LOGO

Part Number
RO0000002HM

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Description
HDMI W/Logo:RO0000002HM

Compal Electronics, Inc.


HDMI
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

22

of

57

UG1

GCLK-UMA@

SLG3NB244VTR TQFN 16P CLK GEN

SLG3NB244VTR SA000057I00 Intel-UMA


SLG3NB300VTR SA00005RS00 Intel-DIS
+RTCBATT

+RTCVCC

R787 GCLK@
330_0402_5%

R788 @
0_0402_5%

+VCCP

+LAN_IO

+3VLP
C5 GCLK@

C7

C8

1
0.1U_0402_16V7K

C6

1 GCLK@
0.1U_0402_16V7K

1 GCLK@

1
0.1U_0402_16V7K

Depop if GCLK
with UMA

0.1U_0402_16V7K

GCLK@

GCLK@

22U_0805_6.3V6M

2
1
1

C9

UG1

10
15

+3VLP

+3VALW

VBAT

VDD_RTC_OUT

VDD

+VCCP
CLK_X1
CLK_X2

1
16

CLK_X1

Y1

1
3
GCLK@
1

OSC
OSC

SLG3NB274VTR_TQFN16_2X3

GCLK@

GND
GND

25MHz_B

6
5

PCH_RTCX1_R

<13>

GCLK@
2 R785
VGA_X1_R 1
10_0402_1%
LAN_X1_R 1 GCLK@ 2 R782
33_0402_5%
1
2 R783
PCH_X1_R
0_0402_5%

VGA_X1

<25>

PCH_X1

<14>

LAN_X1

GCLK@

XTAL_IN
XTAL_OUT

GCLK@
1

12P_0402_50V8J~D

C12
2

VDDIO_25M_B

25MHz_A

4
7
13

C11
2

VDDIO_25M_A

9
12

GND4

27MHz

GND1
GND2
GND3

+LAN_IO

VDDIO_27M

<14>

GCLK@
C14
5P_0402_50V8C

17

11

+1.8VGS

GCLK@

+V3.3A
32kHz

Place close
to UG1.8

14

2.2U_0603_6.3V6K
C10

+1.8VGS

GCLK-DIS@

25MHZ_10PF_7V25000014
CLK_X2

12P_0402_50V8J~D
B

LAN_X1_R

R784
0_0402_5%
1
2
@

reserved for swing level adjustment


(close to U2)

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


GCLK
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

23

of

57

GFX PCIE LANE REVERSAL


PEG_HTX_C_GRX_P[7..0]

<5>

PEG_HTX_C_GRX_P[7..0]

<5>

PEG_HTX_C_GRX_N[7..0]

PEG_GTX_C_HRX_P[7..0]

THR1@

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

AA38
Y37

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

U38
T37

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

T35
R36

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

R38
P37

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

P35
N36
N38
M37
M35
L36
L38
K37
K35
J36
J38
H37
H35
G36

PEG_GTX_C_HRX_N[7..0]

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

SA00004WI0L
UV1A

PEG_HTX_C_GRX_N[7..0]

PCIE_RX13P
PCIE_RX13N

PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N

Y33
Y32

PEG_GTX_C_HRX_P[7..0]

<5>

PEG_GTX_C_HRX_N[7..0]

<5>

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV43 DIS@
1 CV44 DIS@

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

W33 PCIE_CRX_C_GTX_P1
W32 PCIE_CRX_C_GTX_N1

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV45 DIS@
1 CV46 DIS@

PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

U33 PCIE_CRX_C_GTX_P2
U32 PCIE_CRX_C_GTX_N2

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV47 DIS@
1 CV48 DIS@

PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2

U30 PCIE_CRX_C_GTX_P3
U29 PCIE_CRX_C_GTX_N3

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV49 DIS@
1 CV50 DIS@

PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3

T33
T32

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV51 DIS@
1 CV52 DIS@

PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4

LVDS Interface
UV1G

LVDS CONTROL

T30
T29

PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV53 DIS@
1 CV54 DIS@

PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5

P33 PCIE_CRX_C_GTX_P6
P32 PCIE_CRX_C_GTX_N6

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV55 DIS@
1 CV56 DIS@

PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6

P30 PCIE_CRX_C_GTX_P7
P29 PCIE_CRX_C_GTX_N7

220nF_0402_16V7K 2
220nF_0402_16V7K 2

1 CV57 DIS@
1 CV58 DIS@

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7

VARY_BL
DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N

N33
N32

AK27
AJ27

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37

AF35
AG36

LVTMDP

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

N30
N29

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

L33
L32

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

L30
L29

TXOUT_L3P
TXOUT_L3N

K33
K32
J33
J32

AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@

G38
F37
F35
E37
B

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

K30
K29
H33
H32
RV61 2

1 0_0402_5%

+3VGS
CLOCK

1
2
+1.0VGS
RV198 MS@1.69K_0402_1%~D

+3VGS

PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION

PCIE_CALRP

DIS@

2
1K_0402_5%

AH16
AA30

PCIE_CALRN

Y30

1.27K_0402_1% 1 TH@

Y29

2K_0402_1% 1 TH@
1K_0402_1% 1 MS@

<16>

2 RV63
2 RV65
2 RV203

DGPU_HOLD_RST#

<16>

PCH_PLTRST#

+1.0VGS

IN1
IN2

Install 2K for Thames/Seymour

PERSTB

OUT

GPU_RST#

UV13
MC74VHC1G08DFT2G_SC70-5
DIS@

CV326
0.1U_0402_25V6K
DIS@

GPU_RST#

PWRGOOD

1
RV64

VCC

CLK_PEG_VGA
CLK_PEG_VGA#

AB35
AA36

GND

<14>
<14>

CLK_PEG_VGA
CLK_PEG_VGA#

DIS@
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
RV66
100K_0402_5% THAMES XT M2

Place CV326 Close to UV13

UV1

THR3@

SA00004WI1L

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

UV1

MSR1@

UV1

SA00005X10L

MARS-PRO_FCBGA962~D

CHR1@

UV1

SA00005X10L

MARS-PRO_FCBGA962~D

MARS Pro
UV1

MSR3@

CHR3@

Issued Date
Chelsea Pro

Chelsea Pro

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

ATI_ThamesXT_M2_PCIE/LVDS
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

24

of

57

Sam1GR3@

Samsung 2GB
SA00005SH0L(R1)
SA00005SH1L(R3)

128Mx16 (2G)

RV68

RV69

RV71

H5TQ2G63DFR-11C

Hynix 2GB
SA00003YO2L(R1)
SA00003YO3L(R3)

128Mx16 (2G)

RV67

RV70

RV71

AJ21
AK21

PT

AK26
AJ26

2
2
2

RV75 GPU_GPIO0
RV76 GPU_GPIO1
RV77 GPU_GPIO2

10K_0402_5%

RV78 AC_BATT

10K_0402_5%
10K_0402_5%

1
1

@
@

2
2

RV79 GPU_GPIO8
RV80 GPU_GPIO9

10K_0402_5%
10K_0402_5%
10K_0402_5%

1 TH@
1
@
1
@

2
2
2

<54>

VDDCI_VID

<53>

GPU_VID5

GPU_VID4
GPU_VID3
GPU_VID2
RV89 1 @

<53>

GPU_VID1
T78

T79

+3VGS
1
1
1

@
@
@

2 RV85
2 RV86
2 RV87

GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS

10K_0402_5%

2 RV88

GPIO26_TCK

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
GPU_GPIO8
AH15
GPU_GPIO9
AJ16
GPU_VID5
AK16
GPU_GPIO11
AL16
GPU_GPIO12
AM16
GPU_GPIO13
AM14
GPU_VID4
AM13
GPU_VID3
AK14
GPU_VID2
AG30
THM_ALERT#
AN14
2 10K_0402_5%
AM17
AL13
GPU_VID1
GPIO21_BBEN AJ14
AK13
AN13
VGA_CLKREQ#_R
GPIO24_TRSTB AM23
AN23
GPIO25_TDI
AK23
GPIO26_TCK
AL24
GPIO27_TMS
AM24
GPIO28_TDO
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2_R
VGA_SMB_CK2_R
AC_BATT
VDDCI_VID

2
0_0402_5%
2
0_0402_5%

<53>
<53>
<53>

RV81 GPU_GPIO11
RV82 GPU_GPIO12
RV83 GPU_GPIO13

10K_0402_5%
10K_0402_5%
10K_0402_5%

DPD

TX4P_DPD1P
TX4M_DPD1N
TX5P_DPD0P
TX5M_DPD0N

AK24

R
RB

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

G
GB
B
BB

DAC1

HSYNC
VSYNC

+1.8VGS
DIS@
2 RV93
DIS@
2 RV95

+1.8VGS

(Thames 75mA)

LV14DIS@
2
1
BLM15BD121SN1D_0402

RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2/NC
R2B/NC
G2/NC
G2B/NC
B2/NC
B2B/NC
C/NC
Y/NC
COMP/NC
H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

1U_0402_6.3V6K
DIS@
CV83

0.935V@ Mars Pro

AV33
AU34

XTALIN
XTALOUT

AW35

GPU_THERMAL_D+
GPU_THERMAL_D-

AF29
AG29

Add 12/6 for MLPS


AK32

TS_FDO

YV1
XTAL-DIS@
27MHZ_10PF_7V27000050
1
GND

GND

XTAL-DIS@

CV95
10P_0402_50V8J

CV94
10P_0402_50V8J

XTAL-DIS@

10mil
AJ32
AJ33

DIS@ CV93
0.1U_0402_16V7K

DIS@ CV91
10U_0603_6.3V6M

+1.8VGS

DIS@ CV92
1U_0402_6.3V6K

DIS@
(1.8V@20mA TSVDD)
LV16
1
2
+TSVDD
BLM15BD121SN1D_0402
1
1
1

RV97 XTAL-DIS@
1M_0402_5%
XTALIN

AL31

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

XXX

V2SYNC

IGNORE VIP DEVICE STRAPS

AU16
AV15

<15,40,45,46>

ACIN

VIP_DEVICE_STRAP_ENA
RV250
0_0402_5%
@

AT17
AR16

DDC1CLK
DDC1DATA
AUX1P
AUX1N

XTALIN
XTALOUT

DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N

XO_IN2

DPLUS
DMINUS

DDCCLK_AUX4P
DDCDATA_AUX4N

THERMAL

DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
DDC6CLK
DDC6DATA

TS_A/NC

DDCCLK_AUX7P
DDCDATA_AUX7N

TSVDD
TSVSS

H2SYNC

RSVD

GENERICC

AUD[1]

HSYNC

AU22
AV21

AUD[0]

VSYNC

AT23
AR22

AMD RESERVED CONFIGURATION STRAPS

AD39
AD37

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

AU20
AT19

<40>

ACIN_65W

AT21
AR20

H2SYNC

GPIO21

AE36
AD35

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

GENERICC

GPIO2

RV84 1 DIS@
+AVDD

AC33
AC34

+VDD1DI

2 499_0402_1%

10mil

65mA

PS_1

(1.8V@65mA AVDD)

100mA
10mil
(1.8V@100mA VDD1DI) 1

AC30
AC31
AD30
AD31

+1.8VGS

2
+1.8VGS
LV13DIS@
BLM15BD121SN1D_0402

RV237
8.45K_0402_1%
@

2
LV12DIS@
BLM15BD121SN1D_0402
PS_1

2
CV329

AF30
AF31

PS_2
RV238
4.75K_0402_1%
MS@

2 +DPLL_PVDD
0_0402_5%
RV247
1
2 DPLL_PVSS
@
0_0402_5%

AG31
AG32

GENLK_CLK
GENLK_VSYNC

T80
T81

PS_3
RV240
4.75K_0402_1%
MS@
CV333

AD33

TX_PWRS_ENB

Transmitter Power Saving Enable


GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable


GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

RV241

RV242

NC

4.75k

Bits [3:1]
000

Samsung

8.45k

2k

001

Micron

4.75k

NC

111

TH@
AF33

AA29

DIS@
RV90
10K_0402_5%

2
0_0402_5%

RV207

+3VGS
DIS@
RV91
10K_0402_5%

NC_TSVSSQ should be tied to GND on Thames/Seymour

AM26
AN26

EC_SMB_CK2

QV15A DIS@
DMN66D0LDW-7_SOT363-6
4

VGA_SMB_DA2
AM27
AL27

<40>

EC_SMB_DA2

<40>

QV15B DIS@
DMN66D0LDW-7_SOT363-6

AM19
AL19

AN20
AM20

1 RV92
@

2 0_0402_5%

1 RV94

2 0_0402_5%

AL30
AM30
AL29
AM29
AN21
AM21
AJ30
AJ31

VGA Thermal Sensor ADM1032ARMZ

AK30
AK29

Closed to GPU

+3VGS

MS@
CV85
0.1U_0402_16V7K

+3VGS

GPU_THERMAL_D-

CV89
2

MS@
2200P_0402_50V7K

2
XTALIN
RV232
0_0402_5%
GCLK-DIS@

RV96
4.7K_0402_5%

MS@

VDD
D+
DTHERM#

SCLK
SDATA
ALERT#
GND

VGA_SMB_CK2

VGA_SMB_DA2

6
5

THM_ALERT#
1

+3VGS
1
RV98

2
4.7K_0402_5%

ADM1032ARMZ-2REEL_MSOP8
MS@

Address:100_1101

CV90
10P_0402_50V8J
@

MS@
VGA_CLKREQ#_R

Hynix

Internal VGA Thermal Sensor

+3VGS

PS_3

RV199
2.2K_0402_5%
@

2
G

Need to CHECK CIS symbol

VGA_X1

PS_2

close to YV1
<23>

Mars Pro
MLPs

RV242
2K_0402_1%
X76@

0402 1% resistors are required.

UV14

+3VGS

RV241
8.45K_0402_1%
X76@

AG33

PEG_A_CLKRQ#

CV331
MS@

1
@

AC32
AD32
AF32

RV239
10K_0402_1%
@

Add 12/6 for MLPS

RV246

AD29
AC29

+1.8VGS
C

AB34
AD34
AE34

GPU_THERMAL_D+

<14>

GPIO8

+1.8VGS

AC36
AC38

+3VGS

11

AF37
AE38

THR1@

RSVD

216-0833000-A11-THAMES-XT-M2_FCBGA962~D

0
0: disable
1: enable

VGA_SMB_CK2

PLL/CLOCK
DPLL_VDDC

DDCCLK_AUX3P
DDCDATA_AUX3N

RV236
10K_0402_5%
MS@

(Thames 5mA)
XTALOUT

R2SET/NC

TS_FDO

GPIO[13:11]

QV14A
2N7002DW-7-F_SOT363-6

DPLL_PVDD
DPLL_PVSS
DDC/AUX

+DPLL_VDDC AN31

AW34

1U_0402_6.3V6K
DIS@
CV87

20mil

XTALIN
Voltage Swing: 1.8 V

RV235
10K_0402_5%
@

+DPLL_VDDC

0.1U_0402_16V7K
DIS@
CV88

10U_0603_6.3V6M
DIS@
CV86

2
1
BLM15BD121SN1D_0402

+DPLL_PVDD AM32
AN32
2 DPLL_PVSS

+3VGS

(Thames 125mA)

LV15DIS@

A2VDDQ/NC
VREFG
A2VSSQ/TSVSSQ

RV248
0_0402_1%

AH13

20mil

2
1
CV81 0.1U_0402_16V7K
DIS@
@
1

0.1U_0402_16V7K
DIS@
CV84

10U_0603_6.3V6M
DIS@
CV82

A2VDD/NC

20mil

+VREFG_GPU

ROMIDCFG(2:0)

AT15
AR14

DAC2

HPD1

1 249_0402_1%

+DPLL_PVDD

+1.0VGS

1 499_0402_1%

ENABLE EXTERNAL BIOS ROM

+1.8VGS

VDD2DI/NC
VSS2DI/NC

0.60 V level, Please


VREFG Divider ans
cap close to ASIC

RESERVED

GPIO_22_ROMCSB

PACIN#

SCL
SDA
GENERAL PURPOSE I/O

STRAPS
1 TH@
1 TH@
1
@

TX3P_DPD2P
TX3M_DPD2N

I2C

Micron 2GB
SA00005XB0L(R1)
SA00005XB1L(R3)

10K_0402_5%
10K_0402_5%
10K_0402_5%

TXCDP_DPD3P
TXCDM_DPD3N

VGA_SMB_DA2 TH@ 1
RV251
VGA_SMB_CK2 TH@ 1
RV252
+3VGS

TX2P_DPC0P
TX2M_DPC0N

SWAPLOCKA
SWAPLOCKB

H5TQ2G63DFR-11C

128Mx16 (2G)

TX1P_DPC1P
TX1M_DPC1N

GPIO21

BIOS_ROM_EN

QV14B
2N7002DW-7-F_SOT363-6
DIS@

DIS@

K4W2G1646E-BC11

X7644031L13

DPC

RSVD

AT33
AU32
AU14
AV13

AC_BATT

RV71

VGA ENABLED

10K_0402_5%

RV69

GPIO9

DIS@
DIS@

4.7K_0402_5%

X7644031L06

RV67

TX0P_DPC2P
TX0M_DPC2N

BIF_VGA DIS

RV74
AR32
AT31

Micron 1GB
SA00004Y20L(R1)
SA00004Y21L(R3)

RESERVED

MT41J64M16JT-107G:G

64MX16 (1G)

TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N

GPIO8

RV73

Hyn2GR3@

RSVD

AV31
AU30

ZZZ1

Hyn2GR1@

RV72

0: 2.5GT/s
1: 5GT/s

ZZZ6

RV70

Advertises PCIE speed


when compliance test

0.68U_0402_10V

X7644031L12

TX4P_DPB1P
TX4M_DPB1N

GPIO2

+3VGS

H5TQ1G63DFR-11C

64MX16 (1G)
X7644031L05

DPB

RSVD

+3VGS

AR30
AT29

0: disable
1: enable

RV67

RV72

PCIE TRANSMITTER DE-EMPHASIS

Hynix 1GB
SA000041S3L

RV69

GPIO1

RV68

TX_DEEMPH_EN

RECOMMENDED
SETTINGS

Sam2GR3@

TX3P_DPB2P
TX3M_DPB2N

AT27
AR26

0.68U_0402_10V

ZZZ2

VRAM_ID0
VRAM_ID1
VRAM_ID2

0: 50% swing
1: Full swing

64MX16 (1G)
Sam2GR1@

Samsung 1GB
SA00004GS0L(R1)
SA00004GS1L(R3)

TXCBP_DPB3P
TXCBM_DPB3N

PCIE FULL TX OUTPUT SWING

K4W1G1646G-BC11

TX2P_DPA0P
TX2M_DPA0N

DESCRIPTION OF DEFAULT SETTINGS

GPIO0

1U_0402_6.3V6K
DIS@
CV76

VRAM_ID0 VRAM_ID1 VRAM_ID2

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

PIN

TX_PWRS_ENB

10U_0603_6.3V6M
DIS@
CV77

Vendor
ZZZ7

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

X7644031L11

STRAPS

AU26
AV25

0.1U_0402_16V7K
DIS@
CV75

X7644031L02

AT25
AR24

TX1P_DPA1P
TX1M_DPA1N

DPA

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

VRAM_ID2

AU24
AV23

TXCAP_DPA3P
TXCAM_DPA3N

VRAM_ID1

VRAM_ID0

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

X76@
X76@
X76@
X76@
X76@
X76@

Micron1GR3@

2
2
2
2
2
2

1U_0402_6.3V6K
DIS@
CV79

ZZZ3

Micron1GR1@

1
1
1
1
1
1

10U_0603_6.3V6M
DIS@
CV80

ZZZ5

RV67
RV68
RV69
RV70
RV71
RV72

0.1U_0402_16V7K
DIS@
CV78

X7644031L10

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE


GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

+1.8VGS

X7644031L01

CONFIGURATION STRAPS

UV1B

ZZZ4

Sam1GR1@

0.68U_0402_10V

ZZZ8

@
2N7002_SOT23-3
QV28

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2 RV200 1
0_0402_5%

2012/08/22

Deciphered Date

2013/08/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

ATI_ThamesXT_M2_Main_MSIC
Size

Document Number

Rev
1.0

LA-9104P
Date:

Wednesday, August 29, 2012


1

Sheet

25

of

57

Switch circuits in BACO desingns for Thanes/Seymour only


Circuits to support BACO

+3VGS

55mA@1.0V, in BACO mode


RV101
10K_0402_5%
DIS@

+1.0VGS

+BIF_VDDC

+VGA_CORE

60mil
1

1
DIS@

+3VGS

IN1

RUNPWROK
RV102

2
@

RV233
0_0402_1%

for PX4.0 and PX5.0

PX_MODE

PX_MODE

CV97
22U_0805_6.3V6M

<40,53,54>

PX_MODE=1 for Normal Operation

PX_MODE=0 for BACO mode to shut down power rails expcept VDDR3,PCIE_VDDC and 1.8V rail

2
PX_MODE
0_0402_1%

for PX5.0

CV100

+1.8VS TO +1.8VGS

+3VALW

1U_0603_10V6K

OUT

UV16
MC74VHC1G08DFT2G_SC70-5

IN2

@
DV12
RB751V-40_SOD323-2
1
2

PXS_PWREN

DIS@
RV105
20K_0402_5%

+1.8VS

2MM

PXS_PWREN 2
G

PXS_PWREN

1
C

J9
UV35

PXS_PWREN#

<16,53>

+1.8VGS

DIS@
RV109
100K_0402_5%

DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

QV25 DIS@
2N7002_SOT23-3

DIS@

GND

RV104
5.11K_0402_1%
DIS@

VCC

+3VGS CV99
@
0.1U_0402_16V7K
1
2

QV21
2N7002K_SOT23-3
DIS@

2
0_0603_5%~D

for PX5.0

PX4.0 +VGA_CORE,VDDCI,+1.5VGS ON

CV320
10U_0805_10V6K
2 DIS@

CV321
1U_0603_10V6K
2 DIS@

1 2

Note:

2N7002H_SOT23-3
QV29
@

1
2

330K_0402_5%
RV128
DIS@

1 RV211 2
DIS@ 470K_0402_5%

PXS_PWREN# 2
G

2N7002H_SOT23-3
DIS@

QV10

+1.5VGS

RV212
0_0402_5%
@

2
G
S

PXS_PWREN# 1 RV214 2
@
0_0402_5%

Power Seguence of Thames and Mars Pro

+1.5VGPU

+1.5VGPU TO +1.5VGS

RV213
470_0603_5%
@

B+_BIAS

PX4.0 +3VGS, +1.0VGS,+1.8VGS OFF


PX5.0 +3VGS,+VGA_CORE,VDDCI,+1.5VGV,+1.0VGS,+1.8VGS OFF

2
G

PX_EN

1
RV234

for PX4.0
<27>

TH@

2
0_0805_5%

RV103

60mil

MS@

CV2
0.1U_0603_25V7K
DIS@

JP9 @

1
2MM

UV17 DIS@
AO4304L_SO8

10U_0603_6.3V6M

CV105
DIS@

RV111 @
470_0603_5%

B+_BIAS

1
2MM

+5VALW

DIS@
RV107

DIS@
RV108

1
20K_0402_5%

CV101
DIS@

QV22 DIS@
AP2301GN-HF_SOT23-3

DIS@
QV24
S

1 DIS@
CV103
0.1U_0603_25V7K

Deciphered Date

1
@

2
0_0402_5%
A

2
2N7002H_SOT23-3

Compal Electronics, Inc.


2013/08/31

Title

Date:

2
G
QV23
2N7002K_SOT23-3
@

RV110
PXS_PWREN#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

RV106
470_0603_5%
@

1K_0402_5%

2012/08/22

CV102
DIS@

Compal Secret Data

Security Classification

1U_0603_10V6K

2
G

PXS_PWREN

Issued Date

10U_0603_6.3V6M

2 0_0402_5%

CV107 DIS@
0.1U_0603_25V7K

2
2M_0402_5%~D

DIS@ RV115

+3VGS
JP8 @

@
PX_MODE# 1 RV116

DIS@
RV117
100K_0402_5%

DIS@
QV27B

DIS@
QV27A

PX_MODE# 2

DMN66D0LDW-7_SOT363-6

PX_MODE

+3VS

DMN66D0LDW-7_SOT363-6

3 2

<20ms

+3.3VS TO +3.3VGS

DIS@
RV114
100K_0402_5%

2
G
QV26 @
2N7002K_SOT23-3

+1.0VGS

DIS@
20K_0402_5%
RV113

+3VALW

RV112
300K_0402_5%
DIS@

+1.5VGS

+1.8VGS

CV106 DIS@
1U_0603_10V6K

1 2

+VDDCI

1
2
3

+VGA_CORE

8
7
6
5

10U_0603_6.3V6M 1 10U_0603_6.3V6M 1
CV309
CV104
DIS@
DIS@

+3VGS
B

ATI_ThamesXT_M2_BACO POWER
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

26

of

57

UV1F

(Thames 330mA)
+DPAB_VDD18

@ CV119
0.1U_0402_16V7K

AP13
AT13

AN17
AP16
AP17
AW14
AW16

+DPCD_VDD10

20mil

AP22
AP23

150_0402_1% 2 DIS@

AP14
AP15

1.0V@240mA DPEF_VDD10)
0.935V@Mars Pro

@ CV125
0.1U_0402_16V7K

+DPEF_VDD10

RV126
0_0402_1%

@ CV122
0.1U_0402_16V7K

1 RV122 AW18

20mil

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

AP31
AP32

CV109
1U_0402_6.3V6K

(Thames 330mA)

+1.0VGS

+DPAB_VDD10

1
RV120

+DPAB_VDD10

AN27
AP27
AP28
AW24
AW26

2
0_0402_1%

20mil
DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AP25 130mA
AP26

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

20mil

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

AN33 110mA
AP33

AN29
AP29
AP30
AW30
AW32

AW28 RV123 1 DIS@

20mil

2 150_0402_1%

+DPAB_VDD18

AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

20mA

10mil

AU28
AV27

+DPEF_VDD10

+DPAB_VDD18

AL33
AM33

20mA

10mil

AV29
AR28

+DPCD_VDD18

AN34
AP39
AR39
AU37

+DPEF_VDD10

@ CV124
1U_0402_6.3V6K

@ CV123
10U_0603_6.3V6M

@ CV121
1U_0402_6.3V6K

+DPEF_VDD18

@ CV120
10U_0603_6.3V6M

RV124
0_0402_1%

+1.0VGS

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

+DPEF_VDD18

1.8V@300mA DPEF_VDD18)

+DPAB_VDD10

20mil

2@

0.935V@Mars Pro

+DPCD_VDD10

(Thames 330mA)

2@

+1.8VGS

2
0_0402_1%

+DPAB_VDD18

(Thames 220mA)

110mA

+DPCD_VDD18

AN24
AP24

20mil (1.0V@220mA DPAB_VDD10)

AN19
AP18
AP19
AW20
AW22

+1.8VGS

130mA
DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

1
RV118

10U_0603_6.3V6M
CV116

+DPCD_VDD10

RV121
0_0402_1%

@ CV118
1U_0402_6.3V6K

20mil

20mil

DP A/B POWER

+DPCD_VDD10

DP C/D POWER

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

1U_0402_6.3V6K
CV115

CV113
0.1U_0402_16V7K

1.0V@220mA DPCD_VDD10)
0.935V@Mars Pro
@ CV117
10U_0603_6.3V6M

CV112
1U_0402_6.3V6K

CV111
10U_0603_6.3V6M

(Thames 220mA)

AP20
AP21

+DPCD_VDD18

CV114
0.1U_0402_16V7K

RV119
0_0402_1%

+1.0VGS

20mil

+DPCD_VDD18

1.8V@300mA DPCD_VDD18)
1

CV108
0.1U_0402_16V7K

UV1H

(Thames 330mA)
+1.8VGS

CV110
10U_0603_6.3V6M

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18
1
1

20mA

20mil
1

AF34
AG34

20mil

20mA

20mA
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

AK33
AK34

PS_0

AM37
AN38

10mil

+DPEF_VDD18

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

20mA
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

AF39
AH39
AK39
AL34
AM34

10mil

AV19
AR18

+DPEF_VDD18

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

+DPEF_VDD10

+DPCD_VDD18

DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

+DPEF_VDD18

10mil

AU18
AV17

AL38
AM35

10mil

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

+1.8VGS

AM39

RV127
150_0402_1%
DIS@

RV243
8.45K_0402_1%
MS@

DPEF_CALR
216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@

PS_0

MLPS Bit

RV201
0_0402_5%
TH@

2K_0402_1%

CV335

0.68U_0402_10V

MS@

RV201

Thames/Seymour Only

AMD recommended setting


strap

R_PU

R_PD

PS0:

11001

RV243=8.45K

RV201=2K

CV335=NC

PS1:

11000

RV237=NC

RV238=4.75K

CV329=NC

PS2:

00000

RV239=NC

RV240=4.75K

CV331=0.68u

PS3:

11000

RV241=NC

RV242=4.75K

CV333=NC

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

PX_EN

<26>

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

RV125
4.7K_0402_5%
DIS@

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

A39 MECH#1
AW1 MECH#2
AW39MECH#3

T82 PAD
T83 PAD
T84 PAD

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@

Do not install for Heathrow/Mars Pro


PS_0 Should be tied to GND on Thames/Seymour

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

ATI_ThamesXT_M2_PWR_GND
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

27

of

57

(Thames 440mA)

+VGA_CORE

AN9
AN10

1
RV215
10_0402_1%
DIS@

RV202
10_0402_1%
DIS@

1
2

RV204
DIS@ 10_0402_1%

SPVSS

VOLTAGE
SENESE

AF28

FB_VDDC

10mil

VSSSENSE_VGA

VSSSENSE_VGA

SPV10

10mil

VCCSENSE_VGA
VDDCI_SEN

VDDCI_SEN

SPV18

AG28
AH29

FB_VDDCI
FB_GND

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@

1U_0402_6.3V6K
DIS@
CV133

0.1U_0402_16V7K
DIS@
CV132

10U_0603_6.3V6M
DIS@
CV134

1U_0402_6.3V6K
DIS@
CV130

1U_0402_6.3V6K
DIS@
CV129

1U_0402_6.3V6K
DIS@
CV128

10U_0603_6.3V6M
DIS@
CV131

1U_0402_6.3V6K
DIS@
CV150

10U_0603_6.3V6M
DIS@
CV151

1U_0402_6.3V6K
DIS@
CV149

1U_0402_6.3V6K
DIS@
CV148

1U_0402_6.3V6K
DIS@
CV147

1U_0402_6.3V6K
DIS@
CV146

(1.0V@1920mA PCIE_VDDC)

(Mars Pro)

(0.935V@2.5A PCIE_VDDC)

1
1

1U_0402_6.3V6K
DIS@
CV186

1U_0402_6.3V6K
DIS@
CV185

1U_0402_6.3V6K
DIS@
CV184

1U_0402_6.3V6K
DIS@
CV183

1U_0402_6.3V6K
DIS@
CV182

1U_0402_6.3V6K
DIS@
CV181

+VGA_CORE

22U_0603_6.3V6M
DIS@
CV192

+VGA_CORE

+BIF_VDDC

55mA
1

For non-BACO designs, connect BIF_VDDC to VDDC.


For BACO designs - see BACO reference schematics

(GDDR3/DDR3 1.12V@4A VDDCI)


AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

DIS@

1U_0402_6.3V6K
DIS@
CV169

1U_0402_6.3V6K
DIS@
CV168

1U_0402_6.3V6K
DIS@
CV167

1U_0402_6.3V6K
DIS@
CV166

1U_0402_6.3V6K
DIS@
CV165

1U_0402_6.3V6K
DIS@
CV164

1U_0402_6.3V6K
DIS@
CV163

1U_0402_6.3V6K
DIS@
CV162

1U_0402_6.3V6K
DIS@
CV161

1U_0402_6.3V6K
DIS@
CV160

1U_0402_6.3V6K
DIS@
CV159

+VDDCI

+VGA_CORE
LV25@
1
2
BLM15BD121SN1D_0402
LV26@
1
2
BLM15BD121SN1D_0402

4A

(GDDR5 1.12V@16A VDDCI)

10U_0603_6.3V6M
DIS@
CV323

+SPV10

MPV18#1
MPV18#2

(Thames 1.1A)

22U_0603_6.3V6M
DIS@
CV214

0.1U_0402_16V7K
DIS@
CV199

1U_0402_6.3V6K
DIS@
CV198

+VDDCI

+SPV18 AM10

VCCSENSE_VGA
<54>

<53>

10mil
20mil

H7
H8

10U_0603_6.3V6M
DIS@
CV322

<53>

PLL

20mil
+MPV18

(120mA SPV10)
0.1U_0402_16V7K
DIS@
CV217

1U_0402_6.3V6K
DIS@
CV216

DIS@
1
2
MCK1608471YZF 0603

10U_0603_6.3V6M
DIS@
CV215

LV23

NC_VDDRHB
NC_VSSRHB

10U_0603_6.3V6M
DIS@
CV324

(Thames
100mA)
0.935V@Mars Pro

10U_0603_6.3V6M
DIS@
CV213

NC_VDDRHA
NC_VSSRHA

V12
U12

+1.0VGS

0.1U_0402_16V7K
DIS@
CV202

(1.8V@75mA SPV18)
10U_0603_6.3V6M
DIS@
CV200

10U_0603_6.3V6M
DIS@
CV197

LV22DIS@
1
2
BLM15BD121SN1D_0402

M20
M21

LV21DIS@
1
2
MCK1608471YZF 0603

(Thames 50mA)
1U_0402_6.3V6K
DIS@
CV201

+1.8VGS

1U_0402_6.3V6K
DIS@
CV325

(Thames
150mA)
Broadway and Madison: 1.8V@150mA MPV18)

+1.8VGS (M97,

1U_0402_6.3V6K
DIS@
CV212

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

1U_0402_6.3V6K
DIS@
CV211

10U_0603_6.3V6M
DIS@
CV191

AD12
AF11
AF12
AG11

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

10U_0603_6.3V6M
DIS@
CV367

+VDDR4 AF13
AF15
AG13
AG15

1U_0402_6.3V6K
DIS@
CV209

0.1U_0402_16V7K
DIS@
CV194

1U_0402_6.3V6K
DIS@
CV193

10U_0603_6.3V6M
DIS@
CV366

20mil

DIS@ LV20
1
2
BLM15BD121SN1D_0402

1U_0402_6.3V6K
DIS@
CV208

+1.8VGS

I/O

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

1U_0402_6.3V6K
DIS@
CV180

AF23
AF24
AG23
AG24

10U_0603_6.3V6M
DIS@
CV365

10mil

1U_0402_6.3V6K
DIS@
CV207

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

+BIF_VDDC

1U_0402_6.3V6K
DIS@
CV179

AF26
AF27
AG26
AG27

LEVEL
TRANSLATION

1U_0402_6.3V6K
DIS@
CV206

20mil

+1.8VGS

2
1
MBK1608121YZF_0603

+VGA_CORE

1U_0402_6.3V6K
DIS@
CV178

40mA
(1.8V@40mA PCIE_PVDD) DIS@ LV18

(Thames 20.5A)

1U_0402_6.3V6K
DIS@
CV205

0.1U_0402_16V7K
DIS@
CV174

1U_0402_6.3V6K
DIS@
CV173

1U_0402_6.3V6K
DIS@
CV172

1U_0402_6.3V6K
DIS@
CV171

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

1U_0402_6.3V6K
DIS@
CV158

+VDDC_CT

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

1U_0402_6.3V6K
DIS@
CV177

0.1U_0402_16V7K
DIS@
CV156

0.1U_0402_16V7K
DIS@
CV155

0.1U_0402_16V7K
DIS@
CV154

0.1U_0402_16V7K
DIS@
CV153

+1.0VGS

1U_0402_6.3V6K
DIS@
CV196

+PCIE_PVDD

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

1U_0402_6.3V6K
DIS@
CV204

1U_0402_6.3V6K
DIS@
CV190

1U_0402_6.3V6K
DIS@
CV189

1U_0402_6.3V6K
DIS@
CV188

10U_0603_6.3V6M
DIS@
CV187

POWER

(Thames 60mA)

(1.8V@110mA VDD_CT)
10U_0603_6.3V6M
DIS@
CV170

+3VGS

(Thames 250mA)

DIS@ LV19
1
2
BLM15BD121SN1D_0402

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

1U_0402_6.3V6K
DIS@
CV157

+1.8VGS

CV327
330U_D2_2VM_R6M~D

0.1U_0402_16V7K
DIS@
CV152

+1.5VGS

1
2
@
RV245
0_0402_5%

1U_0402_6.3V6K
DIS@
CV176

2 +PCIE_VDDR
TH@ 1
RV244
0_0402_5%

1U_0402_6.3V6K
DIS@
CV175

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

1U_0402_6.3V6K
DIS@
CV195

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

1U_0402_6.3V6K
DIS@
CV203

1U_0402_6.3V6K
DIS@
CV145

1U_0402_6.3V6K
DIS@
CV144

1U_0402_6.3V6K
DIS@
CV143

1U_0402_6.3V6K
DIS@
CV142

1U_0402_6.3V6K
DIS@
CV141

10U_0603_6.3V6M
DIS@
CV140

10U_0603_6.3V6M
DIS@
CV139

10U_0603_6.3V6M
DIS@
CV138

10U_0603_6.3V6M
DIS@
CV137

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

40mil

PCIE

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

+1.8VGS
DIS@ LV17
2
1
MBK1608121YZF_0603

1U_0402_6.3V6K
DIS@
CV210

MEM I/O

(Thames 1.7)A
10U_0603_6.3V6M
DIS@
CV136

220U_B2_2.5VM_R35
CV135

0.1U_0402_16V7K
DIS@
CV126

UV1E

For DDR3 MVDDQ = 1.5V


+1.5VGS

0.1U_0402_16V7K
DIS@
CV127

(1.8V@504mA PCIE_VDDR)

+PCIE_VDDR

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

ATI_ThamesXT_M2_Power
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

28

of

57

UV1C
DDR2
GDDR3/GDDR5
DDR3

1 TH@
1 SE@
1 TH@

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

L27
N12
AG12

RV132
RV134
RV135

1 SE@
1 TH@
1 TH@

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

M12
M27
AH12

RV206
RV205

1 MS@
1
@

2 120_0402_5%
2 120_0402_5%

ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

WEA0B
WEA1B

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

A32
C32
D23
E22
C14
A14
E10
D9

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

C34
D29
D25
E20
E16
E12
J10
D7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

A34
E30
E26
C20
C16
C12
J11
F8

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

J21
G19

ODTA0
ODTA1

H27
G27

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19

MAA13
MAA14

A_BA[2..0]

DQMA#[7..0]

QSA[7..0]

QSA#[7..0]

ODTA0
ODTA1

MAA[14..0]

<30>

A_BA[2..0]

<30>

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

<30>

<30>

<30>

<30>
<30>

CLKA0 <30>
CLKA0# <30>
CLKA1 <30>
CLKA1# <30>
RASA0#
RASA1#

<30>
<30>

CASA0#
CASA1#

<30>
<30>

CSA0#_0

<30>

CSA1#_0

<30>

CKEA0
CKEA1

<30>
<30>

WEA0#
WEA1#

<30>
<30>

+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12

MAA0_8
MAA1_8

MAA13
MAA14

RV133 1

<29,30>
<29,30>

2
TESTEN
5.11K_0402_1%

AD28
AK10
AL10

SE@

TH@

RV132

SE@

RV134

TH@

RV135

TH@

RV206

MS@

RV205

RV138
4.7K_0402_5%
@

CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

1 RV144 2
10_0402_1%
DIS@

DRAM_RST#_R

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8

MAB13
MAB14

DQMB#[7..0]

QSB[7..0]

QSB#[7..0]

ODTB0
ODTB1

<31>

<31>

<31>

<31>
<31>
C

CLKB0 <31>
CLKB0# <31>
CLKB1 <31>
CLKB1# <31>
RASB0#
RASB1#

<31>
<31>

CASB0#
CASB1#

<31>
<31>

CSB0#_0

<31>

CSB1#_0

<31>

CKEB0
CKEB1

<31>
<31>

WEB0#
WEB1#

<31>
<31>

AH11

MAB13
MAB14

<29,31>
<29,31>

DRAM_RST#_R

route 50ohms single-ended/100ohms diff


and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

@
RV137
51.1_0402_1%

+1.5VGS

RV142
40.2_0402_1%
DIS@
+VDD_MEM15_REFDB

+VDD_MEM15_REFSB

RV149
100_0402_1%
DIS@

CV224
0.1U_0402_16V7K
DIS@
A

1
RV148
100_0402_1%

CV223
0.1U_0402_16V7K
DIS@

1
2

DIS@
RV145
4.99K_0402_1%

CV221
0.1U_0402_16V7K
DIS@

DRAM_RST

RV141
40.2_0402_1%
DIS@

DIS@

MAB0_8
MAB1_8

CLKTESTA
CLKTESTB

1 RV143 2
51.1_0402_1%
DIS@

+VDD_MEM15_REFSA

RV147
100_0402_1%
DIS@

TESTEN

+1.5VGS

+VDD_MEM15_REFDA

CSB0B_0
CSB0B_1

DRAM_RST#

DIS@
CV222
120P_0402_50V9

RV140
40.2_0402_1%
DIS@

CASB0B
CASB1B

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

<31>

@
CV219
0.1U_0402_16V7K

<30,31>

RASB0B
RASB1B

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

<31>

B_BA[2..0]

+1.5VGS

+1.5VGS

CLKB1
CLKB1B

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

MAB[14..0]

RV131

RV146
100_0402_1%
DIS@

CLKB0
CLKB0B

H3
H1
T3
T5
AE4
AF5
AK6
AK5

B_BA[2..0]

RV130

@
RV136
51.1_0402_1%

CV220
0.1U_0402_16V7K
DIS@

ADBIB0/ODTB0
ADBIB1/ODTB1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These


Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

Mars Pro

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

Seymour M2

TH@

Co-lay Thames/Seymour/Mars Pro

RV139
40.2_0402_1%
DIS@

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

MAB[14..0]

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@
@
CV218
0.1U_0402_16V7K

216-0833000-A11-THAMES-XT-M2_FCBGA962~D
THR1@

+1.5VGS

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

MDB[0..63]

MDB[0..63]

DIS@

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

Thames M2

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

WEB0B
WEB1B

RV129

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

<31>

DDR2
GDDR5/GDDR3
DDR3

RV129
RV130
RV131

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

UV1D
DDR2
GDDR3/GDDR5
DDR3

L18
L20

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

MAA[14..0]

GDDR5

+VDD_MEM15_REFDA
+VDD_MEM15_REFSA

+1.5VGS

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

MDA[0..63]

MDA[0..63]

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

GDDR5

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

<30>

DDR2
GDDR5/GDDR3
DDR3

MEMORY INTERFACE A

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MEMORY INTERFACE B

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

ATI_ThamesXT_M2_MEM IF
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

29

of

57

CHANNEL A: 256MB/512MB DDR3


UV18

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

<29>

MDA[0..63]

<29>

MAA[14..0]

MDA[0..63]

MAA[14..0]

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA29
MDA27
MDA30
MDA26
MDA28
MDA24
MDA31
MDA25

D7
C3
C8
C2
A7
A2
B8
A3

MDA0
MDA5
MDA1
MDA6
MDA3
MDA4
MDA2
MDA7

VREFC_A2
VREFD_Q2

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

UV20

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA18
MDA23
MDA19
MDA20
MDA17
MDA21
MDA16
MDA22

D7
C3
C8
C2
A7
A2
B8
A3

MDA15
MDA10
MDA14
MDA11
MDA13
MDA9
MDA12
MDA8

+1.5VGS

QSA[7..0]

<29>
<29>
<29>

CLKA0
CLKA0#
CKEA0

<29>
<29>
<29>
<29>
<29>

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

QSA#[7..0]

QSA#[7..0]

<29,31>

J7
K7
K9
K1
L2
J3
K3
L3

QSA3
QSA0

F3
C7

DQMA#3
DQMA#0

E7
D3

QSA#3
QSA#0

G3
B7

T2

DRAM_RST#

L8
J1
L1
J9
L9
M7

RV150
240_0402_1%
DIS@

ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

M2
N8
M3

CLKA0
CLKA0#
CKEA0

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

QSA2
QSA1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#2
DQMA#1

E7
D3

QSA#2
QSA#1

G3
B7

+1.5VGS

DRAM_RST# T2

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

UV21

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA38
MDA36
MDA39
MDA34
MDA35
MDA33
MDA37
MDA32

D7
C3
C8
C2
A7
A2
B8
A3

MDA42
MDA44
MDA40
MDA46
MDA43
MDA45
MDA41
MDA47

+1.5VGS
A_BA0
A_BA1
A_BA2

J1
L1
J9
L9
M7

RV151
240_0402_1%
DIS@

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

DIS@
CLKA0 1
RV154

CK
CK
CKE

B2
D9
G7
K2
K8
N1
N9
R1
R9

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

<29>
<29>
<29>

CLKA1
CLKA1#
CKEA1

<29>
<29>
<29>
<29>
<29>

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

J7
K7
K9
K1
L2
J3
K3
L3

QSA4
QSA5

F3
C7

DQMA#4
DQMA#5

E7
D3

QSA#4
QSA#5

G3
B7

DRAM_RST# T2

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFC_A4
VREFD_Q4

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA55
MDA51
MDA50
MDA52
MDA48
MDA53
MDA49
MDA54

D7
C3
C8
C2
A7
A2
B8
A3

MDA60
MDA58
MDA63
MDA56
MDA61
MDA59
MDA62
MDA57

+1.5VGS

M2
N8
M3

A_BA0
A_BA1
A_BA2

<29>

QSA[7..0]

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

M8
H1

J1
L1
J9
L9
M7

RV152
240_0402_1%
DIS@

<29>

DQMA#[7..0]

BA0
BA1
BA2

DQMA#[7..0]

A_BA0
A_BA1
A_BA2

<29>

M2
N8
M3

<29>
<29>
<29>

VREFC_A3
VREFD_Q3

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

M2
N8
M3

CLKA1
CLKA1#
CKEA1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

QSA6
QSA7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

QSA#6
QSA#7

G3
B7

+1.5VGS

DRAM_RST# T2

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VGS
A_BA0
A_BA1
A_BA2

M8
H1

J1
L1
J9
L9
M7

RV153
240_0402_1%
DIS@

VREFC_A1
VREFD_Q1

UV19

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU

RESET
ZQ
NC
NC
NC
NC
NC

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

2
56_0402_1%
DIS@

2
56_0402_1%

2
1

CV233
2
1

DIS@

VREFD_Q4

RV173
4.99K_0402_1%
DIS@

DIS@

CV232
1

1
RV172
4.99K_0402_1%
DIS@

DIS@

15mil

VREFC_A4

CV231
1

1
RV171
4.99K_0402_1%
DIS@

CV230
1

DIS@

1
2

CV229
1

1
2

CV228
1

CV227
1

1
2

CV226
1

1
2

1
2

DIS@

RV170
4.99K_0402_1%
DIS@

15mil

VREFD_Q3

0.1U_0402_16V7K

RV169
4.99K_0402_1%
DIS@

15mil

VREFC_A3

RV163
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

DIS@

15mil

VREFD_Q2

+1.5VGS

RV162
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

RV168
4.99K_0402_1%
DIS@

+1.5VGS

RV161
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

DIS@

15mil
0.1U_0402_16V7K

DIS@

RV167
4.99K_0402_1%
DIS@

+1.5VGS

RV160
4.99K_0402_1%
DIS@

VREFC_A2
0.1U_0402_16V7K

CV234
0.01U_0402_16V7K
DIS@

15mil

VREFC_A1
0.1U_0402_16V7K

RV166
4.99K_0402_1%
DIS@

0.1U_0402_16V7K

2
56_0402_1%

RV159
4.99K_0402_1%
DIS@

15mil

VREFD_Q1

+1.5VGS

RV158
4.99K_0402_1%
DIS@

15mil

2
56_0402_1%
DIS@

CLKA1# 1
RV165

RV157
4.99K_0402_1%
DIS@

DIS@

+1.5VGS

RV156
4.99K_0402_1%
DIS@
CLKA1 1
RV164

+1.5VGS

+1.5VGS

+1.5VGS

CV225
0.01U_0402_16V7K
DIS@

CLKA0# 1
RV155

+1.5VGS
+1.5VGS

2012/08/22

Deciphered Date

2013/08/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

1U_0402_6.3V6K
DIS@
CV271

1U_0402_6.3V6K
DIS@
CV270

1U_0402_6.3V6K
DIS@
CV269

1U_0402_6.3V6K
DIS@
CV268

1U_0402_6.3V6K
DIS@
CV267

1U_0402_6.3V6K
DIS@
CV266

1U_0402_6.3V6K
DIS@
CV265

1U_0402_6.3V6K
DIS@
CV264

1U_0402_6.3V6K
DIS@
CV263

Compal Secret Data

Security Classification
Issued Date

1U_0402_6.3V6K
DIS@
CV262

1U_0402_6.3V6K
DIS@
CV261

1U_0402_6.3V6K
DIS@
CV260

1U_0402_6.3V6K
DIS@
CV259

1U_0402_6.3V6K
DIS@
CV258

1U_0402_6.3V6K
DIS@
CV257

1U_0402_6.3V6K
DIS@
CV256

1U_0402_6.3V6K
DIS@
CV255

1U_0402_6.3V6K
DIS@
CV254

+1.5VGS

1U_0402_6.3V6K
DIS@
CV253

1U_0402_6.3V6K
DIS@
CV252

10U_0603_6.3V6M
DIS@
CV251

10U_0603_6.3V6M
DIS@
CV250

10U_0603_6.3V6M
DIS@
CV249

10U_0603_6.3V6M
DIS@
CV248

0.1U_0402_16V7K
DIS@
CV247

0.1U_0402_16V7K
DIS@
CV246

0.1U_0402_16V7K
DIS@
CV245

0.1U_0402_16V7K
DIS@
CV244

0.1U_0402_16V7K
DIS@
CV243

0.1U_0402_16V7K
DIS@
CV242

0.1U_0402_16V7K
DIS@
CV241

0.1U_0402_16V7K
DIS@
CV240

0.1U_0402_16V7K
DIS@
CV239

0.1U_0402_16V7K
DIS@
CV238

0.1U_0402_16V7K
DIS@
CV237

0.1U_0402_16V7K
DIS@
CV236

0.1U_0402_16V7K
DIS@
CV235

+1.5VGS

2
A

Compal Electronics, Inc.


ATI_ThamesXT_M2_VRAM_A

Size

Document Number

Rev
1.0

LA-9104P
Date:

Wednesday, August 29, 2012


1

Sheet

30

of

57

CHANNEL B: 256MB/512MB DDR3

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8

<29,30>

E7
D3

QSB#3
QSB#0

G3
B7

T2

DRAM_RST#

L8
1

DIS@
CLKB1 1
RV180

2
56_0402_1%

RV176
240_0402_1%
DIS@

DIS@

2
56_0402_1%

CLKB1# 1
RV181

J1
L1
J9
L9
M7

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CV273
0.01U_0402_16V7K
DIS@

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB2
QSB1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#2
DQMB#1

E7
D3

QSB#2
QSB#1

G3
B7

DRAM_RST# T2

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9
M7

RV177
240_0402_1%
DIS@

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

RV191
4.99K_0402_1%
DIS@

RV192
4.99K_0402_1%
DIS@

RESET
ZQ
NC
NC
NC
NC
NC

<29>
<29>
<29>

CLKB1
CLKB1#
CKEB1

<29>
<29>
<29>
<29>
<29>

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

K1
L2
J3
K3
L3

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

J7
K7
K9

DRAM_RST# T2

J1
L1
J9
L9
M7

RV178
240_0402_1%
DIS@

15mil

+1.5VGS

15mil

RV193
4.99K_0402_1%
DIS@

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB6
QSB7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

+1.5VGS

DRAM_RST# T2

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

15mil

J1
L1
J9
L9
M7

RV179
240_0402_1%
DIS@

15mil

CK
CK
CKE
ODT
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ
NC
NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9
C

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

RV189
4.99K_0402_1%
DIS@

15mil

15mil

VREFC_A4_B
RV196
4.99K_0402_1%
DIS@

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

+1.5VGS

VREFD_Q3_B

RV195
4.99K_0402_1%
DIS@

BA0
BA1
BA2

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

RV188
4.99K_0402_1%
DIS@

VREFC_A3_B

+1.5VGS
B_BA0
B_BA1
B_BA2

+1.5VGS

RV187
4.99K_0402_1%
DIS@

RV194
4.99K_0402_1%
DIS@

BA0
BA1
BA2

+1.5VGS

VREFD_Q2_B

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

RV186
4.99K_0402_1%
DIS@

1
1

DML
DMU

DQSL
DQSU

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFC_A2_B

0.1U_0402_16V7K
DIS@
CV275

VREFC_A1_B

0.1U_0402_16V7K
DIS@
CV274

1
2

RV190
4.99K_0402_1%
DIS@

ODT
CS
RAS
CAS
WE

RV185
4.99K_0402_1%
DIS@

0.1U_0402_16V7K
DIS@
CV276

15mil

VREFD_Q1_B

CK
CK
CKE

+1.5VGS

RV184
4.99K_0402_1%
DIS@

15mil

MDB44
MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB42

M8
H1

+1.5VGS

M2
N8
M3

B_BA0
B_BA1
B_BA2

+1.5VGS

RV183
4.99K_0402_1%
DIS@

RV182
4.99K_0402_1%
DIS@

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

96-BALL
SDRAM DDR3L
K4W2G1646E-BC11_FBGA96~D

+1.5VGS

+1.5VGS

D7
C3
C8
C2
A7
A2
B8
A3

VREFC_A4_B
VREFD_Q4_B

VREFD_Q4_B
0.1U_0402_16V7K
DIS@
CV281

CV272
0.01U_0402_16V7K
DIS@

DQMB#3
DQMB#0

DQSL
DQSU

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38

2
56_0402_1%

F3
C7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

E3
F7
F2
F8
H3
H8
G2
H7

DIS@
CLKB0# 1
RV175

QSB3
QSB0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2
56_0402_1%

ODT
CS
RAS
CAS
WE

CLKB0
CLKB0#
CKEB0

+1.5VGS

BA0
BA1
BA2

DIS@
CLKB0 1
RV174
C

K1
L2
J3
K3
L3

M2
N8
M3

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

CK
CK
CKE

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

<29>
<29>
<29>
<29>
<29>

J7
K7
K9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

UV25

VREFCA
VREFDQ

+1.5VGS
B_BA0
B_BA1
B_BA2

CLKB0
CLKB0#
CKEB0

B2
D9
G7
K2
K8
N1
N9
R1
R9

<29>
<29>
<29>

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

QSB#[7..0]

BA0
BA1
BA2

0.1U_0402_16V7K
DIS@
CV277

QSB#[7..0]

M2
N8
M3

B_BA0
B_BA1
B_BA2

<29>

<29>
<29>
<29>

QSB[7..0]

M8
H1

+1.5VGS
QSB[7..0]

<29>

VREFC_A3_B
VREFD_Q3_B

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB16
MDB19
MDB20
MDB22
MDB17
MDB21
MDB18
MDB23

RV197
4.99K_0402_1%
DIS@

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

E3
F7
F2
F8
H3
H8
G2
H7

MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

D7
C3
C8
C2
A7
A2
B8
A3

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

UV24

VREFCA
VREFDQ

DQMB#[7..0]

DQMB#[7..0]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M8
H1

<29>

MAB[14..0]

VREFC_A2_B
VREFD_Q2_B

0.1U_0402_16V7K
DIS@
CV279

<29>

MAB[14..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

MDB29
MDB26
MDB30
MDB27
MDB31
MDB25
MDB28
MDB24

E3
F7
F2
F8
H3
H8
G2
H7

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

MDB[0..63]

MDB[0..63]

UV23

VREFCA
VREFDQ

M8
H1

0.1U_0402_16V7K
DIS@
CV278

<29>

VREFC_A1_B
VREFD_Q1_B

0.1U_0402_16V7K
DIS@
CV280

UV22

+1.5VGS
+1.5VGS

2012/08/22

Deciphered Date

2013/08/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

1U_0402_6.3V6K
DIS@
CV318

1U_0402_6.3V6K
DIS@
CV317

1U_0402_6.3V6K
DIS@
CV316

1U_0402_6.3V6K
DIS@
CV315

1U_0402_6.3V6K
DIS@
CV314

1U_0402_6.3V6K
DIS@
CV313

1U_0402_6.3V6K
DIS@
CV312

1U_0402_6.3V6K
DIS@
CV311

Compal Secret Data

Security Classification
Issued Date

1U_0402_6.3V6K
DIS@
CV310

1U_0402_6.3V6K
DIS@
CV308

1U_0402_6.3V6K
DIS@
CV307

1U_0402_6.3V6K
DIS@
CV306

1U_0402_6.3V6K
DIS@
CV305

1U_0402_6.3V6K
DIS@
CV304

1U_0402_6.3V6K
DIS@
CV303

1U_0402_6.3V6K
DIS@
CV302

1U_0402_6.3V6K
DIS@
CV301

+1.5VGS

1U_0402_6.3V6K
DIS@
CV300

1U_0402_6.3V6K
DIS@
CV299

10U_0603_6.3V6M
DIS@
CV298

10U_0603_6.3V6M
DIS@
CV297

10U_0603_6.3V6M
DIS@
CV296

10U_0603_6.3V6M
DIS@
CV295

0.1U_0402_16V7K
DIS@
CV294

0.1U_0402_16V7K
DIS@
CV293

0.1U_0402_16V7K
DIS@
CV292

0.1U_0402_16V7K
DIS@
CV291

0.1U_0402_16V7K
DIS@
CV290

0.1U_0402_16V7K
DIS@
CV289

0.1U_0402_16V7K
DIS@
CV288

0.1U_0402_16V7K
DIS@
CV287

0.1U_0402_16V7K
DIS@
CV286

0.1U_0402_16V7K
DIS@
CV285

0.1U_0402_16V7K
DIS@
CV284

0.1U_0402_16V7K
DIS@
CV283

0.1U_0402_16V7K
DIS@
CV282

+1.5VGS

2
A

Compal Electronics, Inc.


ATI_ThamesXT_M2_VRAM_B

Size

Document Number

Rev
1.0

LA-9104P
Date:

Wednesday, August 29, 2012


1

Sheet

31

of

57

W=40mils

+3VALW

JP3

+LAN_IO rising time : >1ms and <100ms

W=40mils

2MM
QL1
+LAN_IO

1
CL18

1
CL27

2
G

WOL_EN#

RL27
1.5M_0402_5%

RL19 2 75_0603_5%

RL20 2 75_0603_5%

Place close to TCT pin

CL33
100P_1206_2KV8J

@
DL11
PESD5V0U2BT_SOT23-3~D

+LAN_VDD

1
CL25
@

1
CL26

0.1U_0402_16V7K

1
CL24
@

0.1U_0402_16V7K

1
CL23
@

0.1U_0402_16V7K

1
CL22

0.1U_0402_16V7K

1
CL21
@

0.1U_0402_16V7K

1
CL20

0.1U_0402_16V7K

0.1U_0402_16V7K

QL2
2N7002BKW_SOT323-3~D

MCT1

These caps close to Pin 12,27,39,42,47,48


For 8105E-VD pop the capacitor close pin 27,39,47,48

CL39
0.1U_0603_50V_X7R

EN_WOL

MCT0

1
CL17

0.1U_0402_16V7K

0.1U_0402_16V7K

1
CL16

0.1U_0402_16V7K

RL18
470K_0402_5%

RL28
10K_0402_5%

WOL_EN#

1
CL19

0.1U_0402_16V7K

0.1U_0402_16V7K

CL15

0.1U_0402_16V7K

SI3456DDV-T1-GE3_TSOP6~D

+3VALW

<40>

1.5A

W=40mils
4

B+_BIAS

6
5
2
1

CL38
1U_0402_6.3V6K

TL1

1
2
3
4
5
6
7
8

MDI1MDI1+

MDI0MDI0+

2
C

<14>
<14>

CL28 1

2 0.1U_0402_16V7K PCIE_CRX_C_DTX_P0

22

CL30 1

2 0.1U_0402_16V7K PCIE_CRX_C_DTX_N0

23
17
18

PCIE_PTX_LANRX_P1
PCIE_PTX_LANRX_N1
<14>

16

LAN_CLKREQ#

<16,38,40,6>
<14>
<14>

25

PLT_RST#

19
20

CLK_PCIE_LAN
CLK_PCIE_LAN#
XTLO

43

XTLI

44

PCIE_WAKE#

28

HSOP
HSON

LED3/EEDO
LED1/EESK
LED0

HSIP
HSIN

EECS/SCL
EEDI/SDA

CLKREQB

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

PERSTB
REFCLK_P
REFCLK_N

10K_0402_5%
2
RL34 1

PCIE_WAKE#

ISOLATEB

26

PCIE_WAKE#

14
15
38

CKXTAL2

DVDD10
DVDD10
DVDD10

+LAN_VDDREG

1 RL31

2 2.49K_0402_1%

33
34
35
46
24
49

+3VS

RL23 1
RL24 1

ISOLATEB

DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

ENSWREG
EVDD10
VDDREG
VDDREG

AVDD10
AVDD10
AVDD10
AVDD10

RSET
GND
PGND

REGOUT

1
2
4
5
7
8
10
11
13
29
41

RL30
2

12P_0402_50V8J
XTAL@

+LAN_VDD

YL2

1
3

27
39

CL37
1
2

12
42
47
48

+LAN_IO

1
21

+LAN_EVDD10

3
6
9
45

RL26
@

1
CL34

36

CL35

7
MDO1-

+LAN_IO
RL35
15K_0402_5%

WOL_EN#

3.3V : Enable switching regulator


: Disable switching regulator
0V

100@ (LDO mode used)

2
4
XTLO

JLAN

GND

S IC RTL8105E-VD-CGT QFN 48P LAN CTRL

LAN_CLKREQ#

GND

OSC

+LAN_EVDD10

0_0603_1%
+LAN_VDD

OSC

12P_0402_50V8J
XTAL@

W=20mils

+LAN_VDD

0_0402_5%
1
XTLI
XTAL@

25MHZ_10PF_7V25000014

ISOLATEB

0_0402_1%

XTAL@
CL36
1
2

1
RL36

X'FORM_ NS0014
CL41
0.01U_0402_16V7K

MDI0+
MDI0MDI1+
MDI1-

MCT1
MDO0MDO0+

2 10K_0402_5%
2 10K_0402_5%

RL33
1K_0402_5%

ENSWREG

DL11 as close as
possible to C27
and C32

LANWAKEB

ENSWREG

30
32

CKXTAL1

+LAN_IO
<15,40>

31
37
40

MDO1MDO1+
MCT0

MDO1+

MDO0-

MDO0+

RJ45 Conn.
<14>

XTLI

RL21 GCLK@
0_0402_5%

PR4+

RL39 @
22_0402_5%

PR2PR3PR3+
PR2+
PR1PR1+

@
RL37 10K_0402_5%
1
2

SHLD1
SHLD2

RL38 10K_0402_5%
1
2
@

CLK_LAN_25M

CLK_LAN_25M

PR4-

PCIE_PRX_LANTX_N1

16
15
14
13
12
11
10
9

PCIE_PRX_LANTX_P1

<14>

These caps close to Pin 3,6,9,13,29,41,45


For 8105E-VD pop capacitor close to pin 13,29,45

RX+
RXCT
NC
NC
CT
TX+
TX-

1U_0402_6.3V6K

<14>

UL1

0.1U_0402_16V7K

CL28,C30 Close UL1

RD+
RDCT
NC
NC
CT
TD+
TD-

9
10

SANTA_130456-311
CONN@

SP011207090
DC234004V00 (OLD)

Reserve 10K pull LAN_IO

10/100

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

LAN RTL8105E
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

32

of

57

+5VA

JACK_SENSE#

RA1 @

+5VS

0_0603_1%

RA2 @
100K_0402_5%

RA204
@

10K_0402_5%

QA4A @
DMN66D0LDW-7_SOT363-6

QA4B @

DMN66D0LDW-7_SOT363-6

0_0603_1%

+3VS

CA71
4.7U_0603_6.3V6K

RA203
2
@
CA51
0.1U_0402_16V7K

CA53
10U_0603_6.3V6M

+3VS
+5VS

+5VA

CA54
0.1U_0402_16V7K

CA55
10U_0603_6.3V6M

CA56
0.1U_0402_16V7K

+5V_PVDD

+5V_PVDD
+5V_PVDD

JACK_PLUG Delay cricutis

+3VS

JACK_PLUG#

CA2

UA1

+3VS

CA59 1

RA9 1
RA10 1

0.1U_0402_16V7K

HDA_BITCLK

8
5
6
10
11

2.2U_0603_6.3V6K
20K_0402_1%

28
15

2 22_0402_5%

1
CA23
RA153 1

2
2

CA24 1
CA25 1

RA49 1

2 0_0402_5%

+MIC2-VREFO

+MIC2-VREFO

RA50 1

CA62 1
CA63 1
CA64 1

2 0_0402_1%
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M
2 10U_0603_6.3V6M

SENSE B
SENSE A

CBP
CBN
CPVEE

SPK-OUT-R+
SPK-OUT-RSPK-OUT-LSPK-OUT-L+

MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO
LDO1-CAP
LDO2-CAP
LDO3-CAP

HPOUT-R(PORT-I-R)
HPOUT-L(PORT-I-L)
SPDIF-OUT/GPIO2

PDB

2
PC_BEEP
1K_0402_1%

RA79

16
1

@ CA365

CA1 @
10U_0603_6.3V6M

2 100P_0402_50V8J

@ RA81 2

24
23

10U_0603_6.3V6M

1 10K_0402_5%

22
21
20
19

JACK_PLUG#

RA4

2 4.7U_0603_6.3V6K
2 4.7U_0603_6.3V6K

14
13

RA51 1

45
44
43
42

INT-SPK-R+
INT-SPK-RINT-SPK-LINT-SPK-L+

33
32

RA23

2 39.2K_0402_1%

1 1K_0402_1%

MIC_IN

JACK_SENSE#
+MIC2-VREFO

RA53
2.2K_0402_5%

HPOUT-R
HPOUT-L
RA1107
22K_0402_1%
1
2

48
2
3

MIC_DATA
MIC_CLK_C

47

EC_MUTE#

JACK_SENSE#
0_0402_1%

Reserve for cancel Delay cricutis

@
CA67 1
CA66 1

18
17

MIC_IN

MIC_IN

MIC_DATA
EC_MUTE#

<21>
<40>

Thermal PAD

CA70
10U_0603_6.3V6M

GPIO0/DMIC-DATA
GPIO1/DMIC-CLK

DVSS
AVSS1
AVSS2

49
22P_0402_50V8J

MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)

VREF
JDREF

4
25
38

CA21

MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)

27
39
7

HDA_BITCLK_AUDIO

LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

SDATA-IN
SDATA-OUT
BCLK
SYNC
RESETB

31
30
29

Place close to UA1.11

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)

DVDD-IO
AVDD2

37
35
34

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

MONO-OUT

DVDD
CPVDD

9
40

CA61
4.7U_0603_6.3V6K
2 22_0402_5%

RA129

HDA_RST_AUDIO#
CA68

2 0_0402_1%
2 0_0402_5%

RA130

HDA_SDIN0
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#

@
@

AVDD1
PVDD1
PVDD2

1
36

0.1U_0402_16V7K

PCBEEP

26
41
46

4.7U_0603_6.3V6K

+1.5VS
+3VS

<13>
<13>
<13>
<13>
<13>

CA60

CA65 1
0.1U_0402_16V7K

CA57

4.7U_0603_6.3V6K

0.1U_0402_16V7K

CA59, CA60
Close to UA1
Pin36

12

RA3 @
100K_0402_5%

2
RA131
22_0402_5%

MIC_CLK

2 0_0603_1%

RA28 1

2 0_0603_1%

RA29 1

2 0_0603_1%

RA30 1

2 0_0603_1%

RA31 1

2 0_0603_1%

RA32 1

2 0_0603_1%

RA1108
22K_0402_1%

GNDA

GND

Place on the moat between GND & GNDA.

ALC3221-CG_MQFN48_6X6~D
MIC_CLK_C

RA25 1

CA58

MIC_CLK

<21>

CA22 @
DA8

22P_0402_50V8J

EC Beep

<40>

BEEP#

CA41
1
2

1
<13>

HDA_SPKR

ICH Beep

BAT54C-7-F_SOT23-3
@

RA19
10K_0402_5%

PC Beep

PC_BEEP

0.1U_0402_16V7K

Speaker 8 ohm : 20mil

2
4

Speaker 4 ohm : 40mil

1000P_0402_50V7K

FBMA-L10-160808-800LMT_2P
1
AUD_HP_OUT_L_CN
FBMA-L10-160808-800LMT_2P
1 AUD_HP_OUT_R_CN
1
AUD_HP_NB_SENSE_R
0_0402_1%

1000P_0402_50V7K
CA32

CONN@

CA29

1000P_0402_50V7K
CA31

LA9

2
2
RA21

JSPK

1
2
3
4
1000P_0402_50V7K
CA30

HPOUT-R RA56 1

LA8

close to Codec

EMC@

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
DA6
AZ5125-02S.R7G_SOT23-3

18_0402_5%
2
AUD_HP_OUT_LL
18_0402_5%
2
AUD_HP_OUT_RL
JACK_PLUG#

HPOUT-L RA55 1

0_0603_5%~D
0_0603_5%~D
0_0603_5%~D
0_0603_5%~D

Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-RJHP

2
2
2
2

DA5
AZ5125-02S.R7G_SOT23-3

LA7
FBMA-L10-160808-800LMT_2P
MIC_IN

1
1
1
1

iPhone type Combo Jack

LA3
LA4
LA5
LA6

INT-SPK-RINT-SPK-R+
INT-SPK-LINT-SPK-L+

Close to UA1
Pin11,13,14,16

1
2
3 GND
4 GND

5
6

E&T_3703-Q04N-11R
CONN@

SP02000H300

EMC@

3
1

3
1

EMC@

DA12
AZ5125-02S.R7G_SOT23-3

DA10
AZ5125-02S.R7G_SOT23-3

CA38
100P_0402_50V8J

CA33
100P_0402_50V8J

CA39
100P_0402_50V8J

SINGA_2SJ-E960-001F
A

DC230007Y00
DC021103300 (OLD)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EMC@

Date:

Audio Codec ALC3221


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

33

of

57

SD_CD#

MS_INS#
CR9

+3VS

RR8

1
RR7

USB20_CR_N10_R

UR1

RR12

1 6.19K_0402_1%

RREF

2
0_0402_5%
2
3

USB20_CR_N10_R
USB20_CR_P10_R

2
0_0402_5%

RREF
DM
DP

SP14
SP13
SP12
SP11
SP10
SP9
SP8

RTS5179-GR_QFN24

V18

SDREG
V18

25

CR4

CR3

6
24

XD_CD#
XD_D7
GPIO0

1U_0402_6.3V6K

CR1
0.1U_0402_16V7K

1U_0402_6.3V6K

+3VS

SP7
SP6
SP5
SP4
SP3
SP2
SP1

Thermal pad

7
23
17

22
21
20
19
18
16
15

14
13
12
11
10
9
8

MS_BS
SD_D2
MS_D1_SD_D3

close to chip side

SD_CMD
MS_D0
MS_D2_SD_CLK_R

RR2

2 0_0402_5%

MS_D2_SD_CLK

RR3

2 0_0402_5%

MS_CLK_SD_WP

MS_D2_SD_CLKConn pin 13 SD_CLK


Viapin 10 MS_D2

SD_CD#
MS_D3
SD_D0
SD_D1
MS_INS#
MS_CLK_SD_WP_R

1
RTS5179-GR_QFN24_4X4

CR6

3
EMC@

For ESD request.


Place close to UR1

Trace width:40mil

USB20_CR_P10_R

5P_0402_50V8C

4
LR2

CR5

CR10
0.1U_0402_16V7K

5P_0402_50V8C

USB20_CR_N10

WCM-2012HS-900T_4P
2
1
2

USB20_CR_N10

<16>

USB20_CR_P10

3V3_IN

USB20_CR_P10

+VCC_3IN1

CARD_3V3

<16>

0.1U_0402_16V7K

CR2

MS_CLK_SD_WPConn pin 5 MS_CLK


Viapin 20 SD_W

+VCC_3IN1

4.7U_0603_6.3V6K
+VCC_3IN1
JREAD
SD_D2
MS_D1_SD_D3

MS_CLK_SD_WP
SD_CMD
MS_D3
MS_INS#

CR8
4.7U_0603_6.3V6K

CR7

RR4

0.1U_0402_16V7K

10K_0402_5%
MS_D2_SD_CLK

MS_D0
MS_D1_SD_D3
MS_D2_SD_CLK
MS_BS

Close to JREAD1

SD_D0
SD_D1
SD_CD#
MS_CLK_SD_WP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SD-DAT2
MS-VSS1
SD-CD/DAT3 MMC-RSV
MS-VCC
MS-SCLK
SD-CMD MMC-CMD
MS-DATA3
MS-INS
SD-VSS MMC-VSS1
MS-DATA2
SD-VDD MMC-VDD
MS-DATA0
MS-DATA1
SD-CLK MMC-CLK
MS-BS
MS-VSS2
SD-VSS MMC-VSS2
SD-DAT0 MMC-DAT
SD-DAT1
SD-CD
SD-GND
GND1
SD-WP(SW)
GND2

23
24

T-SOL_143-2300302602_RV
CONN@
SD_CMD

SP071204100
LTCX004AK00

CR11
10P_0402_50V8J

For ESD request.


Place close to JREAD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Card Reader RTS5179


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

34

of

57

+5VALW to +5VS
QZ1
SI4128DY-T1-GE3_SO8

2
3

CZ13
10U_0805_10V6K

2
1

RZ11
10K_0402_5%
@

0.1U_0402_16V7K

PCH_PWR_EN#

PCH_PWR_EN#

D
<40>

PCH_PWR_EN

RZ17
100K_0402_5%

Please close to QZ9

+1.5V To +1.5VS
B+_BIAS

RZ19
100K_0402_5%
SYSON#

2
1

<40,50>

RZ27
470_0402_5%

2
SYSON#

3
QZ14B
SUSP

2
G

2N7002DW-7-F_SOT363-6

6
QZ14A
PCH_PWR_EN#

2N7002DW-7-F_SOT363-6

3
5
4

6
1

2N7002DW-7-F_SOT363-6

CZ26 @
0.1U_0402_16V7K
1
2

QZ13B
SUSP

QZ12
2N7002K_SOT23-3

RZ22
100K_0402_5%

+1.5V_D

+3VS_D

SUSP

+3V_D

QZ13A

+VCCP_D

+1.5VS_D

CZ25 @
0.1U_0402_16V7K
+5VALW

SYSON

470_0402_5%

RZ26

470_0402_5%

470_0402_5%

CZ24 @
0.1U_0402_16V7K
1
2

RZ25

CZ21
0.1U_0603_50V_X7R

1
RZ24

470_0402_5%

CZ22
0.1U_0402_25V6K

+3VS
+1.5V

+5VALW

+3VS

+3V_PCH

+VCCP

+1.5VS

RZ23

RZ21

2M_0402_5%~D

1
2

2
1
3

0.1U_0402_16V7K

2
0_0402_1%
1

QZ11
2N7002BKW_SOT323-3~D

CZ20
0.1U_0603_50V_X7R

1
@
RZ20

CZ18

+5VALW

2N7002DW-7-F_SOT363-6

+1.5VS
SI4634DY-T1-E3_SO8~D
8
1
7
2
6
3
5

CZ19
10U_0805_10V6K

RZ18
470K_0402_5%

2
G

UZ1
+1.5V

SUSP

QZ10
2N7002K_SOT23-3

RZ16
100K_0402_5%

RZ15

RZ12
100K_0402_5%
<19>

QZ8
2N7002K_SOT23-3

2M_0402_5%~D

SUSP#

SUSP

QZ9
2N7002K_SOT23-3

<10,40,48,49,50>

CZ17
0.1U_0603_50V_X7R

CZ23
2

RZ10
100K_0402_5%

CZ16
0.1U_0603_50V_X7R

CZ15
0.1U_0603_50V_X7R

D
G

1
CZ14
1U_0603_10V6K

SUSP

Reserve for ESD

+5VALW
+3VALW

56K_0402_5%

RZ14
39.2K_0402_1%

RZ13

+5VALW

SUSP

B+_BIAS

QZ6
2N7002BKW_SOT323-3~D

CZ12
10U_0805_10V6K

2
G

RUN_ON_CPU1.5VS3#

RZ9

CZ11
10U_0805_10V6K

QZ5
2N7002BKW_SOT323-3~D
2
G

<10,6>

+3VS

1
2
3

CZ8
1U_0603_10V6K

2
0_0402_1%

+3VALW to +3VS
QZ7
SI4128DY-T1-GE3_SO8

1
RZ8

1
2
RZ7
470K_0402_5%

G
QZ4
2N7002K_SOT23-3

8
7
6
5

CZ7
10U_0805_10V6K

DMN66D0LDW-7_SOT363-6

B+_BIAS

RZ2
22_0603_5%~D

RZ3
220_0402_5%

CZ6
10U_0805_10V6K

+0.75VS

40mil

1
2
3

CZ10
0.1U_0603_50V_X7R

CZ5
10U_0805_10V6K

SUSP

8
7
6
5

PCH_PWR_EN#

+3VALW

+1.5V_CPU_VDDQ
+3V_PCH

2M_0402_5%~D

6
2

2
1

3
QZ2B

SUSP

DMN66D0LDW-7_SOT363-6

QZ2A
@
RZ6
1.5M_0402_5%

+DDR_CHG

+1.5V_CPU_VDDQ_CHG

56K_0402_5%

2
0_0402_1%

CZ9
0.1U_0603_50V_X7R

1
RZ5

B+_BIAS

+5VS_D

RZ4

JUMP_43X79
QZ3
SI4128DY-T1-GE3_SO8

RZ1
470_0603_5%

CZ4

JP2

CZ3

CZ2
10U_0805_10V6K

+3VALW

1
2
3

1U_0603_10V6K

1
CZ1
10U_0805_10V6K

+3VALW to +3V_PCH

10U_0805_10V6K

8
7
6
5

+5VS

+5VALW

QZ15
2N7002BKW_SOT323-3~D

CZ27 @
0.1U_0402_16V7K
+3VS

CZ28 @
0.1U_0402_16V7K
+3VS

+1.05VS

CZ29 @
0.1U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Reserve for ESD

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DC/DC Interface
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
E

Sheet

35

of

57

+5VALW

WCM-2012HS-900T_4P
3
4
3

USB3RN2_JUSB1_R
D

2
1
2
LI1 EMC@
1
2
@ RI1
0_0402_5%
1

USB3RP2_JUSB1_R
CI12
4.7U_0805_10V4Z

CI14

@ RI2

1 USB3TP2_JUSB1_C
0.01U_0402_16V7K

WCM-2012HS-900T_4P
3
4
3

1
LI3 EMC@
1
@ RI4
1

USB3TN2_JUSB1_R

USB3TP2_JUSB1_R

2
0_0402_5%

+5V_USB_PWR1

80mil

JUSB1

RI19

9
1
8
3
7
2
6
4
5

USB3TP2_JUSB1_R

0_0402_1%
1
2

USB_OC1#

<16>

CI15
CI1

AP2301MPG-13_MSOP8

DI1

2
0_0402_5%

@ RI6

8
7
6
5

VOUT
VOUT
VOUT
FLG

0.1U_0402_16V7K
220U_6.3V_M

USB3TN2_JUSB1_R
USB20_JUSB1_P1_R

EMC@

USB3RN2_JUSB1_R

10

USB3RN2_JUSB1_R

USB3RP2_JUSB1_R

USB3RP2_JUSB1_R

USB3TN2_JUSB1_R

USB3TN2_JUSB1_R

USB3TP2_JUSB1_R

USB3TP2_JUSB1_R

USB20_JUSB1_N1_R
USB3RP2_JUSB1_R
DI2
PESD5V0U2BT_SOT23-3~D

2
USB3TP2_JUSB1
CI4

USB3TP2_JUSB1

1 USB3TN2_JUSB1_C
0.01U_0402_16V7K

CI13
0.1U_0402_16V7K

<16>

2
USB3TN2_JUSB1
CI3

GND
VIN
VIN
EN

CI2
0.1U_0402_25V6K

USB_EN#

1
2
3
4

USB_EN#

1
USB3TN2_JUSB1

+5V_USB_PWR1

UI3

<37,40>

<16>

USB conn.1

2.0A

0.1U_0402_16V7K

2
0_0402_5%

USB3RP2_JUSB1

USB3RP2_JUSB1

<16>

USB3RN2_JUSB1

EPAD

USB3RN2_JUSB1

<16>

USB3RN2_JUSB1_R

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

ACON_TARA4-9K1311
CONN@
USB 2.0 Port 1
USB 3.0 Port 2

DC233007O10
DC231204030 (OLD)

EMC@

<16>

USB20_JUSB1_N1

<16>

USB20_JUSB1_P1

USB20_JUSB1_N1

WCM-2012HS-900T_4P
4
3
4
3

USB20_JUSB1_N1_R

USB20_JUSB1_P1

USB20_JUSB1_P1_R

3
8

1
LI2 EMC@
1
@ RI3

USB3RP1_JUSB2

WCM-2012HS-900T_4P
3
4
3

USB3RP1_JUSB2_R

1
2
LI4 EMC@
1
2
@ RI13
0_0402_5%
1
@ RI14

+5VALW

USB3RN1_JUSB2_R

CI6
4.7U_0805_10V4Z

CI7

1
2
3
4

USB_EN#

1 USB3TN1_JUSB2_C
0.01U_0402_16V7K

CI26

8
7
6
5

VOUT
VOUT
VOUT
FLG

80mil
B

0_0402_1%
1
2
RI20

USB_OC0#

USB conn.2

<16>

CI17

AP2301MPG-13_MSOP8

0.1U_0402_16V7K
+5V_USB_PWR2
JUSB2
USB3TP1_JUSB2_R

WCM-2012HS-900T_4P
3
4
3

USB3TN1_JUSB2_R

CI8

USB3TP1_JUSB2

1 USB3TP1_JUSB2_C
0.01U_0402_16V7K

1
LI6 EMC@
1
@ RI17
1
@ RI18

USB3TP1_JUSB2_R
DI4

2
0_0402_5%
2
0_0402_5%

EMC@

USB3RN1_JUSB2_R

10

USB3RN1_JUSB2_R

USB3RP1_JUSB2_R

USB3RP1_JUSB2_R

USB3TN1_JUSB2_R

USB3TN1_JUSB2_R

USB3TP1_JUSB2_R

USB3TP1_JUSB2_R

<16>

2
USB3TP1_JUSB2
CI11

USB3TN1_JUSB2_R
USB20_JUSB2_P0_R

<16>

USB20_JUSB2_N0

<16>

USB20_JUSB2_P0

USB20_JUSB2_N0

USB20_JUSB2_P0

USB3RN1_JUSB2_R

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

CONN@

GND
GND
GND
GND

10
11
12
13

ACON_TARA4-9K1311
USB 2.0 Port 0
USB 3.0 Port 1

DC233007O10
DC231204030 (OLD)

8
USB20_JUSB2_N0_R
IP4292CZ10-TBR_XSON10_2.5X1~D

USB20_JUSB2_P0_R

1
LI5 EMC@
1
@ RI15

2
0_0402_5%

1
@ RI16

2
0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

9
1
8
3
7
2
6
4
5

EMC@

WCM-2012HS-900T_4P
3
4
3

USB20_JUSB2_N0_R
USB3RP1_JUSB2_R
DI5
PESD5V0U2BT_SOT23-3~D

220U_6.3V_M

CI9
0.1U_0402_25V6K

2
USB3TN1_JUSB2
CI10

GND
VIN
VIN
EN

0.1U_0402_16V7K

USB3TN1_JUSB2

+5V_USB_PWR2

UI2

<16>

2.0A

0.1U_0402_16V7K

2
0_0402_5%

USB3RP1_JUSB2

USB3RN1_JUSB2

<16>

USB3RN1_JUSB2

2
0_0402_5%
2
0_0402_5%

@ RI5

<16>

IP4292CZ10-TBR_XSON10_2.5X1~D

EPAD

USB3.0
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

36

of

57

+5VALW

CI23

4.7U_0805_10V4Z

CI22

2.0A

0.1U_0402_16V7K

+5V_USB_PWR3

0.1U_0402_16V7K

8
7
6
5

80mil
0_0402_1%
1
2
RI24

USB_OC2#

USB conn.3

<16>

CI24

AP2301MPG-13_MSOP8

0.1U_0402_16V7K
+5V_USB_PWR3
+5V_USB_PWR3
JUSB3

USB20_JUSB3_P2_R

USB20_JUSB3_N2

USB20_JUSB3_N2_R

USB20_JUSB3_P2

1
LI7 EMC@
1
@ RI25

2
0_0402_5%

1
@ RI21

2
0_0402_5%

1
CI20
220U_6.3V_M

ACON_UARBG-4K1926
CONN@

EMC@

WCM-2012HS-900T_4P
4
3
4
3

VBUS
DD+
GND
GND
GND
GND
GND

CI19
0.1U_0402_25V6K

USB20_JUSB3_P2
USB20_JUSB3_N2

DI7
PESD5V0U2BT_SOT23-3~D

<16>
<16>

1
2
3
4
5
6
7
8

USB20_JUSB3_N2_R
USB20_JUSB3_P2_R

CI16

VOUT
VOUT
VOUT
FLG

USB_EN#

GND
VIN
VIN
EN

<36,40>

USB_EN#

EPAD

UI4

1
2
3
4

USB 2.0 Port 2

Place close to JUSB3

DC233007P00
DC233007P00(OLD)
C

+5VALW

CI31
4.7U_0805_10V4Z

CI30

2.0A

0.1U_0402_16V7K

+5V_USB_PWR4
B

2
0_0402_5%

1
@ RI28

2
0_0402_5%

USB_EN#
USB20_USBDB_N3_R

CI25
0.1U_0402_16V7K

1
LI10 EMC@
1
@ RI32

USB20_USBDB_P3_R

GND
VIN
VIN
EN

VOUT
VOUT
VOUT
FLG

80mil
0_0402_1%
1
2
RI31

USB_OC3#

USB conn.4

<16>

CI32

AP2301MPG-13_MSOP8

0.1U_0402_16V7K

+5V_USB_PWR4
JDB

USB20_USBDB_P3_R
USB20_USBDB_N3_R

USB20_USBDB_N3

WCM-2012HS-900T_4P
3
4
3

8
7
6
5

USB20_USBDB_P3
USB20_USBDB_N3

<16>
<16>

USB20_USBDB_P3

1
2
3
4

EPAD

UI5

DI8
PESD5V0U2BT_SOT23-3~D

CI27

220U_6.3V_M

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

G1
G2

9
10

ACES_51524-0080N-001
CONN@
USB 2.0 Port 3

SP01001A900

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

MB to USB2.0 DB
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

37

of

57

Mini WLAN/WIMAX H=6.7


+3V_WLAN

+3V_WLAN

R13

@
@

1 1K_0402_1%

GND1 GND2

1
USB20_MINI1_N8
USB20_MINI1_P8

USB20_MINI1_N8
USB20_MINI1_P8

3
<16>
<16>

<40>

WLAN_ON

WLAN_ON

54

@ R17
20K_0402_5%

R18
100K_0402_5%
@

R11

CONCR_525B01BE17A
CONN@

100K_0402_5%

@
Q4A
DMN66D0LDW-7_SOT363-6

PCH_SMBCLK
<11,12,14,6>
PCH_SMBDATA <11,12,14,6>

PCH_SMBCLK
PCH_SMBDATA

6
5
2
1

QV30
2N7002_SOT23-3

<16>

WL_OFF#

WL_OFF#

<16,32,40,6>

2
G
1

PLT_RST#

WLAN_RADIO_DIS#_R
1
PLT_RST#
0_0402_1%

1
1

BT_ON#

R14
R15

2
R16

+3V_AOAC
Q2 @
SI3456DDV-T1-GE3_TSOP6~D

B+_BIAS

+3VALW

EC_TX
EC_RX

EC_TX
EC_RX

+3VALW

53

0.1U_0402_10V7K~D
2 PCIE_PRX_WLANTX_N2_C
2 PCIE_PRX_WLANTX_P2_C
0.1U_0402_10V7K~D

+3VS
R110
10K_0402_5%

R21
1M_0402_5%

BT_ON#

2 0_0402_1%
2 0_0402_1%

WLAN_CLKREQ#
CLK_PCIE_WLAN#
CLK_PCIE_WLAN

PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

<40>
<40>
<17>

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

+3VS

C13
4700P_0402_25V7K

PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

WLAN_CLKREQ#

<14>
<14>

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R19
DMN66D0LDW-7_SOT363-6
100K_0402_5%
Q4B

<14>
<14>

<14>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R20
100K_0402_5%

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2

WLAN_WAKE#

@
1
0_0402_5%
C49
1
PCIE_PRX_WLANTX_N2
1
PCIE_PRX_WLANTX_P2
C44

BT_ON# 2
R12
<14>
<14>

<40>

Power Control for Mini card

+1.5VS

JMINI

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

WLAN_WAKE#

DC040009U00

wlan connector

+1.5VS

1
+

CC47 330U_D2_2VM_R6M~D

C43
4.7U_0603_6.3V6K

C48
0.1U_0402_25V6K

C46
0.1U_0402_25V6K

C42
0.047U_0402_16V4Z

C40
0.047U_0402_16V4Z

@ C47
0.1U_0402_25V6K

C45
0.047U_0402_16V4Z

C50
0.047U_0402_16V4Z

@
C87
47P_0402_50V8J

CC47

+3V_WLAN

+3VS

@
C88
47P_0402_50V8J

+3V_WLAN

R25
0_1206_5%~D

+3V_AOAC

2
R22
0_1206_5%~D
@

Battery LED

HDD LED
LED2
12-21C-T3D-CM2P1B18X-2C_WHITE

White

R2
<13>

PCH_SATALED#

PCH_SATALED#

R3

<40>

BATT_CHG_LED#

BATT_CHG_LED#

2
680_0402_1%

2
1

R4

390_0402_5%

+5VS

<40>

BATT_LOW_LED#

BATT_LOW_LED#

2
390_0402_5%

+5VALW

Amber
LED3
HT-210UD5-BP5_AMBER-WHITE

Power LED
Wireless LED

LED1
12-21C-T3D-CM2P1B18X-2C_WHITE

10mils, All pins


R1

2
390_0402_5%

+5VALW
LED4
12-21C-T3D-CM2P1B18X-2C_WHITE

PWR_LED# 1

R9

2
1
680_0402_1%

Q1

WL_BT_LED#

2
G

PWR_PWM_LED#

+5VALW

<40>
<40>

WL_BT_LED#

2N7002_SOT23-3

R786
100K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Mini Card/LED
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

38

of

57

+FAN_POWER

Power ON Circuit

RE49
100K_0402_5%
KB9012@

@ SW1
SMT1-05-A_4P
1
3

TOP Side
DE1

ON/OFF

ON/OFFBTN#

1
CE22

<40>

1000P_0402_50V7K

2.2U_0603_6.3V6K

ON/OFF switch

40mil

+3VLP

FAN Control circuit

1
CE23

+5VS

2
1

3
4

6
5

UE3

1
2
3
4

BAV70W_SOT323-3
CE20
0.1U_0402_25V6K

<40>

EN_DFAN1

EN_DFAN1

CE25
2.2U_0603_6.3V6K
2

VEN
VIN
VO
VSET

GND
GND
GND
GND

8
7
6
5

APE8873M SOP 8P
D

EC_ON

QE1 @
2N7002K_SOT23-3

<40,47>

+FAN_POWER

RE50
10K_0402_5%

JFAN

40mil

1
2
3

6
5

+3VS

@ SW2
SMT1-05-A_4P
1
3

@ RE51
10K_0402_5%

Bottom Side

<40>

1
2
3

4
5

FAN_SPEED1

Pop only
before MP

GND
GND
ACES_85204-0300N
CONN@

1
CE24
0.01U_0402_16V7K

SP02000JR00

POWER/B

INT_KBD Conn.

+3VALW
<40>

JPWR

DE5
PESD24VS2UT_SOT23-3~D

KSI[0..7]

KSI[0..7]

KSO[0..16]

KSO[0..16]

JKB
CONN@
HB_A823020-SBHR21

GND
GND

5
6

HB_A090420-SAHR21
CONN@

EMC@

SP01001G200
SP01000Z300 (OLD)

<40>

1
2
3
4

LID_SW#

<40>

1
2
3
4

LID_SW#
ON/OFFBTN#

Touch pad
+3VS
JTP
<40> TP_CLK
<40> TP_DATA
<14> TP_SMBCLK
<14> TP_SMBDATA

1
2
3
4
5
6

TP_CLK
TP_DATA
TP_SMBCLK
TP_SMBDATA

1
2
3
4
5 G1
6 G2

+5VS
RE60

1
7
8

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
KB_CAPS_PWR

240_0402_1%
KB_CAPS_PWR-

DE3
PESD5V0U2BT_SOT23-3~D

EMC@
A

GND
GND

32
31
B

SP01001H500

SP010014M10

<40>

CAPS_LED

2
G

QE3
2N7002BKW_SOT323-3~D

ACES_51524-0060N-001
CONN@

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


FAN/TP/KB/PWR SW
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

39

of

57

Board ID

Project ID

2
2
0.1U_0402_16V7K

2
2
0.1U_0402_16V7K

1
1
1000P_0402_50V7K

CE6

CE7
0.1U_0402_16V7K

2
0_0402_1%

RE35

EC_SCI#
10K_0402_5%
PCH_HOT#
10K_0402_5%
CE10
@ 22P_0402_50V8J
2
1

+3VALW

2 EC_SMB_CK1_R
2.2K_0402_5%
2 EC_SMB_DA1_R
2.2K_0402_5%
2
KSO1
47K_0402_5%
2
KSO2
47K_0402_5%

EC_RST#
EC_SCI#

2
WLAN_WAKE#
10K_0402_5%

1
RE16
1
RE21
1
RE24
1
RE25

<39>
<39>

2 EC_SMI#
1K_0402_1%
2 EC_PME#
10K_0402_5%
2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%

@
@

1
RE72

EC_SMB_CK2

KSI[0..7]

KSI[0..7]

KSO[0..16]

KSO[0..16]

<25>

EC_SMB_DA2

<25>

2
ODD_EC_EN#
10K_0402_5%

<41>
<45,46>
<45,46>
<14>
<14>

Reserve for ESD


CE27
2

EC_SMB_CK1
EC_SMB_DA1
PCH_SMLCLK
PCH_SMLDATA

EC_SMB_CK1_R
RE26 1
@2 0_0402_1%
EC_SMB_DA1_R
RE27 1
@2 0_0402_1%
2 0_0402_1%
EC_SMB_CK2
2 0_0402_1%
EC_SMB_DA2

<15>
<15>

PM_SLP_S5#_R

<21>

RE31
RE33

PM_SLP_S3#
PM_SLP_S5#

CE_EN

CE_EN

0.1U_0402_16V7K
<21>

Please close to EC

DBC_EN

DBC_EN

1
1

@2 0_0402_1%
@2 0_0402_1%

<39>

CMOS_ON#
130W/90W#

PCH_PWROK

<15,6>

PCH_PWROK 1
RE40

PCH_PWROK

FAN_SPEED1
EC_PME#
EC_TX
EC_RX

FAN_SPEED1
<38>

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#_R
PM_SLP_S5#_R
EC_SMI#

<17> EC_SMI#
<45> PS_ID
<21>
<45>

RE18

EC_TX

2 <38> EC_RX
0_0402_1%

10K_0402_5%
<15,32>

PCIE_WAKE#

1
RE61

2
EC_PME#
0_0402_1%
<15>

RE82
0_0402_5%
1
2

SUSCLK_R

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

RE82 please close to EC

122
123

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

XCLKI/GPIO5D
XCLKO/GPIO5E

1 100K_0402_5%
KB9012@

1
CE17

2
20P_0402_50V8

KB_LED_PWM
BEEP#
1
43_0402_1% 2 RE36
ACOFF
ACOFF

KB_LED_PWM
BEEP# <33>
PCH_PWR_EN
<46> 2

EC_CRY1

22P_0402_50V8J

VCOUT1_PH

BATT_TEMP
VCIN0_PH_R
ADP_I
AD_BID0
PCH_HOT#_R
AD_PID0

RE17 2
0_0402_5% @
RE7

BATT_TEMP

VCIN0_PH
ADP_I

PCH_PWR_EN

<35>

<45,46>

<45,46>

PCH_HOT#
0_0402_5%

PCH_HOT#

<14>

68
70
71
72

EN_INVPWR
<21>
EN_DFAN1 <39>
EC_ENVDD
<21>
LCD_TEST <21>

EN_DFAN1

TP_CLK

1
RE9
1
RE10

4.7K_0402_5%

TP_DATA
4.7K_0402_5%

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

83
84
85
86
87
88

GPIO
Bus

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_MUTE# <33>
USB_EN# <36,37>
IMVP_PWRGD <52>

TP_CLK_R
TP_DATA_R

2
RE23 2
RE38

97
98
99
109

CPU1.5V_S3_GATE
WOL_EN#
ME_EN
1
2
@
RE15
0_0402_1%

119
120
126
128

HDD_S3.5
ODD_EC_EN#

SPI Device Interface


SPI Flash ROM

EC_MUTE#
USB_EN#
@
@

1
1 0_0402_1%
0_0402_1%
CPU1.5V_S3_GATE
WOL_EN# <32>
ME_EN <13>
VCIN0_PH
<45>

RE22 1
PECI_KB930

TP_CLK <39>
TP_DATA <39>

GPIO

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R

100
101
102
103
104
105
106
107
108

2 0_0402_1%

<10>

WL_BT_LED#
0_0402_1%

WL_BT_LED#

ENBKL

ENBKL

EC_RSMRST#
EC_RSMRST# <15>
EC_LID_OUT#
EC_LID_OUT# <17>
2
1
@
RE34
0_0402_1% VCOUT1_PH
2
1
VCOUT0
@
BKOFF#
RE37
0_0402_1%
BKOFF# <21>
PBTN_OUT#
PBTN_OUT# <15,6>
ACIN_65W_R
SA_PGOOD
SA_PGOOD <51>

110
112
114
115
116
117
118

ACIN_D
EC_ON_R
ON/OFF_R
LID_SW#_R
SUSP#

RE14 1
RE41 1
RE42 1

PECI_KB9012

RE43 1
KB9012@

124

+V18R

KB9012QF-A3_LQFP128_14X14

20mil

CE30
0.1U_0402_16V7K

Reserve for ESD


Place close to UE1.128

<38>

<15>

PX_MODE <26,53,54>
BATT_CHG_LED# <38> +3VLP
CAPS_LED <39>
reserve
PWR_PWM_LED# <38>
BATT_LOW_LED# <38>
SYSON <35,50>
VR_ON <52>
RE30
@
47K_0402_5%

BATT_CHG_LED#
CAPS_LED
PWR_PWM_LED#
BATT_LOW_LED#
SYSON
VR_ON
PM_SLP_S4#_R

WL_BT_LED#_R

HDD_S3.5 <41>
ODD_EC_EN#
<41>

WL_BT_LED#_R
RE67

73
74
89
90
91
92
93
95
121
127

TP_CLK
TP_DATA

PECI_KB930 1
RE69

2
0_0402_1%

@
@
@

2 0_0402_1%
2 0_0402_1%
2 0_0402_1%

<38>

for KB9012 Rev.A2


SYSON
PM_SLP_S4#_R 1
RE39

2
PM_SLP_S4#
0_0402_1%

PM_SLP_S4#

<15>

2
VCIN1_PH

CE26
0.1U_0402_16V7K

<45>

VCOUT0_PH

<47>

Place close to UE1.95


ACIN_65W_R

1
RE80

2
0_0402_1%

ACIN_65W

<25>
B

ACIN <15,25,45,46>
EC_ON <39,47>
ON/OFF <39>

SUSP# <10,35,48,49,50>
65W/90W#
<45>
2
H_PECI
43_0402_1%

H_PECI

<17,6>

CE16
4.7U_0805_10V4Z
LID_SW#_R

LE2

1
RE81

2
0_0402_1%

LID_SW#

LID_SW#

<39>

For LID SW debug & test


Place close to UE1.115

1@
CE13
2

22P_0402_50V8J

CE14

SA_PGOOD

RE47
100K_0402_5%

ACIN

2 0.1U_0402_16V7K

CE18
2

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

WLAN_WAKE#

@
YE1
32.768KHZ_12.5PF_Q13MC14610002

NC

Analog Project ID definition,


Please see page 4.

100P_0402_50V8J
1

CE19
47P_0402_50V8J

5
SN74LVC1G06DCKR_SC70-5
1

0.1U_0402_16V7K

H_PROCHOT#

H_PROCHOT#

UE2
<46,6>

CE21

EC_CRY2

1
OSC

1
2

@
0_0402_1%
RE44

@
CE12
CE15

0.1U_0402_16V7K

+3VS

OSC

VR_HOT#

NC

VR_HOT#

NC

<52>

1
ECAGND
100P_0402_50V8J

1
ECAGND 2
FBMA-L11-160808-800LMT_0603

Please close to EC

Analog Board ID definition,


Please see page 4.

CE29

EC_CRY1
EC_CRY2

2 RE45

FAN_SPEED1

220P_0402_50V8J

77
78
79
80

+5VS

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

63
64
65
66
75
76

Rb

0.1U_0402_16V7K

+3VLP

PM_SLP_S3#_R

0.1U_0402_16V7K
CE28
2

TOUCH_ON#

TOUCH_ON#

EC_SMB_CK1
EC_SMB_DA1
RE28 @1
RE29 @1

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

2
LID_SW#
10K_0402_5%

1
RE70

PLT_RST#

<17> EC_SCI#
<38> WLAN_ON

0.1U_0402_16V7K

BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

UMA@
RE12
100K_0402_5%

<16,32,38,6>

1 47K_0402_5%
2

CE11

AD Input

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

21
23
26
27

AD_PID0

CE8

200K_0402_5%

CE9

AGND/AGND

1
RE71

RE8

12
13
37
20
38

69

+3VALW

RE6

CLK_PCI_LPC

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

PWM Output

GND/GND
GND/GND
GND/GND
GND/GND
GND0

<16>

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

11
24
35
94
113

1
RE11
1
RE13
1
RE62
1
RE63

1
2
3
4
5
7
8
10

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<17> GATEA20
<17> KB_RST#
<13> SERIRQ
<13> LPC_FRAME#
<13> LPC_AD3
1 @ 33_0402_5% <13> LPC_AD2
<13> LPC_AD1
<13> LPC_AD0

EC_VDD/AVCC

1 @

200K_0402_5%

ECAGND <45>

Reserved for KB9012

67

9
22
33
96
111
125

1
RE32

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

+3VS

RE12 TH@
UMA@

Rb

ECAGND

RE4
UE1

AD_BID0
RE5

1000P_0402_50V7K

1
1

+3VALW_EC

0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1
2
CE2
CE3
CE4
CE5

CE1

RE19
100K_0402_5%

Ra

2
0_0805_1%1

1
RE1

MS@
Rb => NC

RE3
100K_0402_5%

Ra

LE1
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

DIS@
Rb => NC

+EC_VCCA
+3VALW

+3VALW

+3VALW

Compal Electronics, Inc.


EC ENE-KB9012
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

40

of

57

* Touch Screen Panel


+5VS

+5VS_TOUCH

2
0_0603_5%~D

RV249

SATA HDD Conn.

+5VS

QV16
SI2301CDS-T1-GE3_SOT23-3

<13> SATA_PRX_DTX_N0
<13> SATA_PRX_DTX_P0

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+5V_HDD Source
<13>

HDD_DET#

HDD_DET#

+5VALW

+5V_HDD

QN4

HDD_EN_5V

+3VS

RN11
100K_0402_5%

JTOUCH
ACES_88460-00601-P01

1
2
3
4
5
6

USB20_TOUCH_N9
USB20_TOUCH_P9

<16> USB20_TOUCH_N9
<16> USB20_TOUCH_P9

1
CN8

1
CN9

1
CN5

1
2
3
4
5 G1
6 G2

7
8

CONN@

1
CN6

SP010013W00
1
CN7

USB20_TOUCH_N9
USB20_TOUCH_P9

DV13

PESD5V0U2BT_SOT23-3~D

+5VS_TOUCH

10U_0805_10V6K

+5V_HDD

ODD Power Control


3

CV59

Place close
to JTOUCH

JP7

0.1U_0402_16V7K

EMC@

2
1

TOUCH_ON#

TOUCH_RST

3
4

CV328
@

RV218
47K_0402_5%

0.1U_0402_25V6K

JUMP_43X79

SHORT DEFAULT

1000P_0402_50V7K

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

DC010008700

0.1U_0402_25V6K

<40>

+5VS
@ JP13
1
1

0.1U_0402_25V6K

@ RN12
100K_0402_5%

+5V_HDD
CN18
10U_0805_10V6K

HDD_S3.5

CN17
0.1U_0603_50V_X7R

<40>

QN5B
DMN66D0LDW-7_SOT363-6

QN5A
DMN66D0LDW-7_SOT363-6

@
2

RV217
100K_0402_5%

SANTA_193202-1
CONN@

SI3456DDV-T1-GE3_TSOP6~D
S

GND
GND

D
G

GND
A+
AGND
BB+
GND

1
2
5
6

RN9
100K_0402_5%

@
RN10
100K_0402_5%

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

B+_BIAS

+3VALW

SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C

CN3
CN4

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C

<13> SATA_PTX_DRX_P0_C
<13> SATA_PTX_DRX_N0_C

23
24

1000P_0402_50V7K

JHDD

1
2
3
4
5
6
7

+5VS_TOUCH

+5VS_TOUCH

RV219
100K_0402_5%
1
2

TOUCH_RST

1
CV60
0.1U_0402_16V7K

SATA ODD Conn.


+5VS_ODD

Pleace near ODD CONN

JUMP_43X79

SI3456BDV-T1-E3 1N TSOP6

1U_0402_6.3V6K

<13> SATA_PTX_DRX_P2
<13> SATA_PTX_DRX_N2

2
G

QN3
2N7002BKW_SOT323-3~D

RN7
1.5M_0402_5%

ODD_EN#

<13> SATA_PRX_DTX_N2
<13> SATA_PRX_DTX_P2

ODD_EN

CN16
0.1U_0603_50V_X7R

RN6
470K_0402_5%

<17>

JODD

B+_BIAS

CN12
10U_0805_10V6K

1
CN13

+5VS_ODD

CN11
0.1U_0402_25V6K

QN2

6
5
2
1

CN10
1000P_0402_50V7K

+5VS

CH10 2
CH9 2

1 0.01U_0402_16V7K
1 0.01U_0402_16V7K

SATA_PTX_DRX_P2_C
SATA_PTX_DRX_N2_C

2
CN14 2
CN15

1
1 0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_PRX_DTX_N2_C
SATA_PRX_DTX_P2_C

<17>
<16>

ODD_DETECT#

ODD_DA#

2
ODD_DA#_R
0_0402_1%

RN8
@

1
2
3
4
5
6
7
8
9
10
11
12
13

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND

14
15
16
17

GND
GND
NPTH1
NPTH2

SANTA_202801-1
CONN@

DC010007300
ODD_EN

2
G
1

ODD_EC_EN#

QN6 @
2N7002BKW_SOT323-3~D

@ RN15
100K_0402_5%

Compal Secret Data

Security Classification
Issued Date

<40>

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


HDD / ODD
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012

Sheet

41
H

of

57

Screw Hole
H10
H_2P8
@

H9
H_2P8
@

H_3P3
@

H8
H_3P3
@

H_3P3N
@

1
H34

FD3
@ FIDUCAL

H7
H_3P3
@

H18
H_2P8
@

H35
H_3P7
@

H_3P7X3P2N
@

H_3P7
@

1
FD2
@ FIDUCIAL

1
FD1
@ FIDUCAL

H33
H_3P7
@

H6
H_2P8
@

H32
H_3P7
@

H31

H17
H_2P8
@

H16
H_2P8
@

H12
H_2P8
@

H5
H_2P8N
@

1
H11

H4
H_2P8
@

H2
H_2P8
@

FD4
@ FIDUCIAL

H1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Screw Hole
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

42

of

57

Item Page#

Date

Solution Description

Issue Description

Rev.

21,39

LVDS

2012/05/17

SED

Add FHD Panel CE_ENABLE, DBC_ENABLE function from SED request

Add CE_EN, DBC_EN control pin to EC

0.2

21

LVDS

2012/05/22

SED

Follow SED team request disable CE_EN function

Change RV62 to DE-POP and RV100 to POP for disable CE_EN function

0.2

33

Audio codec

2012/05/23

CODEC

Follow CODEC vendor suggestion

Add AUDIO JACK PLUG delay circuit, Spearate NET JACK_PLUG to


=> JACK_SENSE#
&
=> JACK_PLUG#

0.2
0.2

16,21

39

21,39

33

8
9

15,16,
39,41
14

Touch Screen

2012/05/29

HW

Add touch screen function

Add RV217, RV218, RV219, RV249, CV59, CV60, CV328,


DV13, QV16, JTOUCH

Board ID

2012/05/30

HW

Board ID change for PT

Change RE5 from 8.2k_0402(SD028820180) to 33k_0402(SD028330280)

0.2

Touch Screen

2012/05/30

HW

Add touch screen function power control

Add NET "TOUCH_ON#" from JTOUCH to UE1.82(KB9012) for


TOUCH SCREEN PANEL power control

0.2

Audio codec

2012/05/30

HW

Follow RealTek suggestion remove, delete reserve MUTE circuit

Delete D1,QA1,QA2,QA3,RA24,RA26,RA60,RA62,RA68,RA109,CA72,CA73

0.2

ESD

2012/05/30

ESD

ESD ask CAP for reserve

Reserve 0.1u/0402 CH104,CZ23,CH105,CE27,CE29

0.2

Green CLK

2012/05/30

HW

For Green CLK test

Change RH31,RH41,RV232 0ohm form "GCLK@" to "@"


for break the clock signal to device

0.2

10

10,26,41

DC/DC

2012/05/31

HW

Change "+1.5V_CPU_VDDQ", "+1.5VS", "+1.5VGS" derating

Change RC150 330K/0402 to 2M/0402, RC151 100K/0402 to 470K/0402,


RZ18 100K/0402 to 470K/0402, RV115 0/0402 to 2M/0403

0.2

11

41

DC/DC

2012/05/31

HW

For power sequence trunning

Change RZ15 to DE-POP

0.2

ESD

2012/05/31

ESD

Follow ESD team request

Change 0.1u/0402 from "@" to POP

0.2

12

Title

Page 1

Version Change List ( P. I. R. List )


Request
Owner

06,15,16,
39,41

13

32

Green CLK

2012/06/15

HW

Change for Green CLK bom control

Change RL21,RL30 from "@" to "GCLK@"

0.2

14

41

DC/DC

2012/06/15

HW

For WLAN card power sequence issue

Change RZ4,RZ13 from 470K/0402 56K/0403

0.2

15

35,41

Schematic page modify

2012/06/18

HW

Schematic page modify for easily maintain.

Swap Page. 35 & Page 41.

0.2

16

41

ODD

2012/06/18

HW

Change component location for easily maintain.

Move CH9,CH10 from Page.13 to Page.41

0.2

17

39

FAN

2012/06/29

HW

Fan speed noise issue

Reserve 220p/0402 CE24

0.2

18

CPU

2012/06/29

ESD

System boot-up shot down issue.

Change CC151 from POP to "@"

0.2

Circuit adjuest

2012/07/01

HW

Circuit & page adjust for OAK 15" & OAK 17"

1. Swap P.35 & P.41and move touch screen circuit from P.21 to P.41.
2. Swap P.39 & P.40 page no

0.2

19

21,35,
39,40,41

20

40

LID SW

2012/07/01

HW

LID SW need a trace for debug and switch.

Add RE81 for LID SW.

0.2

21

25

GPU

2012/07/01

HW

Follow AMD request, MarsPro will used MPLs.

Change RV75,RV76,RV81 from "DIS@" to "TH@"

0.2

22

29

GPU

2012/07/01

HW

Follow AMD request, MEM_CALRP2 is not need for Mars ASIC now.

Change RV205 from "MS@" to "@"

0.2

23

38

MINI card

2012/07/03

HW

Power Control for Mini card didn't need

Change R17 to "@"

0.2

24

XDP

2012/07/06

HW

S3 return hang issue

Change RC89 from "@" to POP

0.2

25

23

GREEN CLK

2012/07/09

HW

Follow Green CLK FAE suggestion

1.
2.
3.
4.
5.

0.2

26

35

MOAT

2012/07/09

ESD

For ESD request reserve CAP.

Reserve those CAP for ESD MOAT.

0.2

27

18

LVDS

2012/07/10

HW

Change RES and reserve CAP for LVDS issue

Change RH185 from 0ohm-short to 0ohm/0805, and reserve CH106 1U/0402

0.2
0.2

Change UG1.2(+3VLP) & UG1.8(+3VALW) connect to +LAN_IO


Add R787 connect from +RTCBATT to C5.2 & UG1.10
Change C14 from 0.1u to 5p/0402
Change C8 connect from +3V_ALW to +LAN_IO
Add R788 0ohm/0402 from +RTCVCC to UG1 for GCLK & DH1 select

28

13

PCH

2012/07/11

ESD

Follow ESD team request

Add RH44,RH48,RH70 & NET PCH_JTAG_TMS_R, PCH_JTAG_TDI_R,


PCH_JTAG_TDO_R for break signal trace

29

40

PCH

2012/07/11

ESD

Follow ESD team request

1.Change NET NAME "N59110727" to "WL_BT_LED#_R"


2. Reserve 0.1u/0402 on "WL_BT_LED#_R" for ESD

0.2

30

21

LVDS

2012/07/11

HW

Reserve for CE function for LVDS connector

Change CE_EN_R from dummy to JLVDS.18

0.2

31

32

Connector

2012/07/12

ME

For ME request

Change JLAN CPN from "DC234004V00" to "SP011207090"

0.2

32

40

FAN

2012/07/16

HW

For FAN_SPEED1 noise issue

Change CE29 from "@" to POP

0.2

33

14

Touch PAD

2012/07/17

SED

Change Touch PAD SMBUS port for SMBUS issue

Change Touch PAD SMBUS port for SMB0 to SMB

1.0

34

32

GREEN CLK

2012/07/19

HW

Follow Silego FAE request

Change RL21 from 510 ohm to 0 ohm/0402

1.0

35

41

Touch Screen

2012/08/07

SED

Follow SED team request change JTOUCH USB signal conatct.

Change JTOUCH Pin define.

1.0

36

34

Card Reader

2012/08/14

ESD

Follow ESD team request

Reserve CR11 100p/0402 close to JREAD

1.0

37

23

GREEN CLK

2012/08/16

HW

Fixed GCLK output abnormal issue

Change UG1.2(UG1/VDD) from +LAN_IO to+3VALW

1.0

38

33

CODEC

2012/08/16

HW

The issue already fixed by new CODEC.

Remove delay circuit and POP RA4

1.0

39

23

GREEN CLK

2012/08/17

HW

For RTC discharge issue

De-pop R788

1.0

40

32,34

LAN

2012/08/17

HW

For LAN Chip abnormal leakage issue

Pop RL34 and de-pop RE21

1.0

41

34

Card Reader

2012/08/20

ESD

Follow ESD team request

Change CR11 from 100p/0402 to 10p/0402 and POP

1.0

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


HW-PIR
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

43

of

57

Item Page#

Title

Date

Page 2

Version Change List ( P. I. R. List )


Request
Owner

Solution Description

Issue Description

Rev.

42

41

Touch Screen

2012/08/20

SED

Follow SED team request

Change Touch screen power rail for +3VS to +5VS

1.0

43

38

LED

2012/08/20

HW

Change LED light

Change LED1,LED2,LED4 CPN from SC500006O00 to SC50000DC00

1.0

44

38

WLAN

2012/08/20

HW

Remove AOAC function power control

Change R18,R19,R20,R21,C13,Q2,Q4 component BOM structure to "@"

1.0

45

41

Touch Screen

2012/08/20

HW

Add EC control for Touch Screen function

Add RN15 & QN6 and relative circuit connect

1.0

46

40

BATMAN2

2012/08/21

HW

For BATMAN2

Add RE82 0ohm/0402 between trace SUSCLK_R & EC_CRY2

1.0

47

14,17

PCH

2012/08/21

HW

For SYSTEM S3 leakage issue

Change RH79.2 & RH245.2 connect from +3V_PCH to +3VS

1.0

Compal Secret Data

Security Classification
Issued Date

2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


HW-PIR
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

44

of

57

PR902
2.2K_0402_5%
2

3
1

PD900
DA204U_SOT323~D

PR905
10K_0402_1%

PQ900
MMST3904-7-F_SOT323~D

@
PD902
SM24_SOT23

PR906

PSID-5

10K_0402_1%

EC_SMB_CK1 <40,46>

PR913
100_0402_5%
1
2

EC_SMB_DA1 <40,46>

1VSB_N_003

PR912 @
1VSB_N_002 2
G

PQ902
TP0610K-T1-E3_SOT23-3

PC909
0.1U_0402_25V6

B+_BIAS

VSB_N_001

PQ903
2N7002KW_SOT323-3

PH900 under CPU botten side :


CPU thermal protection at 96 +/- 3 degree C

65W/90W#

<40> S

2
2
G

+3VLP
2

+EC_VCCA

PR927
11K_0402_1%
130W/90W#

<40>

<40> VCIN0_PH

PR916 @
11K_0402_1%

PR917

65W/90W#

90W

High

Low

130W

PH900
100K_0402_1%_TSM0B104F4251RZ

.1U_0402_16V7K

499K_0402_1%

65W
PC915 @

130W/90W#

Low

High

<40> VCIN1_PH

2
G

PR926 @
6.81K_0402_1%

2N7002KW_SOT323-3
PQ906

1 1

PR918
90.9K_0402_1%

2N7002KW_SOT323-3
PQ905

2
1

PR915
332K_0402_1%

<40,46>

ADP_I

1 1

SMART
Battery:
01.BATT1+
02.BATT2+
03.CLK_SMB
04.DAT_SMB
05.BATT_PRS
06.SYS_PRES
07.BAT_ALERT
08.GND1
09.GND2

PR919
0_0402_5%~D
1
2

POK

0_0402_5%~D

PBATT battery connector

+3VALW
<47>

PR914
100_0402_5%
1
2

SUYIN_200028MR009G502ZL
CONN@

PR909
100K_0402_1%

PC910
.1U_0402_16V7K

PR911
10K_0402_1%
1
2

2
PR910
100_0402_5%
1
2

PR908
22K_0402_1%
1
2

<40,46>

BAT_ALERT
SYS_PRES
BATT_PRS
DAT_SMB
CLK_SMB

+3VLP

B+

PC908
0.22U_0603_25V7K

+RTCBATT
@
PD905
RB751V-40_SOD323-2
1
2

1
PR907
100K_0402_1%

JRTC
LOTES_AAA-BAT-054-K01
CONN@

PD903
PESD24VS2UT_SOT23-3~D

+5VALW

PD904
PESD24VS2UT_SOT23-3~D

BATT_TEMP

1
2
3
4
5
6
7
8
9
10
11

PD901
BAV99W-7-F_SOT-323-3~D

1
2
B

PSID-1

PBATT

1
2
3
4
5
6
7
8
9
GND
GND

PR904
100K_0402_1%
1
2

2
G

1
1M_0402_1%

+5VALW
PSID-2

PR900
15K_0402_1%
1
2

1
2

PR930

3
4

PS_ID <40>
+5VALW

BATT++
PC907
100P_0402_50V8J

1
2

1
2

0.1U_0402_25V6
PL900
SMB3025500YA_2P
1
2
PC906
0.01U_0402_25V7K

1
2

PC905
100P_0402_50V8J

PC900
1000P_0402_50V7K
2
1

BATT+

PC916

200K_0402_1%

BATT++

PQ904B
L2N7002DW1T1G_SC88-6

1
PR928

BATT+

62

1M_0402_1%

PR929

<15,25,40,46>

1
ACIN

PL902
BLM18BD102SN1D_0603~D
2
1

PSID

PR903
33_0402_5%
3 PSID-3 1
2
PQ901
FDV301N_NL_SOT23-3~D

ACES_50299-00501-003
CONN@

+3VALW

Erp lot6 Circuit VIN


PR931
3.3K_1206_5%~D

1
2

PR901
@ 0_0402_5%
1

PC904
100P_0402_50V8J

1
2

PC903
1000P_0402_50V7K

1
2

PC902
100P_0402_50V8J

6
7

+5VALW

PQ904A
L2N7002DW1T1G_SC88-6

GND
GND

1
2
3
4
5

1
2
3
4
5

PJPDC

PC901
1000P_0402_50V7K

ADPIN

VIN

PL901
SMB3025500YA_2P
1
2

ECAGND <40>

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_DCIN/BATT CONN/OTP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
D

Sheet

45

of

57

Iada=0~3.34A(65W)

8
7
6
5

ADP_I = 19.9*Iadapter*Rsense

BQ24747

747@

PC135

324K/0402

0.1U/0402

3
4

747@

PC128
0.1U_0402_10V7K
2
1

0.1U/0603

0/0402

PR107

PC123

0/0402

PC105
2200P_0402_25V7K
2
1

PC106
0.1U_0603_25V7K
2
1

29

1
1

CE

CSON
VFB

GND
NC

19
18

17
15 VFB
16

1 PR130

BATT+

3
4
1

100_0402_5%

PC120
10U_0805_25V5K~D
2
1

PGND
CSOP

DL_CHG

BATT+

PC119
10U_0805_25V5K~D
2
1

VREF

20

PC118
10U_0805_25V5K~D
2
1

LGATE

PR141
4.7_1206_5%

1
EAI
EAO

PQ112B
L2N7002DW1T1G_SC88-6

5
6
7
8
PQ108

FBO

PC122
10U_0805_25V5K~D
2
1

PR121
PL100
0.01_1206_1%
10UH_PCMB063T-100MS_4A_20%
1
2 CHG
1
4

PR128
0_0402_5%
1

AO4466L_SO8~D

LX_CHG

3
2
1

DH_CHG

23

L2N7002DW1T1G_SC88-6

731@ PC139
1
2

TP
ISL88731CHRTZ-T_QFN28_5X5~D

747@ PC129
0.1U_0603_25V7K
1
2

0.22U_0603_25V7K
@ PC130
1

0.1U_0603_25V7K

PR132

747@

PC104
4.7U_0805_25V6-K
2
1

PC103
4.7U_0805_25V6-K
2
1

VDDP_LDO

24

PQ112A

PC121
680P_0402_50V7K

PHASE

27
UGATE

VICM

21

ISL88731C BQ24747

PC139

PQ107
DDTC115EUA-7-F_SOT323

2
1

PR107
1

10_0402_5%

731@
2

PR127
1

10_0402_5%

28

VDDP

ACOFF 2

ISL88731C BQ24747

ISL88731C BQ24747

ISL88731C BQ24747

PU100 ISL88731C BQ24747

PR122

200k

PC134

0.01u

PC108

0.1u

PR137

100k

PR123

7.5k

PC129

0.1u

PR127

10

PR112

100k

PR129

10k

PC139

0.22u

0.1u

PR107

10

PR117

158k

PC117

2200p

PR132

10

PC123

0.047u

0.1u

747@

PR142

232k

324k

PC124

56p

PR111

4.7

PC135

0.1u

220p

PC126

120p

PC110

1u

PC132

0.01u

PC125

1u

PD101

747@

V1

BATT_TEMP

SCL

PC112
1000P_0402_50V7K
2
1

12

747@ PC125

56P_0402_50V8~D

PC124
2
747@
1

747@

7.5K_0402_5%

747@ PR142

1U_0603_10V6K

10K_0402_5%

1U_0603_10V6K
2
1

@ PC138
0.01U_0402_25V7K
2
1

731@ PC134
0.01U_0402_25V7K
2
1

0_0402_5%
0_0402_5%
PR135
PR134
1
2 1
2

731@ PC132
0.01U_0402_25V7K
2
1

747@ PR129
1

747@
2

VDDSMB

NC

10K_0402_5%

1 2

PR123

25 BST

ACOK

SDA

PC115

5
747@ PC117
2
1

BOOT

PR138

VDDP_LDO

PD101 747@
BAT54HT1G_SOD323-2~D
1
2

AO4712L_SO8~D

ACIN

0.1U_0603_25V7K
1
2

5
6
7
8

ICOUT

V1

26

PQ110

DCIN

3
2
1

14

MAX8731_REF

PC110 731@
1U_0603_10V6K

PR114
2.2_0603_5%
1
2BST_CHGA

CSSN

<40,45> EC_SMB_DA1

0_0402_5%~D
PR120 @
1
2

PQ113B
L2N7002DW1T1G_SC88-6

PR136
3.3K_1206_5%~D

2
6
4

PQ1111A
L2N7002DW1T1G_SC88-6

0.1U_0603_25V7K
1
2

1
2

2
731@

PR142
232K_0402_1%

6
1

<40,45> EC_SMB_CK1

10

MAX8731_REF

2
1

PU100

ACOFF

11

For DT Mode
VIN

22

PR118

PC102
5600P_0402_25V7K~D
1
2

ACSETIN

2200P_0402_50V7K

1
2
1

PC135
.1U_0402_16V7K

PQ111 @
SSM3K7002FU_SC70-3

731@
PU100
DCIN

VIN

100K_0402_1%

PR110
47K_0402_1%

PC136

0_0402_5%~D
PR119 @
1
2

120P_0402_50VNPO~D

731@

2
BATT_TEMP
G

PQ113A
L2N7002DW1T1G_SC88-6

PC109

0.1U_0402_10V7K
2
1

747@

PC116
0.1U_0402_10V7K
2
1

<40,45> ADP_I

PR108
200K_0402_1%
1
2

PR111 731@
4.7_0603_5%
1

2
PR116
49.9K_0402_1%

747@ PR122
200K_0402_5%

731@
PC123
0.047U_0603_25V7M
1
2

PC111
1U_0603_25V6K~D

13

<40,6> H_PROCHOT#

CHG_B+

PR132
731@ 10_0402_5%
2
1

4
2
PR137
100K_0402_1%
2
1MAX8731_REF

PR126
4.7K_0402_5%
1

PR125
100_0402_1%

@ PC127
1U_0603_25V6K~D

VIN

747@ PC126
1
2

PR109
10_1206_1%
1
2

8
7
6
5

CSIN

PL101
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

PC113
1000P_0402_50V7K
1
2

BATT_TEMP

<40,45>

1
2
3

PQ1111B
L2N7002DW1T1G_SC88-6

10K_0402_5%

BATT_TEMP

PR101
200K_0402_1%

1
2

3S2P : CV = 13.3V CC: 1.54A


4S1P: CV = 17.7V CC: 1.1A

PQ102
AO4407AL_SO8

CSIP

1
2
3
4

PQ109
DDTC115EUA-7-F_SOT323

1
ACOFF

+5VALW

731@
PR117
158K_0402_1%
2
1

ACIN

PR133
ACOFF 1

731@
PR112
100K_0402_1%
2
1VDDP_LDO

ACIN <15,25,40,45>

PR139
200K_0402_5%
1
2

BATT_TEMP
PQ114B
L2N7002DW1T1G_SC88-6

VIN
PR105
150K_0402_1%

ACIN

PC101
0.1U_0603_25V7K

PQ104
DDTC115EUA-7-F_SOT323

3
6
1

PQ114A
L2N7002DW1T1G_SC88-6

4
1

PR103
200K_0402_1%

1
3.3_1210_5%

PR100

2
1
3.3_1210_5%

V1

PC100
2.2U_0805_25V6K
1
2 2

PR104

PQ103
PDTA144EU PNP_SOT323

B+

PR102
0.01_1206_1%

1
2
3

1
2
3

CSSP

P2

8
7
6
5

Iada=0~4.62A(90W)

P3

731@ PC108
0.1U_0603_25V7K

PQ101
AO4409L_SO8

PC107 731@
2

PQ100
AO4407AL_SO8

ICREF

VIN

<40>

731@ for ISL88731C


747@ for BQ24747

BAT54HT1G

0.1U/0603

PR127

747@

0/0402

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_CHARGER
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
D

Sheet

46

of

57

2VREF_6182
1

1U_0603_16V6K

PC201

0.1U_0402_25V6

0.1U_0402_25V6

<40> VCOUT0_PH

VCOUT0_PH

1
2

PC209
4.7U_0805_25V6-K

PC208
2200P_0402_50V7K
2
1

3
2
1

1
2

1
+

PC213
330U_6.3V_M

B++

1
2

PC216
4.7U_0805_10V6K

+5VALWP

PC215
680P_0402_50V7K

3
2
1

@
PQ205
AON7702A_DFN8-5

PR210
4.7_1206_5%
2
1

SNUB_5V

5
PC230
1000P_0402_50V7K
1

FB1

REF

ENTRIP1

LG_5V

NC

VREG5

19

PL201
3.3UH_PCMB063T-3R3MS_6.5A_20%
1
2

18

VIN

LX_5V

PC218
0.1U_0402_25V6

PJP202

PR214
100K_0402_5%
PQ201
DDTC115EUA-7-F_SOT-323

VL

5VALWP
TDC 5.6A
Peak Current 8A
OCP current 9.6A
TYP
H/S Rds(on) :27mohm ,
L/S Rds(on) :11mohm ,

PJP203

+5VALW

+3VALWP

PAD-OPEN 4x4m
PJP204
1
2

PAD-OPEN 4x4m
PJP200
1
2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

+3VALW

MAX
34mohm
14mohm

1
2

reserve from ESD requirement

PC219
4.7U_0603_10V6K

PC226
0.1U_0402_10V7K

20

BST1_5V 2

RT8205LZQW(2) WQFN 24P PWM

+5VALWP

0_0402_5%~D

17

EN

2.2_0603_5%
UG_5V

1
1

1
3/5V_EN-2

LGATE1

BST_5V 1

21

2VREF_6182

L2N7002DW1T1G_SC88-6

2.2K_0402_5%
2
PR215 @
1
2

TONSEL

LGATE2

22

PC211

0.22U_0603_10V7K
POK <45>

PR208 2

PC228
0.1U_0402_10V7K

N_3_5V_001

L2N7002DW1T1G_SC88-6

PR213
1

PHASE1

reserve from ESD requirement

<39,40> EC_ON

PHASE2

23

ENTRIP2

ENTRIP1

UGATE1

24

VL

PQ206A

BOOT1

UGATE2

PQ203
AON7408L_DFN8-5

1
2
3

BZV55-B5V1_SOD80C2
PR211
@ 0_0402_5%
VCOUT0_PH 1

PGOOD

BOOT2

PR200
499K_0402_1%
2

PQ206B

B++

PR206
130K_0402_1%
2

PQ204
AON7702A_DFN8-5

MAX
34mohm
14mohm

PR204
20K_0402_1%
2

VO1

VREG3

13

1
PC229
1000P_0402_50V7K
@

PD200

PR212
200K_0402_1%

B++

VO2

GND

PC227
0.1U_0402_10V7K

12

LG_3V

PC214
680P_0402_50V7K

11

SNUB_3V

PC212
330U_6.3V_M

UG_3V 10

LX_3V

PR209
4.7_1206_5%

BST_3V

2.2_0603_5%

PL200
3.3UH_PCMB063T-3R3MS_6.5A_20%
1
2

+3VALWP

8
PR207 2

PC217
1U_0603_10V6K
2
1

reserve from ESD requirement

PC210
0.22U_0603_10V7K
2
1
BST1_3V 1

16

1
2
3

3.3VALWP
TDC 5.4A
Peak Current 7.7A
OCP current 9.2A
TYP
H/S Rds(on) :27mohm ,
L/S Rds(on) :11mohm ,

P PAD

15

25

FB2

PU200

PC206
10U_0805_6.3V6M

ENTRIP2

PQ202
AON7408L_DFN8-5

FB_5V

ENTRIP1

FB_3V

PR205
133K_0402_1%
1

0.1U_0402_25V6
2
1

0.1U_0402_25V6
2
1

PC225

0.1U_0402_25V6
2
1

PC224

PC205
4.7U_0805_25V6-K

0.1U_0402_25V6
2
1

PC223

PC204
2200P_0402_50V7K
2
1

0.1U_0402_25V6
2
1

PC222

+3VLP

PC203
0.1U_0402_25V6
2
1

0.1U_0402_25V6
2
1

PC221

PC220

1UH_PCMB053T-1R0MS_7A_20%
1
2

PR203
20K_0402_1%
1

PR202
30.9K_0402_1%
1
2

SKIPSEL

PL202

PR201
13.7K_0402_1%
1

14

B++

B+

@ PC200

ENTRIP2

PC207
0.1U_0402_25V6
2
1

PC202

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_3.3VALWP/5VALWP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
E

Sheet

47

of

57

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR403/PR400)=0.6*(1+20K/10K)=1.8V

1
2

+1.8VSP
TDC 2.6A
Peak Current 3.8A
OCP current 4.5A

PC404
22U_0805_6.3V6M

PC402
1

22P_0402_50V8J

1
2
1
PR400
10K_0402_1%

PC400
22U_0805_6.3V6M

SY8033BDBC_DFN10_3X3

PR403
20K_0402_1%

+1.8VSP

1
1.8VSP_FB

1SNUB_1.8VSP 2

EN

PR404
4.7_1206_5%

PG

FB

1
2

@ PR401
47K_0402_5%

PR402 100K_0402_5%

1.8VSP_LX

SVIN

11

EN_1.8VSP
PC405
0.22U_0402_16V7K

SUSP#

LX

<10,35,40,49,50>

LX

PVIN

TP

PL400
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

PC401
680P_0402_50V7K

PC403
22U_0805_6.3VAM

PAD-OPEN 3x3m

PVIN

NC

NC

10

1.8VSP_VIN

@
2

+3VALW

PJP400

PU400

PJP401

+1.8VSP

@
2

+1.8VS

PAD-OPEN 3x3m

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_1.8VSP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
D

Sheet

48

of

57

@
2

+V1.05S_VCCPP_B+

PJP500

B+

DRVL

SW_+V1.05S_VCCPP

7
6

LG_+V1.05S_VCCPP

+5VALW
PC500
1
2

11
1U_0603_10V6K

TPS51212DSCR_SON10_3X3

3
2
1

PC510
1000P_0402_50V7K
2
1

PR504
470K_0402_1%

PC509
PR507 @ 1000P_0402_50V7K

+VCCP

PC504
4.7U_0805_25V6-K

PC503
4.7U_0805_25V6-K
2
1

+VCCP

PR505
@4.7_1206_5%

PC501
2200P_0402_50V7K
2
1

PC502
0.1U_0402_25V6
2
1

PL500
1UH_PCMB063T-1R0MS_12A_20%
1
2

PC507

V5IN

TST

2.2_0603_5%

0.1U_0402_10V7K

VFB

UG_+V1.05S_VCCPP

SW

BST_+V1.05S_VCCPP

EN

10

RF_+V1.05S_VCCPP

DRVH

FB_+V1.05S_VCCPP

VBST

TRIP

TP
2

PC506
0.22U_0402_16V7K

PGOOD

PQ501

SUSP#

<10,35,40,48,50>

PR503
150K_0402_5%
1
2

PC505
.1U_0603_25V7K
2
1

SIR818DP-T1_POWERPAK-SO8-5~D

1
PR502
1
2 TRIP_+V1.05S_VCCPP
53.6K_0402_1%
EN_+V1.05S_VCCPP

PR500 2

3
2
1

PU500

+V1.05S_VCCP_PWRGOOD

<51>

PQ500

PR501
100K_0402_5%

PC508
680P_0402_50V7K

+3VS

SIR472DP-T1-GE3_POWERPAK8-5~D

JUMP_43X118

PR506
@ 1.2K_0402_1%

PR508
100_0402_5%

4.99K_0402_1%
2
1

PR511 @
2

VCCIO_SENSE

VSSIO_SENSE_R

<9>

<9>

0_0402_5%~D

PR509
10K_0402_1%

@ PJP501
PR510
@ 10_0402_1%

+VCCP

+1.05VS

+V1.05S_VCCP
TDC 11A
Peak Current 16A
OCP current 19A
TYP
H/S Rds(on) 10mohm ,
L/S Rds(on) :3mohm ,

MAX
14.5mohm
3.6mohm

PAD-OPEN 4x4m

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_+VCCIO
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

49

of

57

PJP301

VLDOIN_1.5V

1.5V_B+

PC307
10U_0805_6.3V6M

1
VTT

20

19
VLDOIN

UGATE

BOOT

18

17

16

VTTREF

VTTREF_1.5V

+1.5VP

PC310
0.033U_0402_16V7K

PC314
220P_0402_50V8J~D
1
2

S3

S5

TON

0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.2A

FB

VDDQ

VDD

PC311
1U_0603_10V6K

PC316
1000P_0402_50V7K

PC306
10U_0805_6.3V6M

2
1
5
AON7702A_DFN8-5
PQ301

1
2
3

VDDP

11

+5VALW

1.5V_FB

PR305
10K_0402_1%
2
1

<35,40> SYSON

PR300
1M_0402_1%
1
2

1.5V_B+

PR306
200K_0402_5%
1
2

PR307
10K_0402_1%

S5_1.5V
PC300

PR308
100K_0402_5%
1
2

PC313
@.1U_0402_16V7K
C

S3_1.5V

SUSP#

1U_0402_6.3VX5R

+1.5V

JUMP_43X118

2 PC309
12
1U_0603_10V6K
VDD_1.5V

GND

RT8207MZQW_WQFN20_3X3

+0.75VS

PAD-OPEN 3x3m

CS_1.5V

CS

PJP304

VTTSNS

PJP300

JUMP_43X118
@
2

PGND

+0.75VSP

PAD

VTTGND

21

+5VALW

PU300

PC315
0.1U_0402_10V7K

+1.5VP

PJP303

PR304
5.1_0603_5%

@
2

LGATE

14

PR302
8.66K_0402_1%
1
2

1
2
3
2

PC312
680P_0402_50V7K

PC308
330U_2.5V_M

15

13

4.7_1206_5%
PR303
1
SNUB_1.5V 2

DL_1.5V

+0.75VSP

SW_1.5V

PC304
0.22U_0603_10V7K

5
AON7408L_DFN8-5
PQ300

1
2

PL300
1UH_PCMB063T-1R0MS_12A_20%
1
2

1.5VP
TDC 6A
Peak Current 8A
OCP current 10A

BOOT_1.5V

DH_1.5V

PC305
2200P_0402_50V7K

1
2

PC303
0.1U_0402_25V6

1
2

PC302
4.7U_0805_25V6-K

1
2

PC301
4.7U_0805_25V6-K

+1.5VP

PR301 2

2.2_0603_5%

PHASE

JUMP_43X118

PGOOD

+1.5VP

1
PAD-OPEN1x1m

PJP302

@
2

10

B+

+1.5VP

PJP1100
@
2

+V1.05SP_B+

B+

VGA@

1
VGA@
PU1100

SW

VFB

V5IN

RF

DRVL
TP

SW_+1.5VGPU

7
6
11

TPS51212DSCR_SON10_3X3
VGA@
PR1106
470K_0402_1%

PC1105
VGA@
4.7U_0805_25V6-K

1
2

PC1102 VGA@
4.7U_0805_25V6-K
2
1

PC1101 VGA@
2200P_0402_50V7K
2
1

3
2
1

PL1100 VGA@
1UH_PCMB053T-1R0MS_7A_20%
1
2

+5VALW

LG_+1.5VGPU

VGA@
PC1107
1U_0603_10V6K

+1.5VGPUP
1

+
PR1102
4.7_1206_5%

@
PC1104
0.1U_0402_16V7K

DRVH

UG_+1.5VGPU

VGA@
PC1103
330U_2.5V_M

RF_+1.5VGPU

EN

BST_+1.5VGPU

FB_+1.5VGPU

0_0402_5%~D

TRIP

10

PC1106
680P_0402_50V7K

2.2_0603_5%

VBST

PQ1101
AON7702A_DFN8-5
VGA@

EN_+1.5VGPU

PGOOD

PR1101 @
2

<10,35,40,48,49> SUSP#

SUSP#

TRIP_+1.5VGPU

3
2
1

1
2
62K_0402_1%

@ PC1109
1000P_0402_50V7K
2
1

1
PR1104

VGA@

PR1100 2

VGA@
PC1108
0.1U_0603_25V7K

PQ1100
AON7408L_DFN8-5
VGA@

PC1100 VGA@
0.1U_0402_25V6
2
1

JUMP_43X118

VGA@
PR1105

11.5K_0402_1%
2
1

+1.5VGPU
TDC 4.2A
Peak Current 6A
OCP current 7.2A

VGA@
PR1103
10K_0402_1%

+1.5VGPUP

PJP1102

2
@

+1.5VGPU

JUMP_43X118

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_+1.5VP/+1.5VGPUP/0.75VSP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

50

of

57

VID [0]
0
0
1
1

VID[1]
0
1
0
1

VCCSA Vout
0.9V
0.85V
0.775V
0.75V

1
2
SNUB_+1.5VP

+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

PC600
680P_0402_50V7K

output voltage adjustable network

PR600
4.7_1206_5%

PL601

PG

VOUT
VID1

EN
VID0

PR605
100K_0402_5%
2
1

4
5

+VCCSA_EN

+3VS
2

+V1.05S_VCCP_PWRGOOD

<49>

PR601 @
0_0402_5%~D

PC609
22U_0805_6.3VAM
1
2

LX

FB

+VCCSAP
PC607
22U_0805_6.3VAM
1
2

SVIN

<40>

PC606
22U_0805_6.3VAM
1
2

SA_PGOOD

PC604
22U_0805_6.3VAM
1
2

@ PC601
0.1U_0402_10V7K
2
1

10

LX

PL600
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

+VCCSA_PHASE

1K_0402_5%
PR604
1
2

PC610
68P_0402_50V8J
1
+VCCSAP_FB2

PVIN

GND

11

1K_0402_5%
PR603
1
2

PC612
10U_0805_6.3V6M

1
2

PC611
10U_0805_6.3V6M
2
1

0.1U_0603_25V7K
PC603
2
1

+VCCSA_PWR_SRC

13

HCB1608KF-121T30_0603
1
2

2200P_0402_50V7K
PC605

+3VALW

PU600
SY8037DDCC_DFN12_3X3
12
1
PVIN
LX

PR606
100_0402_5%
2
1

VCCSA_VID0

<10>

VCCSA_VID1

<10>

PR602 @
2

VCCSA_SENSE

<10>

0_0402_5%~D

The 1k PD on the VCCSA VIDs are empty.


These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.

@
PJP601

+VCCSAP

+VCCSA

PAD-OPEN 4x4m

+VCCP

+VCCSA

@ PR607
0.004_2512_1%
A

reserve for Pentium and Celeron only

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_+VCCSAP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

51

of

57

0.01U_0402_50V7K

PR759
1_0402_5%

1
2
PR758
3.65K_0603_1%

+VCC_GFXCORE_AXG
GP1_Vo

VSUMG+

VSUMG-

PR736

PC722
390P_0402_50V7K
2
1

499_0402_1%
@ PC732
2200P_0402_50V7K
1
2

PR741

1.78K_0402_1%

2K_0402_1%

PC731
100U_25V_M~D

PC730
100U_25V_M~D

PC754
2200P_0402_25V7K
2
1

PC736
0.1U_0402_25V6
2
1

1
+

+VCC_CORE
P1_Vo
B

P1_SW

PR755
1
2
VSUM+
3.65K_0603_1%

VSUM-

PR742
42.2K_0402_1%
1
2

PC727
1

VCC_core
TDC 16A
Peak Current 33A
OCP current 40A
Load line -2.9mV/A

PR757
1
1_0402_5%

130K_0402_1% 150P_0402_50V8F~D
PR744

47P_0402_50V8J

PR740

PC723
1

PQ704

+3VS

PL701
0.22UH_FDUE0640J-H-R22M-P3_25A_20%

PC745
680P_0402_50V7K

PHASE1

PC734
10U_0805_25V6K
2
1

<15,6>

3
2
1

VGATE

PJP700
JUMP_43X118

PR751
4.7_1206_5%
1 2
1

UGATE1
PR726 @
2

@
2

+VCC_PWR_SRC

PC733
10U_0805_25V6K
2
1

PQ701
BOOT1

PGOOD

PC751
680P_0402_50V7K

PQ703

3
2
1

3
2
1

PC715
1U_0603_10V6K

3
2
1

1
2

SIR818DP-T1_POWERPAK-SO8-5~D
PR760
4.7_1206_5%
2
1
2
1

SIR818DP-T1_POWERPAK-SO8-5~D

PQ702

PC714
1U_0603_10V6K

SIR472DP-T1-GE3_POWERPAK8-5~D

UGATE1

PHASE1

18
17

LGATE1

LGATE1

PC743
.1U_0402_16V7K
2
1

B+

PR720
1_0603_5%

19

SIR818DP-T1_POWERPAK-SO8-5~D

20

2
1 1
2
PR749
PC742
2.2_0603_5% 0.22U_0402_16V7K

@ PR752
649_0402_1%
2
1

BOOT1

PGOOD

COMP

FB

RTN

VDD

2
1
PR728
1.91K_0402_1%

PR750
365_0402_1%
2
1

+5VS

21

0.033U_0402_16V7K
PC740

1
2

1
2

1
11K_0402_1%

LGATEG

22

0_0402_5%~D

PR713
0_0402_5%

UGATE1

PHASEG

16

PR733 @
2

ISUMN

PHASE1

ISEN2

24
23

LGATE1

NTC

PL700
0.22UH_FDUE0640J-H-R22M-P3_25A_20%

25
UGATEG

27

26
BOOTG

PGOODG

29

30

28
COMPG

FBG

RTNG

32

31
ISUMNG

ISUMPG

PWM2

VR_HOT#

VCC_GFXCORE
TDC 21.5A
Peak Current 33A
OCP current 40A
Load line -3.9mV/A

3
2
1
5
2
1 1

IMVP_PWRGD

2
1

VDD

SDA

15

+5VS

PU700
ISL95833HRTZ-T_TQFN32_4X4

14

PR727
27.4K_0402_1%
1

2
PR747

PR746
2.61K_0402_1%
12
1
VSUM-

10KB_0402_5%_ERTJ0ER103J

ALERT#

PH703

130_0402_1%
1
SDA

VCCP

0_0402_5%~D

PC756
1000P_0402_50V7K
2
1

PR737
2

VR_HOT#_1

SCLK

PC719
43P_0402_50V8J~D

1
75_0402_5%
1 ALERT#

SDA

NTC

PR725
3.83K_0402_1%
1
1
2
PH702
470K_0402_5%_ TSM0B474J4702RE

SCLK

PR735
2

PR724 @
2
0_0402_5%

2
1

ALERT#

LGATEG

13

PHASEG

12

SCLK

VR_ON

11

2
0_0402_5%~D
2
0_0402_5%~D
2
0_0402_5%~D
2
0_0402_5%~D

54.9_0402_1%

PC710
.1U_0402_16V7K

BOOTG

NTCG

ISUMP

VSUM+

10

VR_SVID_DAT

+VCCP

PAD

33
1
PR723
1
PR729
1
PR731
1
PR732

VR_SVID_CLK

NTCG
VR_EN

VR_SVID_ALRT#

<9>

PR715 1
27.4K_0402_1%

ISEN1

PR722 @
2
0_0402_5%~D

PR712
3.83K_0402_1%
1
2

0.22U_0402_16V7K
PC739

VR_HOT#

PR730

PR763
2.2_0603_5%

@ PC735
2200P_0402_50V7K
1
2

2
1
PH701
470K_0402_5%_ TSM0B474J4702RE

<9>

<40>

VR_ON

<9>

UGATEG

PC755
1000P_0402_50V7K
2
1

PR753
649_0402_1%
2
1

PC750
0.22U_0402_16V7K

PR708
@ 0_0402_5%

<40>

1
2

PR711
392_0402_1%
1
2

2
<40>

PC709
0.082U_0402_16V7K

1
2
2

1
2

1
PR709
11K_0402_1%

PC707
0.033U_0402_16V7K

PR710
0_0402_5%

PC738
.1U_0402_16V7K

IMVP_PWRGD

PC711
.1U_0402_16V7K
2
1

VSUMG-

10KB_0402_5%_ERTJ0ER103J

PH700

PR707
2.61K_0402_1%
1 2
1

VSUMG+

PC708
.1U_0402_16V7K

PJP701
JUMP_43X118

PC752
2200P_0402_25V7K
2
1

68P_0402_50V8J

PC749
0.1U_0402_25V6
2
1

390P_0402_50V7K

PC747
10U_0805_25V6K
2
1

VSS_AXG_SENSE

499_0402_1%

PQ700

PC706
1
2

B+
@
2

+VCC_GFX_PWR_SRC

PC746
10U_0805_25V6K
2
1

330P_0402_50V7K

PC705
1
2

SIR472DP-T1-GE3_POWERPAK8-5~D

VCC_AXG_SENSE

PC704
2
1

PR704

PC702
2
1

130K_0402_1% 150P_0402_50V8F~D

<10>

33.2K_0402_1%

PR703

2.61K_0402_1%

PR705

PR702

2
@ PC703
2
1
<10>

PR701
PC701
2K_0402_1%
330P_0402_50V7K
2
1
2
1

Local sense put on HW site

PC729
1
2
330P_0402_50V7K

PC737

330P_0402_50V7K
PC741
1
2

VCCSENSE

<9>

VSSSENSE

<9>

0.01U_0402_50V7K

Local sense put on HW site

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_VCORE
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

52

of

57

<28>

@
2

VGA_CORE_B+

VCCSENSE_VGA

PJP800

B+

UG_VGA_CORE
SW_VGA_CORE

11

BST_VGA_CORE

BST_VGA_CORE-1 1

3
2
1

PC816 VGA@
4.7U_0805_25V6-K

1
2

PC848 VGA@
4.7U_0805_25V6-K
2
1

PC846 VGA@
0.1U_0402_25V6
2
1

PC847 VGA@
2200P_0402_50V7K
2
1

PC841 @

1
2

1
2

PC815 VGA@
10U_0805_6.3V6M

PC850 VGA@
10U_0805_6.3V6M

PC817 VGA@
10U_0805_6.3V6M

VGA@ PC849
470U_D2_2VM_R4.5M
2
1

+VGA_CORE

VGA@ PC843
470U_D2_2VM_R4.5M

1000P_0603_50V7K

PC839
VGA@
0.1U_0603_25V7K

EN

PR817 VGA@
2.2_0603_5%

PR821 @
4.7_1206_5%

@ PC853
1000P_0402_50V7K
2
1

13

VGA@ PQ801
SIR818DP-T1_POWERPAK-SO8-5~D

+5VALW

LG_VGA_CORE

3
2
1

VGA_CORE_5V

12

VGA@ PQ802
SIR818DP-T1_POWERPAK-SO8-5~D

MODE

16

17
GND

PC803
VGA@
1U_0603_10V6K

10

9
2

14

VGA@ PL800
0.36UH_FDUM0640J-H-R36M-P3_22A_20%

0_0402_5%~D
PR839

VGA@ PC804
0.1U_0402_10V7K

15

3
2
1

PC802 VGA@
1
2

18
TRIP

BST
VID1

V0
VID0

SW

EN_VGA_CORE

VGA@ PR813
1K_0402_5%

+VGA_PCIE
TDC 3.6A
Peak Current 5.2A
OCP current 6A

<25>

1
<25>

GPU_VID1

VGA@ PC805
.1U_0402_16V7K

GPU_VID3

DRVH

TPS51518RUKR_QFN20_3X3

V1

VGA@ PR812
1K_0402_5%
1
2

Thames XT

VGA@

1
VGA@
2

PC840

1
22P_0402_50V8J

2
PJP806

+VGA_PCIEP

VGA_PCIE

VGA@ PC851
22U_0805_6.3VAM

1
2

1
2

VGA@ PC837
22U_0805_6.3VAM

VGA@ PC852
22U_0805_6.3VAM

+VGA_PCIEP

Thames XT

PR832

+1.0VGS

VGA@ PC835
22U_0805_6.3VAM

SNUB_PCIE

PR832 VGA@
6.81K_0402_1%
2
1

VGA@ PR831
10K_0402_1%

1
2

FB_PCIE

+VGA_CORE
TDC 20A
Peak Current 30A
OCP current 36A
FSW=350kHz
DCR 1.4mohm +/-5%

SY8036LDBC_DFN10_3x3

VGA@ PR841
4.7_1206_5%

FB
EN

VGA@

@ PR844
47K_0402_5%

PG

SVIN

TP

2EN_PCIE
200K_0402_5%

LX

VGA@ PC834
680P_0402_50V7K

PVIN

LX_PCIE

+VGA_PCIEP

PXS_PWREN

LX

LX

1
2
<16,26>

PVIN

0.1U_0402_10V7K

1.0V

VGA@ PR843

0.9V

VGA@
PC833
22U_0805_6.3VAM

VGA@ PL803
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

JUMP_43X79

10

PCIE_B+

SS

0.85V

PU801

0.8V

PC832

11

+3VALW

Core Voltage Level

PC842
0.1U_0402_10V7K

GPU_VID1
(GPIO20)

PJP807

GPU_VID3
(GPIO15)

VGA@

<26,40,54> PX_MODE

@ PR810
0_0402_5%~D
1

VGA@ PR809
10K_0402_1%

1
2

<17> VGA_PWRGD

SLEW

21

V2

+3VS

VGA@ PR811
2.2K_0402_5%
1
2

VSNS

DRVL

V5IN

V3

VGA@ PR807
12.4K_0402_1%

PR802
VGA@
47.5K_0402_1%

GSNS

PGOOD

PR838
0_0402_5%~D
1
2

VGA@ PR806
6.19K_0402_1%
1
2

VGA@ PR808
124K_0402_1%
1
2

VREF

VGA@ PR804
100K_0402_1%

PAD

VGA@
PU800

1
VGA@ PR805
6.19K_0402_1%

@ PR803
0_0402_5%~D
1

<28> VSSSENSE_VGA

VGA@ PQ800
SIR472DP-T1-GE3_POWERPAK8-5~D

VGA@ PC801
10P_0402_50V8J

PC800 VGA@
10P_0402_50V8J
1
2

0_0402_5%~D
PR801

2
1
20

4700P_0402_25V7K
19
1
2

JUMP_43X118

Mars Pro

1.0V

0.95V

6.81K

5.9K

JUMP_43X79

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_VGA_CORE/VGA_PCIE
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

53

of

57

1
2

1
1

VGA@

VGA@ PC1012
22U_0805_6.3V6M

VGA@ PC1007
22P_0402_50V8J
2
1

1
2

PR1011 VGA@
10_0402_5%

VGA@ PR1013

PR1021
1M_0402_5%
@

VGA@

PR1020 10K_0402_5%

FB=0.6Volt

+VDDCIP

VGA@ PC1010
22U_0805_6.3V6M
2
1

2
PC1008
0.1U_0402_10V7K

PX_MODE

11

FB_VDDCIP

PR1012 VGA@
4.7_1206_5%

TP

EN_VDDCIP

PC1009 VGA@
22U_0805_6.3V6M

JUMP_43X79

<26,40,53>

PL1000 VGA@
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2

LX_VDDCIP

VGA@ PC1011
680P_0402_50V7K

VGA@
PU1000
SY8033BDBC_DFN10_3X3
10
2
PVIN
LX
9
3
PVIN
LX
8
SVIN
6
FB
5
EN

PG

NC

NC

PJP1002

@
1

+3VALW

+VDDCI
TDC 2.2A
Peak Current 2.2A
OCP current 4A

4.99K_0402_1%

PR1014 @
2

VDDCI_SEN

<28>

0_0402_5%~D

+3VGS

VGA@
PR1015
29.4K_0402_1%

PR1016 VGA@
10K_0402_5%
PR1017 VGA@
10K_0402_5%
2
1

PR1018
10K_0402_1%

@ PC1013
4700P_0402_25V7K

<25>

PR1019 @
100K_0402_5%

PQ1006 VGA@
2N7002W-T/R7_SOT323-3

VDDCI_VID

2
G

VGA@

VDDCI_VID (GPIO_6)

High

1V

Low

0.9V

+VDDCIP

@
1

PJP1003

+VDDCI

JUMP_43X79

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_+VDDCIP
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

54

of

57

PC1294
330U_D2_2V_Y

PC1292
10U_0603_6.3V6M

PC1291
10U_0603_6.3V6M

1
PC1282
1U_0402_6.3V6K

1
PC1269
1U_0402_6.3V6K

PC1268
1U_0402_6.3V6K

2
PC1281
1U_0402_6.3V6K

PC1255
330U_D2_2V_Y

PC1267
1U_0402_6.3V6K

PC1254
330U_D2_2V_Y

PC1280
1U_0402_6.3V6K

PC1266
1U_0402_6.3V6K

PC1279
1U_0402_6.3V6K

PC1265
1U_0402_6.3V6K

PC1278
1U_0402_6.3V6K

PC1263
1U_0402_6.3V6K

PC1264
1U_0402_6.3V6K

PC1277
1U_0402_6.3V6K

PC1262
1U_0402_6.3V6K

PC1276
1U_0402_6.3V6K

PC1261
1U_0402_6.3V6K

PC1230
330U_D2_2V_Y

PC1275
1U_0402_6.3V6K

PC1260
1U_0402_6.3V6K

PC1290
10U_0603_6.3V6M

PC1274
1U_0402_6.3V6K

PC1273
1U_0402_6.3V6K

2
PC1259
1U_0402_6.3V6K

PC1272
1U_0402_6.3V6K

2
PC1258
1U_0402_6.3V6K

PC1289
10U_0603_6.3V6M

PC1288
10U_0603_6.3V6M

PC1287
10U_0603_6.3V6M

PC1286
10U_0603_6.3V6M

PC1285
10U_0603_6.3V6M

PC1284
10U_0603_6.3V6M

Issued Date

2
2
PC1293
330U_D2_2V_Y

2
PC1283
10U_0603_6.3V6M

1
2

1
1

PC1253
22U_0805_6.3V6M

1
PC1252
22U_0805_6.3V6M

PC1271
1U_0402_6.3V6K

1
PC1251
22U_0805_6.3V6M

1
PC1250
22U_0805_6.3V6M

1
PC1247
10U_0603_6.3V6M

PC1246
10U_0603_6.3V6M

PC1245
10U_0603_6.3V6M

PC1244
10U_0603_6.3V6M

PC1243
10U_0603_6.3V6M

PC1242
10U_0603_6.3V6M

Security Classification

2012/08/22

Deciphered Date

1
PC1241
1U_0402_6.3V6K

PC1240
1U_0402_6.3V6K

PC1239
1U_0402_6.3V6K

PC1238
1U_0402_6.3V6K

PC1237
1U_0402_6.3V6K

PC1236
1U_0402_6.3V6K

PC1235
1U_0402_6.3V6K

PC1234
1U_0402_6.3V6K

PC1233
1U_0402_6.3V6K

PC1232
1U_0402_6.3V6K

PC1231
1U_0402_6.3V6K

For BOT side

PC1249
22U_0805_6.3V6M

PC1257
1U_0402_6.3V6K

PC1248
22U_0805_6.3V6M

PC1215
2.2U_0402_6.3V6M

PC1214
2.2U_0402_6.3V6M

PC1270
1U_0402_6.3V6K

PC1207
2.2U_0402_6.3V6M

PC1206
2.2U_0402_6.3V6M

PC1227
22U_0805_6.3V6M

PC1221
22U_0805_6.3V6M

PC1213
2.2U_0402_6.3V6M

PC1205
2.2U_0402_6.3V6M

PC1226
22U_0805_6.3V6M

2
+

PC1220
22U_0805_6.3V6M

PC1229
330U_D2_2V_Y

PC1212
2.2U_0402_6.3V6M

1
1

PC1204
2.2U_0402_6.3V6M

PC1225
22U_0805_6.3V6M

PC1219
22U_0805_6.3V6M

PC1211
2.2U_0402_6.3V6M

PC1203
2.2U_0402_6.3V6M

PC1228
330U_D2_2V_Y

PC1224
22U_0805_6.3V6M

1
1

PC1218
22U_0805_6.3V6M

2
PC1223
22U_0805_6.3V6M

PC1210
2.2U_0402_6.3V6M

2
1

PC1217
22U_0805_6.3V6M

PC1222
22U_0805_6.3V6M

PC1202
2.2U_0402_6.3V6M

2
1

PC1209
2.2U_0402_6.3V6M

+VCC_CORE

+VCC_CORE

PC1201
2.2U_0402_6.3V6M

PC1216
22U_0805_6.3V6M

PC1208
2.2U_0402_6.3V6M

PC1200
2.2U_0402_6.3V6M

5
2
1

+VCC_GFXCORE_AXG

2013/08/31

For TOP side

+VCC_CORE

Can connect to GND if motherboard only

Vaxg

motherboard design (Gfx VR keeps VAXG from


floating) if the VR is stuffed

VAXG can be left floating in a common

supports external graphics and if GFX VR is not


stuffed in a common motherboard design,

+VCCP
B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data


Title

Date:

PWR_PROCESSOR DECOUPLING

Compal Electronics, Inc.

Document Number

LA-9104P
Wednesday, August 29, 2012
1

Sheet
55
of
57
Rev
1.0

Power block

CPU OTP

Page 44

Turn Off

Input
Switch Page 45

DC IN

B+
+3VALWP: TDC:5.4A
+5VALWP: TDC:5.6A
RT8205LZQW(2) WQFN

CHARGER
CC:0A~1A(4cell) or 2.1A(6cell)
CV:17.7V(4cell) / 13.3V(6cell)
ISL88731CHRTZ-T

Always
Page 46

+3VALW
+1.8VSP: TDC:2.6A
SY8033BDBC

Page 45

Battery

SUSP#

Page 47

+VCCSAP: TDC:4.2A
SY8037DDCC

+V1.05S_VCCP_PWRGOOD
Page 50

+VGA_PCIEP: TDC:3.6A
SY8036LDBC

PX_MODE

+VDDCIP: TDC:2.2A
SY8033BDBC

+VGA_CORE
TDC: 22A
ADP3211AMNR2G_QFN32

PXS_PWREN
Page 52

PX_MODE
Page 53

Page 52

SUSP#

+VCCP: TDC:11A
TPS51212DSCR
VR_ON

+VCC_CORE
TDC: 16A
ISL95833HRTZ-T_TQFN32

+1.5VP/+0.75VSP: TDC:6A/0.7A
RT8207MZQW

Page 51

VR_ON

Page 48

SYSON

Page 49

+VCC_GFXCORE_AXG
TDC: 12A
ISL95833HRTZ-T_TQFN32

+1.5VGPUP: TDC:4.2A
TPS51212DSCR

SUSP#
Page 49

Page 51

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR_POWER BLOCK DIAGRAM


Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

56

of

57

Version Change List ( P. I. R. List )


D

Item Page#

Title

Date

Request
Owner

Page 1

Issue Description

Solution Description

51

VCORE

12/05/11

Morris

adjust VR parameter

change
change
change
change
change
change

PL700
PC707
PR750
PR711
PR740
PR705

44

DCIN/BATT CONN/OTP

12/05/11

Morris

follow SSI memo for part shortage issue

change PQ112,PQ114,PQ1111,PQ206,PQ904 from SB00000CQ00 to SB00000PV00

45

CHARGER

46

3.3VALWP/5VALWP

Rev.

and PL701 from 0.36u to 0.22u


and PC740 from 0.047u to 0.033u
from 649 to 365
from 649 to 392
from 1.91k to 1.78k
from 150k to 33.2k

X00

X00

49

+1.5VP/1.5VDGPU/0.75VSP

12/05/15

Morris

design change

change PR302 from 12k to 8.66k

X00

50

+VCCSAP

12/05/23

Morris

for Pentium and Celeron special BOM

add PR607 and reserve

X00

49

+1.5VP/1.5VDGPU/0.75VSP

12/07/06

Morris

design change to reduce low-side mosfet induce

add PC316 1000pf

X01

45

CHARGER

12/07/17

Morris

from EMI request

change PR114 from 0 to 2.2


add PR141 and PC121

X01

45

CHARGER

12/07/17

Morris

design change to solve Battery LED


is still on after unplug AC when SUT in S3S4S5 issue

change PR142 from 210k to 232k for ISL88731C (X76)


change PR142 from 309k to 324k for BQ24747 (X76)

X01

44

DCIN/BATT CONN/OTP

12/07/17

Morris

revise OTP setting to 96C from thermal request

change PR927 from 12.1k to 11k

X01

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2012/08/22

Deciphered Date

2013/08/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PWR-PIR
Document Number

Rev
1.0

LA-9104P
Wednesday, August 29, 2012
1

Sheet

57

of

57

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