Contents

1 CMOS Digital Design...............................................................................

1.1 Design of CMOS SRAM Cell and Array..........................................
1.1.1 Plan of SRAM Cell and Array...............................................
1.1.2Design of 6 Transistor SRAM Cell........................................
1.1.3Simulations of SRAM Cell....................................................
1.1.4Layout of SRAM Cell............................................................
1.1.5Design of SRAM Array.........................................................
1.1.6Simulation of SRAM Array...................................................
1.2Design of SRAM Chip Circuit Elements...........................................
1.2.1SRAM Chip Circuit Elements................................................
1.2.2Design of Complete SRAM Chip..........................................
1.2.3Simulations of Complete SRAM Chip...................................
1.2.4 Delay Extraction for SRAM Chip Write/Read
Operation................................................................................
1.2.5 Re-Design of SRAM Chip for Low Power
Consumption..........................................................................
Appendix.....................................................................................................
References...................................................................................................

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2 FPGA Application Design........................................................................

2.1Design of Direct Sequence-Spread Spectrum System.......................
2.1.1PN Sequence Generator.........................................................
2.1.2 Transmitter for Direct Sequence-Spread
Spectrum System...................................................................
2.1.3 Receiver for Direct Sequence-Spread
Spectrum System...................................................................
2.2FIR Filter Design...............................................................................
2.2.1Concepts of FIR Filter...........................................................
2.2.2Low Pass FIR Filter Design...................................................
2.2.3Distributed Arithmetic Architecture......................................
2.2.4Simulation and Synthesis Results..........................................

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Contents

2.3Discrete Cosine Transform Algorithms.............................................

2.3.1Concepts of DCT...................................................................
2.3.2DCT Architectures on FPGA.................................................
2.3.3Scaled 1-D 8-Point DCT Architecture...................................
2.3.4Simulation and Synthesis Results..........................................
2.4Convolution Codes and Viterbi Decoding.........................................
2.4.1Concepts of Convolution Codes.............................................
2.4.2Viterbi Decoder......................................................................
2.4.3Simulation and Synthesis Results..........................................
Appendix.....................................................................................................
References...................................................................................................

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3 ASIC Design..............................................................................................
3.1ASIC Front-End Memory Design......................................................
3.1.1Introduction............................................................................
3.1.2Memory Architecture and Specifications...............................
3.1.3Implementation and Simulations...........................................
3.1.4Results Analysis and Conclusion...........................................
3.2ASIC Front-End Matrix Multiplier Design........................................
3.2.1Introduction............................................................................
3.2.2Problem Statement.................................................................
3.2.3Matrix Multiplier Design.......................................................
3.2.4Implementation and Simulations...........................................
3.2.5Analysis of Results and Conclusion......................................
3.3Physical Design of Matrix Multiplier................................................
3.3.1Introduction to Systolic Array Matrix Multiplier..................
3.3.2Physical Design Flow.............................................................
3.3.3Results and Conclusion..........................................................
Appendix.....................................................................................................
References...................................................................................................

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4 Analog and Mixed Signal Design............................................................. 83

4.1Schematic Design of OPAMP............................................................ 83
4.1.1Introduction............................................................................ 83
4.1.2Two Stage OPAMP Design.................................................... 84
4.1.3Results.................................................................................... 93
4.2Layout Design of OPAMP................................................................. 93
4.2.1Introduction............................................................................ 93
4.2.2Layout Design........................................................................ 93
4.2.3Summary and Results............................................................ 98
Appendix..................................................................................................... 99
References................................................................................................... 104
About the Author............................................................................................ 105

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