module memory(read_data, write_data, address, en_chip, rw, clock);

input [3:0]write_data;
input [3:0]address;
input en_chip;
input rw;
input clock;
output [3:0]read_data;
reg [3:0]read_data;
THIS IS THE ONLY WAY TO GIVE THE BASICS OF THE MEMORY.
reg [63:0]mem[0:255];
// [7:0] is width and [0:256] is depth.
always @(posedge clock && en_chip && rw)
begin
mem[address] <= write_data;
end
always @(posedge clock && en_chip && !rw)
begin
read_data <= mem[address];
end
endmodule