Amoi M515 REV B

5
catalog
Cover sheet
BLOCK_DIAGRAM
SMBUS_&_IRQ_ROUTING
POWER_ON_SEQUENCE
POWER_Block
CLCOK GEN
CPU
CPU_POWER
GMCH_1_Host_DDR2
GMCH_2_Display
GMCH_3_POWER
DDR2_SODIMM0
DDR2_SODIMM1
DDR2_Temination
LCD_CON
CRT&S_Video CON
ICH6_1
ICH6_2
ICH6_3_Power
MiniPCI
LAN
Richo 1394
Richo CardBus&CardReader
SATA
DVDROM
USB_PORT
PWR_Budget
PWR_Charger
PWR_System
PWR_DDR2
PWR_VCCP&VCC_GMCH
PWR_VCore
S3_S4_CNTR&Discharge
System_PWRGD
ACIN
KBC_1
KBC_2&CON
Touch PAD and LED
FM
ALC260 Codec
Audio speaker&earphone
Modem CON
Power_Sequence
Miscellaneous
INTEL NAPA Platform

M515
Version : B
Drawing by :Yang Tao
Modified by Xiong Wei to Switch to M515
Notes:
Amoi IT Division.
Part Value Prefix : "@" means nopop

Net Value suffix : "#" means Low Active
295 Lane, Zuchongzhi Road, Zhangjiang,

Shanghai, China, 201203
Title
C
ENGINEER:
<Variant Name>
Size
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Cover sheet
Friday, December 22, 2006
Sheet
1
of
49
hexainf@hotmail.com
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
BLOCK DIAGRAM
14.318MHz
Thermal Sensor
FAN
CPU
Yonah
CLK_CPU_BCLK#,CLK_CPU_BCLK
KBC
CRT
R.G.B
LVDS
LVDS
CPU Power
ISL6262
CLK_PCIE
CLK_AC97
CLK_FWHPCI
CLK_KBCPCI
Clock Gen
CLK_MCH_BCLK#,CLK_MCH_BCLK
DREFCLK#,DREFCLK
DREFSSCLK#,DREFSSCLK
CLK_MCH_3GPLL#,CLK_MCH_3GPLL
FSB 667
System Power
ISL6232
Chipset Power
ISL6227
DDR2-667 SO DIMM1
CalistogaGM
DDR2 Power
ISL88550A
DDR2-667 SO DIMM2
CLK_CARDBUS
CLK_LAN
CLK_MiniPCI
TV-OUT
TV-OUT
DMI X4
32.768KHz
GPU
Charger
MAX1908
400MB/S
@
200MHz
CLK_ICH14
CLK_ICHPCI
CLK_USB48
CLK_PCIE_SATA#,CLK_PCIE_SATA
CLK_PCIE_ICH#,CLK_PCIE_ICH
S3/S4 Control
and Discharge
PCI
SATA
Hard Disk
ICH7-M
PATA
ODD
CardBus/1394/
USB Express Card
USB2.0
USB2.0
LAN
Mini PCI
USB0
USB1
24.576MHz
25MHz
USB2
32.768KHz
LPC BUS
BlueTooth
PCI-E
CLK_KBCPCI
KBC
MINI CARD
Azalia
BIOS&EC
KB
TOUCH
PAD
Audio
Codec
<Variant Name>
Modem
Codec
Amoi IT Division.
Title
Size
CLK_Azalia
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
BLOCK
Sheet
1
of
49
RESET TOPOLOGY
PCI Device:
REQ0: PCMICIA
REQ1: MINI PCI
REQ2: LAN
REQ3: X
GMCH
PIRQA#:RTL8100CL/8110SBL
PIRQB#: NC
PIRQC#: MINI PCI
PIRQD#: MINI PCI (Function0)
PIRQE#: R5C841 (Function0)
PIRQF#: R5C841
PIRQG#: R5C841
PIRQH#: Internal USB
PLT_RST#
PCI_RST#
ICH6-M
Buffer
H_CPURST#
CPU
BUF_PLT_RST#
HDD
DVD ROM
MiniPCI
MiniCard
LAN
KBC
LPC Port
CardBus
AD18:LAN
AD22:MINIPCI
AD25:R5C841
ACZ_RST#
Audio
Modem
SMBUS ADDRESS:
Device:
Address
Hex
Clock Gen
SODIMM0
SODIMM1
1101001x
1010000x
1010010x
D2/D3 SMB_ICH_S2
A0
SMB_ICH_S2
A4
SMB_ICH_S2
BUS
SMBUS TOPOLOGY
SMB_BS
+V3.3S
ICH6-M
Notes:
First address is for a write command and
second is for a read command
B Buses
+V3.3A
EXPANDER
SMB_ICH_S2
SODIMM1
SODIMM0
labbeled SMB_ICH_xx come out of ICH,

Via an I2C expander.
The rest come out of EC
SMB_ICH
KBC
+V3.3S
CLOCK
GEN
SMB_BS
+V3.3A
SMB_THRM
GPU Thermal
Sensor
FM
Battery
hexainf@hotmail.com
Smart Battery
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
IRQ ROUTING & SMBUS
Sheet
B
3
of
49
03
ACIN
Circuit
POWER ON SEQUENCE
+V_DC_IN
PG:40
5AC 1BAT
+V_ADP_IN
1AC
POWSW#
D
Startup
Circuit
1
+V_ADP_OUT
+VBAT
Charger
Circuit
Batt
PG:34
PG:40
PG:34
5AC
2
+V_DC
SMCONOFF#
+V3.3A +V5A
S4
shutdown
Power
control
+V3.3A
+V5A
System VR
Monitors
+V3.3A,+V5A,
+V2.5A,+V1.5A
KBC
4
RSMRST#_PWRGD
PG:31
PG:35
PG:39
Delay 99ms
+V3.3A +V5A
S3 shutdown
Power control
PG:39
+V3.3S +V5S +V2.5S
SLP_S3#
11
ALL_SYS_VRPWRGD
IMVP_VR_ON
10
PM_PWRBTN#
+V5
PMRSMRST#
+V3.3
5a
5b
+V1.05S(For Core,CPU I/O)

+V3.3A(Sus)
+V3.3S(For PCI,IDE)
+V1.5S(For Core,SATA,PLL,)
ICH7M
+V0.9S
+V1.8S
PWROK
06
+V1.8
AND
VRMPWRGD
SLP_S4#
H_PWRGD
S4#
S3#
10
DDR2
VR PG:36
16
PG:17,18
+V1.5S(For PLL)
+VCC_Core
+V1.05S
SLP_S3#
17
DDR_VR_PWRGD
AND
15
14
PLT_RST#
+V1.05S +V1.5S
1.05V
VR
1.5V
VR
PG:37
+V1.5S(For PLL)
+V2.5S(For LVDS,CRT)
+V1.8(For DDR)
+1.05S(VCCP,GMCH_Core)
SLP_S3#
AND
PG:37
AND
H_CPURST#
CPU
PG:07
18
8
IMVP_VR_ON
12
+VCC_CORE
11
945GM
DELAY_VR_PWRGOOD
IMVP
VR
PWROK
PG:09,10
14
PG:38
<Variant Name>
CLK_EN#
13
Amoi IT Division.
System
Clock

PG:06
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Power on Sequence
B
Sheet
of
49
BC
BC
BB
BB
BA
BA
AZ
AZ
AY
AY
AX
AX
AW
AW
POWER Delivery Architectural Block Diagram
AV
AV
AU
AU
AT
AT
G3 shut down power
S4,S5 shut down power
AS
S3 shut down power
+V1.8
AR
AR
+Vcore
AQ
+VCCP
ADAPTOR
AP
+VCC_PROC
+V_DC
AO
DDR2 POWER Module
+V1.8
+V0.9S
Dothan-LV
Vcore:0.726-1.116V /?A /S0
VCCP:1.05V /3.0A /S0
VPLL:1.50V /0.3A /S0
DDR2
+V0.9S
AQ
AP
AO
+V3.3A_KBC
KBC
AN
AM
AL
+V1.8S
+VCCP
+VCC_GMCH
Charger
CPU VCORE POWER Module
AK
+V1.5S
+VCC_CORE
AJ
AI
+V1.8
+V2.5S
AH
AG
+V1.05S
BATTERY
+V3.3S
1.05/1.5V POWER Module
AF
AM
GMCH
VCCP:1.05V /S0
Vcore:1.05-1.50V /S0
VPLLs:1.50V /S0
VccPCIE:1.5V /S0
VccDLVDS:1.5V /S0
VccSM:1.8V /S0,S3
VccALVDS:2.5V /S0
VCRTDAC:2.5V /S0
VTVDAC:3.3V /S0
+V3.3S
AK
+V5
AI
BlueTooth
AG
PATA
AF
+V3.3S
+VCCP
+V1.5S
AA
+V2.5S
+V3.3
+V3.3S
+V3.3S
X
+V5A
+V5S
+V3.3A
SYSTEM POWER Module
+V5S
+V5A
AD
+V3.3S
AC
+V2.5S
AE
Azalia/Ac97
SATA
+V5S
+V3.3A
AH
+V5S
AD
AJ
USB
+V3.3
+V1.5S
2.5V POWER Module
AL
FMH
AE
AB
AN
ICH6-M
VccpCPU:1.05V /S0
Vcore:1.50V /S0
VPLLs:1.50V /S0
VccPCIE:1.5V /S0
V2.5REF:2.5V /S0
VccPCI:3.3V /S0
VccIDE:3.3V /S0
Vccp:3.3V /S0
VccpAUX(LAN):3.3V /S0
VccSUS:3.3V /S0,S3
V5REF:5V /S0
V5REFSUS:5V /S0,S3
AC
+V3.3
AB
MiniPCI
+V5S
AA
+V3.3
CardBus
+V5S
+V3.3S
LCD
+V_DC
T
<Variant Name>
Amoi IT Division.

www.amoi.com.cn
Title
Size
C
ENGINEER:
A
5
<EngName>
Date:
M515
Sheet
Name
Rev
Power Block
Sheet
1
of
49
hexainf@hotmail.com
AS
POWER RAIL
VCORE_CPU
VCCP
1.8VDDM
DESTINATION
VOLTAGE
Banias
Banias
ICH4M MontaraGM
Banias
(PLL)
MontaraGM (PLL)
0.7-1.708V
0.9-1.105V
1.8V
1.2VDDM
1.5VDDM
2.5VDDS
1.8VDDS
1.25VDDM
1.5VDDS
1.2VDDS
1.5VDDA
3VDDM
3VDDS
1.2V
(CORE, HUB, DDRDDL)
MontaraGM
(LVDS, DAC, DVO)
(CORE)
ICH4M
MontaraGM
(DDR, LVDSIO)
DDR RAM
R5C551
82541EI
DDR RAM
(LAN)
ICH4M
82541EI
ICH4M
(SUS)
ICH4M
(IO)
R5C551
MiniPCI
FWH BIOS
LPC KBC
AC97 CODEC
CLK GEN
LVDS
ICH4M
(LAN)
R5C551
MiniPCI
82540EM
PCMCIA VCCA
1.5V
2.5V
1.25V
1.5V
1.2V
1.5V
3.3V
S0 CURRENT
32A
2.5A
0.72A
0.3A
0.099A
1.89A
(1.4A, 0.09A, 0.4A)
0.23A
(0.07A, 0.07A, 0.09A)
0.5A
2.12A
(2.07A, 0.05A)
(Run
1.046A (Idle) 1.692A
3DMark)
0.13A
0.22A
0.0769A
0.0155A
0.47A
0.0675A
0.528A
0.13A
3.3V
0.0308A (Idle)
0.0461A (Idle)
0.36A
0.246A
0.0092A
0.15A
3VDDA
ICH4M
5VDDM
AMP2020
CDROM
HDD
INT KB/ INT MS
INVERTER
5VDDS
PCMCIA VCCA
5VDDA
ICH4M
USB
10UA
PMU3V
PMU08
0.0615A
PMU5V
ASIC_B0
0.0615A
(SUS)
3.3V
0.165A
0.0615A (Idle) 0.338A
(Run)
0.0461A (Idle) 0.677~0.8A (Run)
0.0461A (Idle) 0.492A
(Run)
0.0615A (Idle) 0.569A
(Run)
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_Budget
B
Sheet
of
49
Power On Sequence
Power Down Sequence
POWSW#
STP_CLK#
PS_LATCH#
SUS_STAT#
DCIN
STP_PCI#
+V3.3A_KBC
PLT_RST#,PCI_RST#
+V*A
H_CPURST#
RSMRST#_PWRGD
SLP_S3#
PMRSMRST#
SLP_S4#
Need confirm the power sequency

PM_PWRBTN# and PMRSMRST#
PM_PWRBTN#
+V*S
SLP_S3#
+VCC_GMCH_Core
+V*S
+VCC_PROC
+VCC_GMCH_Core
DDR_VR_PWRGD
+VCC_PROC
PM_SYS_PWRGD
SLP_S4#
GMCH_VRPWRGD
+V*
+V*
DDR_VR_PWRGD
VCC_MCH_VRPWRGD
PM_SYS_PWRGD
PM_ICH_PWROK
GMCH_VRPWRGD
H_PWRGD
VCC_MCH_VRPWRGD
VR_SHUTDOWN#
99ms
VR_ON
IMVP_VR_ON
+VCCP
+VCC_CORE
VCCP_VRPWRGD
VR_PWRGD_C410#
VID[5:0]
DELAY_VR_PWRGOOD
VR_SHUTDOWN#
VR_ON
IMVP_VR_ON
+VCCP
+VCC_CORE
VCCP_VRPWRGD
VR_PWRGD_C410#
VRM_PWRGD
CPU Power Down Sequence

Intel request:
CLK
B
99ms
DELAY_VR_PWRGOOD
H_PWRGD
PM_ICH_PWROK
Vcore
PLT_RST#,PCI_RST#
Vccp
H_PWRGD
VccA(+VCC_PROC)
H_CPURST#
VID[5:0]
Intel request:
CPU Power on Sequence
Vccp
BCLK
VccA(+VCC_PROC)
<Variant Name>
Amoi IT Division.
Vcore

www.amoi.com.cn
H_PWRGD
Title
H_CPURST#
Size
C
ENGINEER:
5
<EngName>
Date:
M515
Sheet
Name
Rev
Power_Sequence
B
Sheet
of
49
hexainf@hotmail.com
VID[5:0]
A
+V3.3S
FB7
U13
330R
FB0805
1u
C0603
C244
C251
C252
C250
C253
C265
C264
C262
10u
C0805
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
VSS_REF
VSS_PCI
VSS_SRC
VSS_CPU
VSSA2
C234
C228
C227
1u
C0603
10u
C0805
0.1u
C0402
11
13
VDD_48
VSS_48
37
38
VDDA
VSSA
FB9
330R
FB0805
C275
C279
1u
C0603
10u
C0805
C269
C263
33p
C0402
0.1u
C0402
C268
R276
R217
R218
R275
2.2K R0402
2.2K R0402
2.2K R0402
33
R0402
FS_A
22
21
CLK_USB48
CLK_ICHPCI
R242
R253
R254
33R0402
33R0402
33R0402
ITP_EN
96_100M_SEL
SEL_CLKREQ
48
CLK_TPM
29
CLK_KBCPCI
R252
R245
33R0402
33R0402
PCI5
22 PM_STPPCI#
22 PM_STPCPU#
22
CLK_ICH14
CLKREQA#/SRC6
CLKREQB#/SRC6#
33
32
SRC5
SRC5#
SRC4_SATA
SRC4#_SATA
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
31
30
26
27
24
25
22
23
19
20
50 XIN
X3
49 XOUT
14.318MHZ
osc-b276x197mil-4
33p
C0402
FS_B
44
43
41
40
36
35
+V3.3S
4.7
R0603
R221
+V3.3S
CPU0
CPU0#
CPU1
CPU1#
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
29 KBC_CLOCKIN_14.318
9,12 CPU_BSEL2
9,12 CPU_BSEL1
9,12 CPU_BSEL0
VDD_REF
VDD_PCI
VDD_SRC1
VDD_SRC2
VDD_SRC_ITP
VDD_CPU
VDDA2
2
6
29
45
51
C240
1
7
21
28
34
42
48
33 REF_CLK1
R0402
R274
53
16
12
8
9
56
3
4
5
REF1
+V1.05S
+V1.05S
+V1.05S
R531 POP = NA
1K
R0402
R533
1K POP = NA
R0402
CPU_BSEL1
R532
0
R0402
POP = NA
R269
R268
R256
R255
R241
R240
RE2
RE1
R258
R257
33
33
33
33
33
33
33
33
33
33
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
DOT96
DOT96#
14
15
DOT96
DOT96#
33
33
R0402
R0402
SDATA
SCLK
47
46
VTTPWRGD#/PD
10
IREF
39
R260
R259
CLK_CPU_BCLK 9
CLK_CPU_BCLK# 9
CLK_MCH_BCLK 11
CLK_MCH_BCLK# 11
CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25
CLK_PCIE_SOCKET2
CLK_PCIE_SOCKET2#
CLK_MCH_BCLK
R294
49.9_1%
R0402
CLK_MCH_BCLK#
R293
49.9_1%
R0402
CLK_CPU_BCLK
R289
49.9_1%
R0402
CLK_CPU_BCLK#
R288
49.9_1%
R0402
CLK_PCIE_VGA
R251
49.9_1%
R0402
CLK_PCIE_VGA#
R250
49.9_1%
R0402
CLK_PCIE_3GPLL
R227
49.9_1%
R0402
CLK_PCIE_3GPLL# R226
49.9_1%
R0402
CLK_PCIE_SATA
R247
49.9_1%
R0402
CLK_PCIE_SATA#
R246
49.9_1%
R0402
CLK_PCIE_ICH
R225
49.9_1%
R0402
CLK_PCIE_ICH#
R224
49.9_1%
R0402
DREFSSCLK
R228
49.9_1% R0402
DREFSSCLK#
R229
49.9_1% R0402
DREFCLK
R249
49.9_1% R0402
DREFCLK#
R248
49.9_1% R0402
CLK_PCIE_SOCKET2
R283
49.9_1% R0402
CLK_PCIE_SOCKET2#
R282
49.9_1% R0402
CLK_PCIE_LAN
R292
49.9_1% R0402
CLK_PCIE_LAN#
R291
49.9_1% R0402
CLK_PCIE_NEWCARD
R281
49.9_1% R0402
CLK_PCIE_NEWCARD#
R280
49.9_1% R0402
CLK_PCIE_NEWCARD 42
CLK_PCIE_NEWCARD# 42
CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
CLK_PCIE_3GPLL 12
CLK_PCIE_3GPLL# 12
CLK_PCIE_VGA 40
CLK_PCIE_VGA# 40
DREFSSCLK
DREFSSCLK#
DREFCLK
DREFCLK#
12
12
12
12
SMB_DATA_S2 17,18,22,42
SMB_CLK_S2 17,18,22,42
R238
R272
475_1%
R0402
1K
R0402
CLK_EN#
48
48
35
C237
0.1u
C0402
BSEL Setup
FSB
R530 POP = NA
1K
R0402
CPU_BSEL0
PCIE_CLK5
PCIE_CLK5#
PCIE_CLK4
PCIE_CLK4#
PCIE_CLK3
PCIE_CLK3#
PCIE_CLK2
PCIE_CLK2#
PCIE_CLK1
PCIE_CLK1#
33
33
33
33
CY28442ZXC-2
tssop50p740-56n
R271
R270
R0402
R0402
R0402
R0402
R0402
R0402
DREFSSCLK_D R237
DREFSSCLK#_DR243
PCI2/SEL_CLKREQ
PCI3
PCI4
PCI5
52
33
33
33
33
33
33
17
18
ITP_EN/PCIF0
96_100_SEL/PCIF1
PCI_STP#
CPU_STP#
R277
R273
R287
R286
R285
R284
96_100_SSC
96_100_SSC#
FS_C(TEST_SEL)/REF0
FS_B/TESTMODE
FS_A/48M_0
55
54
CPU_CLK0
CPU_CLK0#
CPU_CLK1
CPU_CLK1#
R528
1K POP = NA
R0402
CPU_BSEL2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
+V3.3S
533
667
R529 POP = NA
0
R0402
+V3.3S
R230
10K
R0402
POP = NA
ITP_EN
R239
10K
R0402
+V3.3S
R231
10K
R0402
96_100M_SEL
R244
10K
R0402
R264
10K
R0402
POP = NA
SEL_CLKREQ
R263
10K
R0402
POP = NA
1:Set pin36/35 to CPU_ITP

0:Set Pin36/35 to SRC7
1:Set pin17/18 to 100MHZ

0:Set Pin17/18 to 96MHZ
1:Set pin32/33 as clock request pin

0:Set Pin32/33 as SRC
For EMI
CLK_USB48
C236
10p
C0402
CLK_TPM
C246
10p
C0402
CLK_ICHPCI
C245
10p
C0402
CLK_KBCPCI
C242
10p
C0402
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Clock GEN
Sheet
1
of
49
11
H_A#[31:3]
11
H_D#[63..0]
0 R0402
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
B25
RSVD[11]
CONTROL
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
B1
F3
F4
G3
G2
HIT#
HITM#
G6
E4
PROCHOT#
THERMDA
THERMDC
D21
A24
A25
THERM
XDP/ITP SIGNALS
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
THERMTRIP#
STPCLK#
LINT0
LINT1
SMI#
F1
D20
B3
BCLK[0]
BCLK[1]
H_BREQ#0 11
H_IERR#
R522
56R0402
+V1.05S
H_INIT# 20
H_LOCK# 11
H_RS#0
H_RS#1
H_RS#2
H_CPURST#
11
H_RS#[2:0]
H_TRDY#
11
H_HIT#
H_HITM#
11
11
11 H_DSTBN#[3:0]
+V1.05S
H_TCK
TDI_FLEX
R91
150
R0402
11 H_DSTBP#[3:0]
11 H_DINV#[3:0]
+V1.05S
H_TDO
H_TMS
H_TRST#
ITP_DBRESET
+V1.05S
R521
68
R0402
H_PROCHOT#
H_THERMDA
H_THERMDC
H_PROCHOT#
A22
A21
RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]
D2
F6
D3
C1
AF1
D22
C23
C24
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_GTLREF
R516
2K_1%
R0402
PM_THRMTRIP# 12,20,40
RSVD[12]
R517
1K_1%
R0402
35
C7
T22
11
CLK_CPU_BCLK 8
CLK_CPU_BCLK# 8
AD26
R520
1K
R519
51
R0402
8,12 CPU_BSEL0
8,12 CPU_BSEL1
8,12 CPU_BSEL2
R0402
POP = NA
R535
R534
R525
GTLREF
ACLKPH
C26
TEST1
DCLKPH
D25
TEST2
B22
B23
C21
BSEL[0]
BSEL[1]
BSEL[2]
0 R0603
0 R0603
0 R0603
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
DATA GRP 2
A20M#
FERR#
IGNNE#
A1
20 H_INTR
20 H_NMI
20 H_SMI#
A6
A5
C4
H_STPCLK#_C D5
C6
B4
A3
H_DEFER# 11
H_DRDY# 11
H_DBSY# 11
H4
H CLK
20 H_STPCLK#
R479
H5
F21
E1
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
RESERVED
20 H_A20M#
20 H_FERR#
20 H_IGNNE#
H_ADS# 11
H_BNR# 11
H_BPRI# 11
IERR#
INIT#
KEY2
H_ADSTB#1
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#
KEY1
11
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
BR0#
H1
E2
G5
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 1
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
DEFER#
DRDY#
DBSY#
ADDR GROUP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
K3
H2
K2
J3
L5
ADS#
BNR#
BPRI#
A2
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
H23
G22
J26
DATA GRP 0
11 H_ADSTB#0
11 H_REQ#[4:0]
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
U22B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
DATA GRP 3
U22A
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
U1
V1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
MISC
COMP0
COMP1
COMP2
COMP3
R514
R515
R97
R98
27.4_1%
54.9_1%
27.4_1%
54.9_1%
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#
R0402
R0402
R0402
R0402
20,35
20
11
20
11
35
CPU
bga-127p-26x26-478
CPU
bga-127p-26x26-478
Intel ITP DEBUG PORT

+V1.05S
+V3.3A_KBC
C489
R96
54.9_1%
R0402
0.1u
C0402
29 CPU_TEMP_DBUS
VDD
BBUS
GND
DP
DN
R93
R92
R523
54.9_1% 54.9_1% 150
R0402
R0402
R0402
ITP_DBRESET
H_TMS
H_TDO
H_CPURST#
U24
1
+V3.3A
H_THERMDA
C480
POP = NA
07.13:debug port NC comfirm
33p
H_THERMDC
C0402
EMC1212-AGZQ-TR
sot95p240-5
27.4_1% R0402
680
R0402
H_TCK
H_TRST#
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
CPU1
Sheet
1
of
49
hexainf@hotmail.com
R95
R94
VCC(CORE) Decoupling
PLACE NEAR CPU
+VCC_CORE
+VCC_CORE
U22D
Mid Frequency
Place these inside socket

cavity on L8 ( North side
Secondary)
C104
10u
C0805
C132
C94
C111
C97
C82
C117
C125
C100
C145
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
07.13:10uf?cost down
+VCC_CORE
Place these inside

socket cavity on L8
( South side Secondary)
C98
C95
C133
C83
C126
C118
C112
C105
C101
C146
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
10u
C0805
+VCC_CORE

Primary)
C460
C472
C463
C465
C468
C470
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
+VCC_CORE
cavity on L1 ( South side
Primary)
C471
C469
C467
C464
C462
C459
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
10u
C0805
POP = NA
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
CPU
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA
B26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF2
AE2
+V1.05S
+VCC_CORE
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
(0805,MLCC,>=X5R)
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
U22C
+ CP8
330u
C7343
+V1.5S
LAYOUT NOTE:
PLACE C82 NEAR PIN B26
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VID[6..0]
C481
35
C484
0.01u
C0402
10u
C0805
+VCC_CORE
R509
100_1%
R0402
VCCSENSE
AF7 TP_VCCSENSE
VCCSENSE
35
VSSSENSE
AE7 TP_VSSSENSE
VSSSENSE
35
bga-127p-26x26-478
Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
If use Low Inductance Low-Frequency Decoupling Cap

(Total LF Cap ESR=1.5mohm,ESL=0.8nH/6),
these cap can NA,
If use Commom Low-Frequency Decoupling Cap
(Total LF Cap ESR=1.5mohm,ESL=1.8nH/6),
these must be mounted
R505
100_1%
R0402
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
CPU
bga-127p-26x26-478
VCCP Decoupling
PLACE NEAR CPU
High Frequency
(0603,MLCC,>=X7R)
A
+V1.05S
<Variant Name>
C85
C86
C84
C144
C142
C143
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402

Secondary)
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
CPU2
Sheet
1
10
of
49
H_XRCOMP
H_D#[63..0]
H_A#[31:3]
24.9_1% R0402
Trace should be 10-mil wide

with 20-mil spacing.
+V1.05S
R142
54.9_1%
R0402
H_XSCOMP
+V1.05S
R140
221_1%
R0402
Signal voltage level = 0.3125*Vcc1_05

H_XSWING
R137
100_1%
R0402
C161
0.1u
C0402
H_YRCOMP

R161
24.9_1%
R0402
U23A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
H_XRCOMP
H_XSCOMP
H_XSWING
E1
E2
E4
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
Y1
U1
W1
H_YRCOMP
H_YSCOMP
H_YSWING
+V1.05S
R204
54.9_1%
R0402
8 CLK_MCH_BCLK
8 CLK_MCH_BCLK#
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
AG2
AG1
HOST
R146
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
K4
T7
Y5
AC4
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
K3
T6
AA5
AC5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_CLKIN
H_CLKIN#
H_YSCOMP
D3
D4
B3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
D8
G8
B8
F8
A8
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B4
E6
D6
H_RS#0
H_RS#1
H_RS#2
H_SLPCPU#
H_TRDY#
E3
E7
H_DINV#[3:0]
100_1%
R0402
Signal voltage level = 2/3 of Vcc1_05
H_VREF
H_BNR# 9
H_BPRI#
9
H_BREQ#0 9
H_CPURST# 9
H_DBSY# 9
H_DEFER#
9
H_DPWR# 9
H_DRDY# 9
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_HIT#
H_HITM#
H_LOCK#
R130
H_ADS# 9
H_ADSTB#0 9
H_ADSTB#1 9
J7
W8
U3
AB10
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
+V1.05S
C157
0.1u
C0402
R131
200_1%
R0402
H_DSTBN#[3:0]
H_DSTBP#[3:0]
H_HIT# 9
H_HITM# 9
H_LOCK#
H_REQ#[4:0]
9
B
H_RS#[2:0]
H_CPUSLP#
H_TRDY#
9
9
INTEL945GM
fbga_1466_42_34
+V1.05S
Signal voltage level = 0.3125*Vcc1_05

R205
221_1%
R0402
H_YSWING
C211
0.1u
C0402
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB1
Sheet
1
11
of
49
hexainf@hotmail.com
R198
100_1%
R0402
U23B
TP28
TP27
21 MCH_ICH_SYNC#
R109
10K
R0402
H28
H27
K28
H32
10K
R0402
PM_EXTTS#0
MUXING
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
AU20
AT20
BA29
AY29
M_CKE0
M_CKE1
M_CKE2
M_CKE3
17,19
17,19
18,19
18,19
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
AW13
AW12
AY21
AW21
M_CS#0
M_CS#1
M_CS#2
M_CS#3
17,19
17,19
18,19
18,19
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BA13
BA12
AY20
AU21
17
17
18
18
+V3.3S
17
17
18
18
R115
10K
R0402
39
M_RCOMP#
M_RCOMP
SM_RCOMP#
SM_RCOMP
AV9
AT9
SM_VREF_0
SM_VREF_1
AK1
AK41
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
AF33
AG33
A27
A26
C40
D41
R536
R537
17,19
17,19
18,19
18,19
AE35
AF39
AG35
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AC35
AE39
AF35
AG39
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
C182
0.1u
C0402
DMI_TXP[3:0]
DMI_RXN[3:0]
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE37
AF41
AG37
AH41
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AC37
AE41
AF37
AG41
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_RXP[3:0]
Reserved
DMI X2 Select
CFG6
CFG7
Reserved
CPU Strap
CFG8
CFG9
Reserved
PCIE Graphics
Lane Reversal
Reserved
XOR/ALLZ
CFG[11:10]
CFG[13:12]
CFG[15:14]
CFG16
Reserved
FSB Dynamic ODT
CFG[18:17]
CFG19
Reserved
DMI Lane Reversal
M_VREF
17,18,33
+V1.5S_PCIE
U23C
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
R0402
L_LVBG
TP25
1.5K
L_VDDEN
D32
TP26
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
A33
A32
E27
E26
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
39 GM_LA_DATAN0
39 GM_LA_DATAN1
39 GM_LA_DATAN2
C37
B35
A37
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
39 GM_LA_DATAP0
39 GM_LA_DATAP1
39 GM_LA_DATAP2
B37
B34
A36
LA_DATA_0
LA_DATA_1
LA_DATA_2
G30
D30
F29
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
F30
D29
F28
LB_DATA_0
LB_DATA_1
LB_DATA_2
21
21
EXP_A_COMPI
EXP_A_COMPO
+V1.5S
21
07.13:TV ...
21
+V3.3S
R112
R114
39
GM_CRT_B
39
GM_CRT_G
39
10K
10K
R0402
R0402
TV_DCONSEL0
TV_DCONSEL1
GM_CRT_R
R125
150_1% R0402
R123
150_1% R0402
R122
150_1% R0402
39 GM_CRT_DDC_CLK
39 GM_CRT_DDC_DATA
39 GM_CRT_HSYNC
Configuration
010=FSB 800MHz
011=FSB 667MHz
Others = Reserved
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
39 GM_LA_CLKN
39 GM_LA_CLKP
80.6_1% R0402
80.6_1% R0402
CLK_PCIE_3GPLL# 8
CLK_PCIE_3GPLL 8
DREFCLK#
8
DREFCLK
8
DREFSSCLK# 8
DREFSSCLK
8
DMI_TXN[3:0]
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
+V1.8
R111
10K
R0402
CRTIREF
39 GM_CRT_VSYNC
R121
255_1%
R0402
A16
C18
A19
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
J20
B16
B18
B19
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
K30
J29
TV_DCONSEL0
TV_DCONSEL1
E23
D23
C22
B22
A21
B21
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
C26
C25
G23
J22
H23
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
VGA
CFG[4:3]
CFG5
R106
39
M_ODT0
M_ODT1
M_ODT2
M_ODT3
R110
10K
R0402
L_BKLTEN
39 L_DDC_CLK
39 L_DDC_DATA
INTEL945GM
MCH Strapping Options Summary

Pin Name
Strap Description
CFG[2:0]
FSB Frequency Select
R116
10K
R0402
TV
R119
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
AW35
AT1
AY7
AY40
AL20
AF10
NC
+V3.3S
D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
CLK_REQ#
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
MISC
+V3.3S
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
GRAPHICS
G28
F25
H26
G6
AH33
100 R0402 RST_IN#_MCHAH34
PM_EXTTS#0
PM_EXTTS#1
PM
22 PM_BMBUSY#
17,18 PM_EXTTS#0
35
PM_EXTTS#1
9,20,40 PM_THRMTRIP#
29,37 DELAY_VR_PWRGOOD
R497
21,22 PLT_RST#
AY35
AR1
AW7
AW40
PCI-EXPRESS
TP39
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
LVDS
TP38
TP33
TP36
TP40
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
CFG
TP37
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
DDR
TP32
TP35
CLK
8,9 CPU_BSEL0
8,9 CPU_BSEL1
8,9 CPU_BSEL2
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
DMI
A41
A35
A34
D28
D27
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD
T32
R32
F3
F7
AG11
AF11
H7
J19
D40
D38
PEG_COMP
R103
PEG_RXN[15..0]
40
PEG_RXP[15..0]
40
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
EXP_TXN15C422
EXP_TXN14C428
EXP_TXN13C434
EXP_TXN12C439
EXP_TXN11C442
EXP_TXN10C415
EXP_TXN9 C413
EXP_TXN8 C409
EXP_TXN7 C406
EXP_TXN6 C401
EXP_TXN5 C397
EXP_TXN4 C388
EXP_TXN3 C377
EXP_TXN2 C372
EXP_TXN1 C368
EXP_TXN0 C363
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
EXP_TXP15C419
EXP_TXP14C425
EXP_TXP13C432
EXP_TXP12C438
EXP_TXP11C440
EXP_TXP10C416
EXP_TXP9 C414
EXP_TXP8 C411
EXP_TXP7 C407
EXP_TXP6 C405
EXP_TXP5 C399
EXP_TXP4 C391
EXP_TXP3 C381
EXP_TXP2 C374
EXP_TXP1 C370
EXP_TXP0 C365
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXN[15..0]
40
PEG_TXP[15..0] 40
INTEL945GM
0=DMI X 2
1=DMI X 4 (Default)
0=Reserved
1=Mobile CPU(Default)
0 = Reverse Lanes, 15->0, 14->1 etc.
1 = Normal operation(Default)
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_16
00 = Reserved
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal Operation (Default)
R128
R512
R126
R513
R127
R129
R511
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
R0402
R0402
R0402
R0402
R0402
R0402
R0402
POP = NA
POP = NA
POP = NA
POP = NA
POP = NA
POP = NA
Reserve PCIE Graphics Lanes

+V3.3S
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled
0 = Normal operation(Default)
1 = Reverse Lanes, 3->0, 2->1 etc
For the Crestline chipset: 1= Reverse lanes 1->0, 0->1
CFG20
SDVO/PCIe concurrent 0=Only SDVO or PCIE x1 is operational(Default)
1=SDVO and PCIE x1 are operating simultaneously via the PEG port
SDVO_CTRLDATA SDVO Present
0=No SDVO Card Present(Default)
1=SDVO Card Present
All strap signals are sampled with respect to the leading edge of the (G)MCH PWROK signal
40 MCH_CFG_20
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
R117
R118
R113
1K
1K
1K
R0402
R0402
R0402
POP = NA
POP = NA
POP = NA
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
24.9_1% R0402
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB2
Sheet
1
12
of
49
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AW14
AK23
AK24
AY14
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
M_A_DQS[7..0]
17
M_A_DQS#[7..0]
17
M_A_A[13..0] 17,19
M_A_RAS#
TP30
TP29
M_A_WE#
17,19
17,19
INTEL945GM
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS_0
SB_BS_1
SB_BS_2
AT24
AV23
AY28
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AU23
AK16
AK18
AR27
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
U23E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
17,19
17,19
17,19
17,19
17
MEMORY
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CAS#
M_A_DM[7..0]
SYSTEM
AU12
AV14
BA20
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SYSTEM
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR
18 M_B_DQ[63..0]
U23D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR
17 M_A_DQ[63..0]
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CAS#
M_B_DM[7..0]
18,19
18,19
18,19
18,19
18
M_B_DQS[7..0]
18
M_B_DQS#[7..0]
18
M_B_A[13..0]
M_B_RAS#
TP34
TP31
M_B_WE#
18,19
18,19
18,19
INTEL945GM
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB3
Sheet
1
13
of
49
hexainf@hotmail.com
+V1.05S
U23G
+V1.05S
VCC
INTEL945GM
C447
C448
0.47u
C0603
0.47u
C0603
330u
C7343
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
CP11
+
VCCSM_LF4
VCCSM_LF5
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
CP18
+
C107
C121
C136
C130
C115
C150
330u
C7343
10u
C0805
1u
C0603
10u
C0805
0.22u
C0603
0.22u
C0603
0.22u
C0603
U23F
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
C479
0.47u
C0603
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
+V1.5S
NCTF
INTEL945GM
+V1.8
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
C476
C474
C466
CP9
+
10u
C0805
10u
C0805
0.47u
C0603
330u
C7343
AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16
VCCSM_LF2
VCCSM_LF1
C183
C173
0.47u
C0603
0.47u
C0603
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB4
Sheet
1
14
of
49
+V1.5S
+V1.5S
+V2.5S
+V1.05S
+V1.5S_DPLLA
C131
+V1.5S
0.1u
C0402
POP = NA
2
H22
C152
0.1u
C0402
C102
C30
B30
A30
C103
+V1.5S_PCIE
4.7u
C0805
0.1u
C0402
+V1.5S_3GPLL
+V2.5S
+V1.5S_DPLLB
+V2.5S_CRTDAC
2 10uH
L0805
C154
L16 1
CP23
+
C93
330u
C7343
0.1u
C0402
C455
0.1u
C0402
10u
C0805
0.1u
C0402
POP = NA
C473
C475
C140
22u
22u
0.1u
+V2.5S C0805 C0805 C0402
+V1.5S_HPLL
120R
FB1206
F21
E21
G21
0.022u
+V1.5S_DPLLA
C0402
+V1.5S_DPLLB
B26
+V1.5S_HPLL
C39
AF1
C141
C155
1
FB6
C452
CT4
22u
C3216
0.1u
C0402
C201
AJ41
AB41
Y41
V41
R41
N41
L41
AC33
G41
H41
C92
C81
0.01u
C0402
0.1u
C0402
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
A38
B39
VCCA_LVDS
VSSA_LVDS
AF2
VCCA_MPLL
+V1.5S_MPLL
0.1u
C0402
VCCSYNC
H20
G20
VCCA_TVBG
VSSA_TVBG
+V1.5S
+V1.5S_MPLL
C149
+V1.5S
0.1u
C0402
120R
FB1206
+V1.5S
1
FB5
CT5
22u
C3216
C220
TV...
0.1u
C0402
C122
C156
10u
C0805
0.1u
C0402
+V1.05S
C257
10
R0603
VCCGFOLLOW
+V2.5S_CRTDAC
0.1u
C0402
180R
FB0603
+V1.5S
CP20
+
C450
C449
330u
C7343
10u
C0805
10u
C0805
2 0.15uH
L1210
+V1.5S_PCIE
L13 1
+V1.5S
+V1.5S_3GPLL
L14 1
2 1uH
L1210
R506
VCCD_HMPLL0
VCCD_HMPLL1
A28
B28
C28
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
C138
C128
D21
VCCD_TVDAC
A23
B23
B25
10u
C0805
0.1u
C0402
VCC_HV0
VCC_HV1
VCC_HV2
H19
VCCD_QTVDAC
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
C153
FB4
AH1
AH2
+V3.3S
0.1u
C0402
D5
BAT54
sot95p280-3n-123
2
R124
+V1.5S_QTVDAC
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
+V1.5S
+V1.5S
+V1.5S
+V2.5S
E19
F19
C20
D20
E20
F20
1_1%
R0603
POWER
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
C258
C259
0.1u
C0402
10u
C0805
+V2.5S
C80
C451
C456
0.1u
C0402
4.7u
C0805
0.1u
C0402
+V1.05S
1
C124
330u
C7343
U23H
0.1u
C0402
+V2.5S
CP24
+
CP3
+
330u
C7343
2 10uH
L0805
L17 1
C158
C108
C139
0.22u
C0603
4.7u
C0805
2.2u
C0603
Place on
the edge
Place in
cavity
VTTLF_CAP3
C485
0.47u
C0603
VTTLF_CAP2
VTTLF_CAP1
C214
C170
0.47u
C0603
0.22u
C0603
INTEL945GM
C134
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB5
Sheet
1
15
of
49
hexainf@hotmail.com
0.1u
C0402
U23I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
U23J
VSS
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
INTEL945GM
INTEL945GM
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
NB6
Sheet
1
16
of
49
DDR2 SODIMM0
M_A_DQ[63..0]
J6A
12 M_CLK_DDR0
12 M_CLK_DDR#0
C151
Layout Note:
Place near SO-DIMM
12 M_CLK_DDR1
12 M_CLK_DDR#1
10p
C0402
POP = NA
M_CLK_DDR#0
13,19 M_A_BS#[2..0]
13,19 M_A_A[13..0]
M_CLK_DDR1
C254
Layout Note:
near SO-DIMM
Place
10p
C0402
POP = NA
M_CLK_DDR#1
M_CKE0
M_CKE1
79
80
CKE0
CKE1
M_CLK_DDR0
M_CLK_DDR#0
30
32
CK0
CK0#
M_CLK_DDR1
M_CLK_DDR#1
164
166
CK1
CK1#
M_A_BS#0
M_A_BS#1
107
106
BA0
BA1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
M_A_BS#2
C
12,19
12,19
13,19
13,19
13,19
R265
R267
10K
10K
M_CS#0
M_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#
R0402
R0402
13 M_A_DM[7..0]
13 M_A_DQS[7..0]
13 M_A_DQS#[7..0]
12,19
12,19
M_ODT0
M_ODT1
M_CS#0
M_CS#1
110
115
S0#
S1#
M_A_RAS#
M_A_CAS#
M_A_WE#
108
113
109
RAS#
CAS#
WE#
198
200
SA0
SA1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
13
31
51
70
131
148
169
188
DQS_0
DQS_1
DQS_2
DQS_3
DQS_4
DQS_5
DQS_6
DQS_7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
11
29
49
68
129
146
167
186
DQS_#0
DQS_#1
DQS_#2
DQS_#3
DQS_#4
DQS_#5
DQS_#6
DQS_#7
M_ODT0
M_ODT1
114
119
ODT0
ODT1
SA0_DIM1
SA1_DIM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
SDA
5 M_A_DQ0
7 M_A_DQ1
17M_A_DQ2
19M_A_DQ3
4 M_A_DQ4
6 M_A_DQ5
14M_A_DQ6
16M_A_DQ7
23M_A_DQ8
25M_A_DQ9
M_A_DQ10
35
M_A_DQ11
37
M_A_DQ12
20
M_A_DQ13
22
M_A_DQ14
36
M_A_DQ15
38
M_A_DQ16
43
M_A_DQ17
45
M_A_DQ18
55
M_A_DQ19
57
M_A_DQ20
44
M_A_DQ21
46
M_A_DQ22
56
M_A_DQ23
58
M_A_DQ24
61
M_A_DQ25
63
M_A_DQ26
73
M_A_DQ27
75
M_A_DQ28
62
M_A_DQ29
64
M_A_DQ30
74
M_A_DQ31
76
M_A_DQ32
123
M_A_DQ33
125
M_A_DQ34
135
M_A_DQ35
137
M_A_DQ36
124
M_A_DQ37
126
M_A_DQ38
134
M_A_DQ39
136
M_A_DQ40
141
M_A_DQ41
143
M_A_DQ42
151
M_A_DQ43
153
M_A_DQ44
140
M_A_DQ45
142
M_A_DQ46
152
M_A_DQ47
154
M_A_DQ48
157
M_A_DQ49
159
M_A_DQ50
173
M_A_DQ51
175
M_A_DQ52
158
M_A_DQ53
160
M_A_DQ54
174
M_A_DQ55
176
M_A_DQ56
179
M_A_DQ57
181
M_A_DQ58
189
M_A_DQ59
191
M_A_DQ60
180
M_A_DQ61
182
M_A_DQ62
192
M_A_DQ63
194
197SMB_CLK_S2
195SMB_DATA_S2
13
+V1.8
+V1.8
J6B
C203
C493
C210
C196
C195
2.2u
C0603
2.2u
C0603
2.2u
C0603
2.2u
C0603
2.2u
C0603
Layout Note:
Place these Caps near SO-DIMM
+V1.8
+V3.3S
C490
C501
C500
C491
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
Layout Note:
C273
C271
0.1u
C0402
2.2u
C0603
R132
12,18 PM_EXTTS#0
0
R0402
M_VREF
C123
C119
12,18,33 M_VREF
2.2u
C0603
112
111
117
96
95
118
81
82
87
103
88
104
VDD_01
VDD_02
VDD_03
VDD_04
VDD_05
VDD_06
VDD_07
VDD_08
VDD_09
VDD_10
VDD_11
VDD_12
199
VDDSPD
83
120
50
69
163
NC1
NC2
NC3
NC4
NCTEST
VREF
0.1u
C0402
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
E1
E2
M_CLK_DDR0
M_CKE0
M_CKE1
E1
E2
12,19
12,19
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
DDR2
SMD-CN-60X820P-200N
+V1.8
SMB_CLK_S2 8,18,22,42
SMB_DATA_S2 8,18,22,42
DDR2
SMD-CN-60X820P-200N
C221
C216
C181
C185
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
Layout Note: Place these Hi-Freq

Decoupling Caps near the GMCH
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
DDR2_SODIMM0(1 of 3)
B
Sheet
17
of
49
hexainf@hotmail.com
DDR2 SODIMM1
+V1.8
J7A
12 M_CLK_DDR3
12 M_CLK_DDR#3
30
32
CK0
CK0#
12 M_CLK_DDR2
12 M_CLK_DDR#2
164
166
CK1
CK1#
C147
Layout Note:
near SO-DIMM
Place
10p
C0402
POP = NA
M_CLK_DDR#3
M_B_BS#0
M_B_BS#1
107
106
BA0
BA1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_BS#2
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
M_CS#2
M_CS#3
110
115
S0#
S1#
M_B_RAS#
M_B_CAS#
M_B_WE#
108
113
109
RAS#
CAS#
WE#
SA0_DIM0
R0402
SA1_DIM0
R0402
198
200
SA0
SA1
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
13
31
51
70
131
148
169
188
DQS_0
DQS_1
DQS_2
DQS_3
DQS_4
DQS_5
DQS_6
DQS_7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
11
29
49
68
129
146
167
186
DQS_#0
DQS_#1
DQS_#2
DQS_#3
DQS_#4
DQS_#5
DQS_#6
DQS_#7
M_ODT2
M_ODT3
114
119
ODT0
ODT1
13,19 M_B_BS#[2..0]
13,19 M_B_A[13..0]
M_CLK_DDR2
C256
Layout Note:
near SO-DIMM
Place
10p
C0402
POP = NA
M_CLK_DDR#2
12,19
12,19
13,19
13,19
13,19
+V3.3S
M_CS#2
M_CS#3
M_B_RAS#
M_B_CAS#
M_B_WE#
R290
R279
10K
10K
13 M_B_DM[7..0]
13 M_B_DQS[7..0]
13 M_B_DQS#[7..0]
12,19
12,19
M_ODT2
M_ODT3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
SDA
197SMB_CLK_S2
195SMB_DATA_S2
M_B_DQ[63..0]
J7B
13
+V1.8
C495
C202
C496
C209
C498
2.2u
C0603
2.2u
C0603
2.2u
C0603
2.2u
C0603
2.2u
C0603
Layout Note:
+V3.3S
+V1.8
C189
C223
C191
C217
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
12,17 PM_EXTTS#0
C267
C266
0.1u
C0402
2.2u
C0603
R133
12,17,33 M_VREF
Layout Note:
0
R0402
M_VREF
C113C110
112
111
117
96
95
118
81
82
87
103
88
104
VDD_01
VDD_02
VDD_03
VDD_04
VDD_05
VDD_06
VDD_07
VDD_08
VDD_09
VDD_10
VDD_11
VDD_12
199
VDDSPD
83
120
50
69
163
NC1
NC2
NC3
NC4
NCTEST
VREF
2.2u 0.1u
C0603
C0402
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
E1
E2
CKE0
CKE1
M_CKE2
M_CKE3
5 M_B_DQ0
7 M_B_DQ1
17 M_B_DQ2
19 M_B_DQ3
4 M_B_DQ4
6 M_B_DQ5
14 M_B_DQ6
16 M_B_DQ7
23 M_B_DQ8
25 M_B_DQ9
35 M_B_DQ10
37 M_B_DQ11
20 M_B_DQ12
22 M_B_DQ13
36 M_B_DQ14
38 M_B_DQ15
43 M_B_DQ16
45 M_B_DQ17
55 M_B_DQ18
57 M_B_DQ19
44 M_B_DQ20
46 M_B_DQ21
56 M_B_DQ22
58 M_B_DQ23
61 M_B_DQ24
63 M_B_DQ25
73 M_B_DQ26
75 M_B_DQ27
62 M_B_DQ28
64 M_B_DQ29
74 M_B_DQ30
76 M_B_DQ31
123M_B_DQ32
125M_B_DQ33
135M_B_DQ34
137M_B_DQ35
124M_B_DQ36
126M_B_DQ37
134M_B_DQ38
136M_B_DQ39
141M_B_DQ40
143M_B_DQ41
151M_B_DQ42
153M_B_DQ43
140M_B_DQ44
142M_B_DQ45
152M_B_DQ46
154M_B_DQ47
157M_B_DQ48
159M_B_DQ49
173M_B_DQ50
175M_B_DQ51
158M_B_DQ52
160M_B_DQ53
174M_B_DQ54
176M_B_DQ55
179M_B_DQ56
181M_B_DQ57
189M_B_DQ58
191M_B_DQ59
180M_B_DQ60
182M_B_DQ61
192M_B_DQ62
194M_B_DQ63
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
E1
E2
79
80
12,19
12,19
M_CLK_DDR3
M_CKE2
M_CKE3
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
DDR2
smd-cn-60X820p-200an
SMB_CLK_S2 8,17,22,42
SMB_DATA_S2 8,17,22,42
DDR2
smd-cn-60X820p-200an
+V1.8
C492
C494
C497
C499
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
Layout Note: Place these Hi-Freq

Decoupling Caps near the GMCH
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
DDR2_SODIMM1(2 of 3)
B
Sheet
18
of
49
DDR2 Termination
+V0.9S
Layout note:
Place one cap
close to every 2
pullup resistors
teminated to +0.9S
C231
0.1u
C0402
0.1u
C229
C0402
0.1u
C172
C0402
C168
0.1u
C0402
0.1u
C0402
C166
C226
0.1u
C0402
0.1u
C0402
C218
0.1u
C0402
C206
0.1u
C198
C0402
0.1u
C0402
C192
0.1u
C188
C0402
0.1u
C179
C0402
0.1u
C193
C0402
C180
0.1u
C0402
C219
0.1u
C0402
C213
0.1u
C0402
C204
0.1u
C0402
0.1u
C0402
C199
C225
0.1u
C0402
0.1u
C222
C0402
0.1u
C212
C0402
0.1u
C200
C0402
C194
0.1u
C0402
C187
0.1u
C0402
C171
0.1u
C0402
0.1u
C0402
R202
R212
R199
R207
56
56
56
56
R0402
R0402
R0402
R0402
R147
R145
R143
R152
56
56
56
56
R0402
R0402
R0402
R0402
R215
R214
R206
R211
56
56
56
56
R0402
R0402
R0402
R0402
R195
R191
R154
56
56
56
R0402 M_A_BS#0
R0402 M_A_BS#1
R0402 M_A_BS#2
R200
R208
R197
56
56
56
R0402
R0402
R0402
R192
R187
R149
56
56
56
R0402 M_B_BS#0
R0402 M_B_BS#1
R0402 M_B_BS#2
R196
R201
R194
56
56
56
R0402
R0402
R0402
R185
R184
R181
R180
R175
R174
R170
R166
R169
R165
R190
R144
R160
R220
56
56
56
56
56
56
56
56
56
56
56
56
56
56
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
R183
R182
R178
R176
R173
R171
R168
R164
R167
R163
R186
R157
R155
R210
56
56
56
56
56
56
56
56
56
56
56
56
56
56
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_CS#0
M_CS#1
M_CS#2
M_CS#3
12,17
12,17
12,18
12,18
M_CKE0
M_CKE1
M_CKE2
M_CKE3
12,17
12,17
12,18
12,18
M_ODT0
M_ODT1
M_ODT2
M_ODT3
12,17
12,17
12,18
12,18
M_A_BS#[2..0]
13,17
M_B_BS#[2..0]
13,18
M_A_WE# 13,17
M_A_CAS# 13,17
M_A_RAS# 13,17
M_B_WE# 13,18
M_B_CAS# 13,18
M_B_RAS# 13,18
M_A_A[13..0]
M_A_A[13..0]
13,17
M_B_A[13..0]
M_B_A[13..0]
13,18
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
DDR2_Temination(3 of 3)
Sheet
1
B
19
of
49
hexainf@hotmail.com
C232
+V3.3A_RTC
D9
P
Where:
1). Cload = Crystals load capacitance. This value can be obtained from Crystals specification.
2). Cin1, Cin2 = input capacitances at RTCX1,RTCX2 pins of the ICHn. These values can be obtained in the ICHns data sheet.
3). Ctrace1, Ctrace2 = Trace length capacitances measured from the Crystal terminals to RTCX1,RTCX2 pins. These values depend
on the characteristics of board material, the width of signal traces and the length of the traces. The typical value of this
capacitance is approximately equal to:
Ctrace = trace length * 2 pF/inch
4). Cparasitic = Crystals parasitic capacitance. This capacitance is created by the existence of electrode plates and the
dielectric constant of the crystal blank inside the crystal part. Refer to the crystals specification to obtain this value.
+V3.3A_SYS
N
1SS355
sod2514n
2006.07.26:Forrin modify
CN8
D8
E1 -
N
1SS355
sod2514n
C20
RTC_X1
RTCRST# requeres 18-25ms delay.

Use the RC circuit delay the signal .
+V3.3S
22p
C0402
X1
R21
10M
3
+V3.3A_RTC
R396
20K
R0402
2PIN
SMD-CN-125P-3N
C369
1u
C0603
C14
22p
R405 1M C0402
R0603
C389
1u
C0603
32.768KHZ
osc-b720x127-3
+V3.3A_RTC
R398
U7A
INTVRMEN
Disable
1
0
Pull up
R450
10K
R0603
Forrin modify,2005.07.03,Can be
AA3
RTCRST#
STUFF
R381
R380
R424
R423
R422
R421
26 ACZ_BITCLK_C
28 ACZ_BITCLK_M
26 ACZ_SYNC_C
28 ACZ_SYNC_M
26 ACZ_RST#_C
28 ACZ_RST#_M
NC 26 ACZ_SDATAIN0
28 ACZ_SDATAIN1
TP1
26 ACZ_SDATAOUT_C
28 ACZ_SDATAOUT_M
R426
R425
39
39
39
39
39
39
R0603
R0603
R0603
R0603
R0603
R0603
ACZ_SDATAIN2
39 R0603
39 R0603
R451
ATA_LED#
Distance between the ICH-7 M

and cap on the "P" signal should
be identical distance between
the ICH-7 M and cap on the "N"
signal for same pair.
24
24
24
24
SATA_TXN0
SATA_TXP0
R413 R417
1K
1K
R0402 R0402
RTC_RST#
UNSTUFF
UNSTUFF
+V3.3S
RTXC1
RTCX2
R395
0
R0402
POP = NA
Pull down
STUFF
AB1
AB2
SM_INTRUDER#
ICH7 internal VR enable strap

Enable (default)
RTC_X2
332K_1%
R0603
47
R0402
Place within 500mils

of ICH ball
45 IDE_PDIOR#
45 IDE_PDIOW#
45 IDE_PDDACK#
45 INT_IRQ14
45 IDE_PDIORDY
45 IDE_PDDREQ
SATA_RXN0
SATA_RXP0
C276
3900p C0603
C280
3900p C0603
TP6
TP7
R428 24.9_1%
R0402
AA6
AB5
AC4
Y6
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
ICH_DRQ#0
ICH_DRQ#1
INTRUDER#
INTVRMEN
LDRQ0#
LDRQ1#/GPIO23
AC3
AA5
W1
Y1
Y2
W3
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LFRAME#
AB3
A20GATE
A20M#
AE22
AH28
V3
LAN_CLK
CPUSLP#
AG27
U3
LAN_RSTSYNC
TP1/DPRSTP#
TP2/DPSLP#
AF24
AH25
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
FERR#
AG26
GPIO49/CPUPWRGD
AG24
U7
V6
V7
LAN_TXD0
LAN_TXD1
LAN_TXD2
U1
R6
ACZ_BIT_CLK
ACZ_SYNC
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
RCIN#
AG23
NMI
SMI#
AH24
AF23
STPCLK#
AH22
THERMTRIP#
AF26
R5
ACZ_RST#
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
AF18
ACZ_SDOUT
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA_RXN2
AF7
SATA_RXP2
AE7
SATA_TXN2_B AG6
SATA_TXP2_B AH6
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF1
AE1
R409
10K
R0402
R390
10K
R0402
LPC_AD[3..0]
ICH_DRQ#0
29,48
29
+V1.05S
LPC_FRAME# 29,48
H_A20GATE
H_A20M#
R483
R498
R488
56
R0402
29
9
TP56
0
R0402
0
R0402
Within 2" from the ICH
H_DPRSTP#
H_DPSLP#
SATA_CLKN
SATA_CLKP
AH10
AG10
SATARBIASN
SATARBIASP
AF15
AH15
AF16
AH16
AG16
AE15
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
IDE
9,35
9
H_FERR#
H_PWRGD
H_IGNNE#
H_INIT#
H_INTR
9
9
H_NMI
H_SMI#
9
9
H_STPCLK#
TP12
H_RCIN#
H_SMI#_R
R475 0
R0402
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
DA0
DA1
DA2
AH17
AE17
AF17
IDE_PDA0
IDE_PDA1
IDE_PDA2
DCS1#
DCS3#
AE16
AD16
29
Within 2" from the series resistor

without stub
Within 2" from the ICH
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
+V1.05S
SATALED#
AF3
AE3
SATA_TXN0_B AG2
SATA_TXP0_B AH2
8 CLK_PCIE_SATA#
8 CLK_PCIE_SATA
LAD0
LAD1
LAD2
LAD3
Y5
W4
T4
R0402
RTC
LPC
1K
R0603
LAN
CPU
NC
R335
AC-97/AZALIA
SATA
E1
E2 +
E2
IDE_PDD[15..0]
R489
56
R0402
R494 24.9_1%
R0402
45
IDE_PDA0
IDE_PDA1
IDE_PDA2
45
45
45
IDE_PDCS1#
IDE_PDCS3#
45
45
ICH7M
bga652_ich7_koz
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
ICH7M1
Sheet
1
20
of
49
PCIE_RXN2_WWLAN
PCIE_RXP2_WWLAN
PCIE_TXN2_WWLAN
PCIE_TXP2_WWLAN
25 PCIE_RXN3_LAN
25 PCIE_RXP3_LAN
25 PCIE_TXN3_LAN
25 PCIE_TXP3_LAN
42 PCIE_RXN4_NEWCARD
42 PCIE_RXP4_NEWCARD
42 PCIE_TXN4_NEWCARD
42 PCIE_TXP4_NEWCARD
0.1u C0402
0.1u C0402
PCIE_TXN1
PCIE_TXP1
F26
F25
E28
E27
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
C74
C73
0.1u C0402
0.1u C0402
PCIE_TXN2
PCIE_TXP2
H26
H25
G28
G27
C71
C72
0.1u C0402
0.1u C0402
PCIE_TXN3
PCIE_TXP3
K26
K25
J28
J27
PERN3
PERP3
PETN3
PETP3
C70
C77
0.1u C0402
0.1u C0402
PCIE_TXN4
PCIE_TXP4
M26
M25
L28
L27
PERN4
PERP4
PETN4
PETP4
P26
P25
N28
N27
PERN5
PERP5
PETN5
PETP5
T25
T24
R28
R27
PERN6
PERP6
PETN6
PETP6
+V3.3A
Not needed
when sharing SPI flash with
ICH7M and Tekoa
TP41
TP4
R406
10K
R0402
R382
10K
R0402
SPI_SCLK
SPI_CE#
SPI_ARB
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
SPI_SI
SPI_SO
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
+V3.3A
48
USB_OC2#
R403
R394
R408
R384
R389
R386
10K
R0402
10K
10K
10K
10K
10K
44
44
USB_OC0#
USB_OC1#
R0402
R0402
R0402
R0402
R0402
SPI
TP2
TP42
TP3
R407
10K
R0402
PCI-Express
48
48
48
48
C76
C75
USB
PCIE_RXN1_WLAN
PCIE_RXP1_WLAN
PCIE_TXN1_WLAN
PCIE_TXP1_WLAN
Direct Media Interface
U7D
48
48
48
48
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V26
V25
U28
U27
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25 DMI_RXN3
AD24 DMI_RXP3
AC28 DMI_TXN3
AC27 DMI_TXP3
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
R486
24.9_1%
R0402
CLK_PCIE_ICH# 8
CLK_PCIE_ICH 8
DMI_IRCOMP_R
USBRBIAS#
USBRBIAS
D2
D1
12
DMI_RXN[3:0]
12
DMI_RXP[3:0]
12
C25
D25
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
12
DMI_TXP[3:0]
+V1.5S_PCIE_ICH
AE28
AE27
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
DMI_TXN[3:0]
USB_PN0 44
USB_PP0 44
USB_PN1 44
USB_PP1 44
USB_PN2 48
USB_PP2 48
USB_PN3
USB_PP3

of ICH ball,
USB_PN3
USB_PP3
USB_PN4 42
USB_PP4 42
USB_PN5 47
USB_PP5 47
USB_PN6 47
USB_PP6 47
USB_PN7_C
USB_PP7_C
48
48
USB_PN7
USB_PP7
43
43
USB_RBIAS_PN
ICH7M
R385
22.6_1%
R0402
bga652_ich7_koz
42
USB_OC4#
Allocation
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7
USB Devices
Port 1
Port 2
USB Hub
RESERVED
NewCard
Blue Tooth
Finger print
Card Reader
USB2-Sub1
USB2-Sub2
USB2-Sub3
USB2-Sub4
Mini Card1
Mini Card2
Port 3
Camera

of ICH ball,
And avoid routing next to
clock/high speed signals
PCI Pullups
+V3.3S
U7B
A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
GPIO1/REQ5#
GPIO17/GNT5#
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
C/BE0#
C/BE1#
C/BE2#
C/BE3#
B15
C12
D12
C15
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PLTRST#
PCICLK
PME#
C26
A9
B19
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
PCI_REQ#1
PCI_REQ#2
R436
8.2K
R0402
PCI_REQ#3
R434
PCI_REQ#4
1K
R0402
POP = NA
PCI_REQ#5
ICH7 Boot BIOS select

+V3.3S
PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
TP45
TP47
STRAP
GNT5#
GNT4#
11
UNSTUFF
UNSTUFF
PCI
10
UNSTUFF
STUFF
SPI
01
STUFF
UNSTUFF
LPC (default)
R444
8.2K
R0402
22,29,48 PM_CLKRUN#
PLT_RST#
CLK_ICHPCI
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
U20
sot65p190-5 4
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
C435
0.1u
C0402
BUF_PLT_RST# 25,29,40,42,45,48
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
AE9
AG8
AH8
F21
AH20
MCH_ICH_SYNC#
R503
100K
R0603
12
<Variant Name>
Amoi IT Division.
ICH7M
bga652_ich7_koz

Title
Size
C
ENGINEER:
5
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
+V3.3S
1
PLT_RST#
R445
R411
R438
R440
R429
R432
R419
R430
R412
R442
R448
R435
R416
R393
R399
R410
R404
R420
R414
R418
R415
R449
12,22
Buffer to reduce
loading on
PLT_RST#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#5
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
PM_CLKRUN#
SN74LVC1G08DCKR
MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
G8
F7
F8
G7
+V3.3S
PCI_REQ#0
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
ICH7M2
Sheet
1
21
of
49
hexainf@hotmail.com
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
+V3.3A
R469
10K
R0402
SMB_CLK 48
SMB_DATA 48
SMBUS Expander
+V3.3A
+V3.3S
+V3.3A
+V3.3A
R473
8.2K
R0402
+V3.3A
RTC well input requires

pull-down to reduce leakage
from coin cell battery in G3.
Input must not float in G3.
This signal should be connected
to power monitoring logic.
When asserted, PWROK is an
indication to the ICH7M
that ICH7M's Main core well power
(Vcc3_3, Vcc1_5) and PCICLK have
been stable for at least 99 ms.
PWROK can be driven asynchronously.
+V3.3S
D
R499
10K
R0402
R481
10K
R0402
PM_BATLOW#_R
R490
10K
R0402
To KBC GPIO and

use special hotkey control
R471
10K
R0402
POP = NA
+V3.3S
R459
10K
R0402
8 PM_STPPCI#
8 PM_STPCPU#
PM_RI# A28
R458
10K
R0402
POP = NA
40 SMB_ALERT#
29,48 PM_SUS_STAT#
A19
A27
A22
12 PM_BMBUSY#
AB18
SMB_ALERT#
B23
AC20
AF21
GPIO26
BIOS_REC
FWH_MFG_MODE
Default is NO_STUFF
STUFF for BIOS recovery
+V3.3A
R465
0
R0402
POP = NA
R461
+V3.3S
1K
R0402
21,29,48 PM_CLKRUN#
R57
R52
10K R0402
8.2K R0402
GPIO33
GPIO34
25,42,48 PCIE_WAKE#
29,48 INT_SERIRQ
ICH7M does not supprort THRM# based HW Throttling.

Please refer to ICH7M EDS Thermal managemnet section
29,35
VR_PWRGD_CK410
29 SMC_RUNTIME_SCI#
29 SMC_EXTSMI#
SATA_PWR_EN#0_R
SMC_RUNTIME_SCI#_R
SMC_EXTSMI#_R
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
CLK14
CLK48
AC1
B2
SUSCLK
C20
SLP_S3#
SLP_S4#
SLP_S5#
B24
D23
F22
SPKR
SUS_STAT#
SYS_RST#
GPIO0/BM_BUSY#
GPIO11/SMBALERT#
GPIO18/STPPCI#
GPIO20/STPCPU#
A21
GPIO26
B21
E23
GPIO27
GPIO28
AG18
GPIO32/CLKRUN#
AC19
U2
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
F20
AH21
AF20
WAKE#
SERIRQ
THRM#
AD22
VRMPWRGD
AC21
AC18
E21
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
RI#
GPIO6
GPIO7
GPIO8
PWROK
GPIO16/DPRSLPVR
R462
R454
R53
R460
100 R0402
100 R0402
100 R0402
100 R0402
CLK_ICH14 8
CLK_USB48 8
TP52
SLP_S3#_R
SLP_S4#_R
PM_SLP_S5#
AA4 R27
R485
R480
100 R0402
100 R0402
PM_ICH_PWROK
PM_ICH_PWROK
37
AC22
TP0/BATLOW#
PWRBTN#
C23
PM_PWRBTN#_R
LAN_RST#
C19
RSMRST#
Y4
PM_RSMRST#_R R397
R0402
R470
100K
R0603
PLT_RST#
12,21
100 R0402
PATA_PWR_EN#_R
PM_RSMRST# 29
IDE_PATADET 45
LID
41,47
SMC_WAKE_SCI#
R400
10K
R0402
29
R0402
40
+V3.3S
GFX_PRSN#
+V3.3A
bga652_ich7_koz
R476
10K
R0402
+V3.3S
R482
0
R0402
POP = NA
R464
10K
R0402
GPIO33
GPIO34
GPIO35
GPIO26
R452
R383
R467
R453
10K
10K
10K
10K
R0402
R0402
R0402
R0402
R463
R468
R28
10K
R0402
35
PM_PWRBTN# 29
R495
IDE_PATADET_R
E20
A20
F19
SMC_WAKE_SCI#_R
E19
GPIO14
R4
E22
R3
D20
AD21 GPIO35
AD20
R466
0
AE20
ICH7M
PM_DPRSLPVR
PM_DPRSLPVR
PM_BATLOW#_R
10K
10K
R0402
R0402
RTC well input requires

pull-down to reduce leakage
from coin cell battery in G3. C
Input must not float in G3.
This signal should be connected
to power monitoring logic and
should go high no sooner than
10 ms after both VccSus3_3
and VccSus1_5 have reached
their nominal voltages.
+V3.3A
+V3.3A
R387
R472
R388
R456
R491
10K
R0402
R487
10K
R0402
PM_SLP_S3# 29,33,34,36
PM_SLP_S4# 29,33,36
TP55
R0402
C21
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
GPIO
SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3
AF19
AH18
AH19
AE19
SATA
GPIO
+V3.3S
C22
B22
A26
B25
A25
Clocks
SMB_CLK
SMB_DATA
SMB_LINK_ALERT#
SMLINK0
SMLINK1
SMB
U7C
SMB_CLK
SMB_DATA
Q36
D BSS138
sot95p280-3n-gsd
SYS
GPIO
Power MGT
Q35
D BSS138
sot95p280-3n-gsd
8,17,18,42 SMB_CLK_S2
8,17,18,42 SMB_DATA_S2
No Reboot Strap
R446
NO_STUFF by default
1K
STUFF for No Reboot R0402
POP = NA
R477
2.2K
R0402
R500
10K
R0402
R474
2.2K
R0402
R484
10K
R0402
R457
10K
R0402
10K
10K
10K
10K
R0402
R0402
R0402
R0402
POP = NA
SATA_PWR_EN#0_R
SMB_LINK_ALERT#
SMLINK0
SMLINK1
PATA_PWR_EN#_R
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
ICH7M3
Sheet
1
22
of
49
+V1.05S
F6
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
0.1u Layout note: Cap needs be placed

C0402 within 100mils of pin AD17 of ICH7
on the bottom side or 140 mils on
the top
Layout note: Place all Caps

within 100 mils of ICH Ball
+V1.5S_PCIE_ICH
120R
FB1206
1
FB3
CP19
+
C427
C420
C421
330u
C7343
0.1u
C0402
0.1u
C0402
0.1u
C0402
100ohm@100MHz
+V3.3S
C431
0.1u
C0402
L1
1uH
L0805
R100
1u
C0603
1_1%
R0603
AH11
VCC1_5_B[1]
VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCCSUS3_3/VCCLAN3_3[1]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC3_3/VCCHDA
VCC1_5_B[22]
VCC1_5_B[23]VCCSUS3_3/VCCSUSHDA
VCC1_5_B[24]
VCC1_5_B[25]
V_CPU_IO[1]
VCC1_5_B[26]
V_CPU_IO[2]
VCC1_5_B[27]
V_CPU_IO[3]
VCC1_5_B[28]
VCC1_5_B[29]
VCC3_3[3]
VCC1_5_B[30]
VCC3_3[4]
VCC1_5_B[31]
VCC3_3[5]
VCC1_5_B[32]
VCC3_3[6]
VCC1_5_B[33]
VCC3_3[7]
VCC1_5_B[34]
VCC3_3[8]
VCC1_5_B[35]
VCC3_3[9]
VCC1_5_B[36]
VCC3_3[10]
VCC1_5_B[37]
VCC3_3[11]
VCC1_5_B[38]
VCC1_5_B[39]
VCC3_3[12]
VCC1_5_B[40]
VCC3_3[13]
VCC1_5_B[41]
VCC3_3[14]
VCC1_5_B[42]
VCC3_3[15]
VCC1_5_B[43]
VCC3_3[16]
VCC1_5_B[44]
VCC3_3[17]
VCC1_5_B[45]
VCC3_3[18]
VCC1_5_B[46]
VCC3_3[19]
VCC1_5_B[47]
VCC3_3[20]
VCC1_5_B[48]
VCC3_3[21]
VCC1_5_B[49]
VCC1_5_B[50]
VCCRTC
VCC1_5_B[51]
VCC1_5_B[52]
VCCSUS3_3[1]
VCC1_5_B[53]
VCCSUS3_3[2]
VCC3_3[1]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCDMIPLL
VCCSUS3_3[5]
VCCSUS3_3[6]
VCC1_5_A[1]
VCC1_5_A[2]
VCCSUS3_3[7]
VCC1_5_A[3]
VCCSUS3_3[8]
VCC1_5_A[4]
VCCSUS3_3[9]
VCC1_5_A[5]
VCCSUS3_3[10]
VCC1_5_A[6]
VCCSUS3_3[11]
VCC1_5_A[7]
VCCSUS3_3[12]
VCC1_5_A[8]
VCCSUS3_3[13]
VCC1_5_A[9]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSATAPLL
VCCSUS3_3[16]
VCCSUS3_3[17]
VCC3_3[2]
VCCSUS3_3[18]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
VCC1_5_A[18]
B27
GPLL_R_L
AG28
C60
1uH
+V1.5S
Place within 100 mils of

ICH on the bottom side
or 140 mils on the top
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
+V1.5S
C366
C375
0.1u
C0402
0.1u
C0402
+V3.3S
Place within 100 mils of

AD2
C404
+V1.5S
0.1u
C0402
C373
C376
1u
C0603
+V1.5S
0.1u
C0402
C387
TP_VCCSUSLAN1
TP5TP_VCCSUSLAN2
TP44
0.1u
C0402
E3
VCCSUS3_3[19]
C1
VCCUSBPLL
AA2
Y7
ATX
Place within 100 mils of ICH on

the bottom side or 140 mils on
the top near AG9
+V3.3A
ARX
C61
0.01u
C0402 10u
C0805
V5REF_SUS
VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]
VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC PAUX VCC1_05[20]
VCCA3GP
Layout note: Place above

Caps within 100 mils of
near D28, T28, AD28
C379
V5REF[2]
C21
+V1.5S
+V1.5S
V5REF[1]
C412
CP4
+
0.1u
C0402
1u
C0603
330u
C7343
+V3.3A
C378
+V3.3S
+V3.3A
0.1u
C0402
C386
U6
C367
0.1u
C0402
R7
+V1.05S
0.1u
C0402
AE23
AE26
AH26
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
+V3.3S
C417
C423
C430
0.1u
C0402
0.1u
C0402
0.1u
C0402
C402
0.1u
C0402
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
+V3.3S
C403
C382
C408
0.1u
C0402
0.1u
C0402
0.1u
C0402
+V3.3A_RTC
W5
+V3.3A
C383
C384
0.1u
C0402
0.1u
C0402
P7
A24
C24
D19
D22
G19
AB17
AC17
T7
F17
G17
VCC1_5_A[24]
VCC1_5_A[25]
AB8
AC8
K7
C371
C390
0.1u
C0402
0.1u
C0402
+V3.3A
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCCSUS1_05[1]
C400
V5
V1
W2
W7
VCC1_5_A[19]
VCC1_5_A[20]
VCCSUS1_05[2]
VCCSUS1_05[3]
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
ICH7M
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
VCC5REF_SUS
G10
AD17
CORE
Forrin modify,2005.07.03,NET NAME change
U7F
IDE
1u
C0603
VCC5REF
0.1u Layout note: Cap needs be placed
C0402 within 100mils of pin AD17 of ICH7
on the bottom side or 140 mils on
the top
PCI
R23
10
R0603
D2
3BAT54
sot95p280-3n-123C22
C12
1u
C0603
USB
+V5A
R13
10
R0603
D1
3BAT54
sot95p280-3n-123C13
+V3.3A
+V5S
USB CORE
+V3.3S
C385
C380
0.1u
C0402
0.1u
C0402
+V1.5S
C410
TP_ICHVCCSUS1
TP43
C28 TP_ICHVCCSUS2
G20 TP_ICHVCCSUS3
A1
H6
H7
J6
J7
0.1u
C0402
TP57
TP54
+V1.5S
C148
bga652_ich7_koz
U7E
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
<Variant Name>
Amoi IT Division.
www.amoi.com.cn
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
Title
Size
C
ENGINEER:
5
Date:
M515
Sheet
Name
Rev
ICH7M4
Sheet
1
23
of
49
hexainf@hotmail.com
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
0.1u
C0402
10
+V3.3S
CN15
I
C260
C261
10u
C1206
0.1u
C0402
20
SATA_TXP0
20
SATA_TXN0
20 SATA_RXN0
20 SATA_RXP0
+V5S
FB8
+V5S_HDD
60R
FB0805
C238
10u
C1206
C243
C247
C248
10u
C1206
0.1u 0.1u
C0402 C0402
C274
C270
3900p C0603
3900p C0603
R262
4.7
R261
1_1% R0603
R0603
2
3
5
6
TX
TX#
RX#
RX
GND_2M_S_1
GND_2M_S_4
GND_2M_S_7
1
4
7
8
9
10
V_3.3_1
V_3.3_2
V_3.3_3_PC
14
15
16
V_5.0_7_PC
V_5.0_8
V_5.0_9
GND_1M_P_4
GND_2M_P_5
GND_2M_P_6
11
12
13
18
P_RESERVE_11 GND_2M_P_10
17
20
21
22
V_12_13_PC
V_12_14
V_12_15
GND_1M_P_12
19
E1
E2
E1
E2
C249
0.1u
C0402
HDD_CONN
SMD-CN-254X260P-22N
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
SATA HD
B
Sheet
24
of
49
VDD33
+V3.3S
FB37
330R
FB0805
C437
C436
C42
C66
C47
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
C51
C64
0.1u
C0402
0.1u
C0402
C445
22u
C0805
0.1u
C0402
the cap are for U2 RTL8111B VDD33

pins--16, 37, 46 and 53.
FB47
AVDD33
VDD33
GND
330R
FB0805
GND
the cap are for U2 RTL8111B

AVDDH pins-- 2 and 59.
GND
VDD33
The cap are for U2 RTL8111B
AVDDL pins--5, 8, 11 and 14.
Only For 8111B and 8100E application

1
2
CTRL18
Q37
2SB1188
sot150p-3
AVDD18
C444
POP = NA
FB48
C441
22u
C0805
POP = NA
22u
C0805
C62
C68
C63
C446
C67
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
330R
FB0805
GND
R504
REFCLK+
REFCLK-
8 CLK_PCIE_LAN
8 CLK_PCIE_LAN#
EVDD18
0
R0603
C453
C48
C50
4.7u
C0805
0.1u
C0402
0.1u
C0402
HSOP
HSON
0.1u C0402
0.1u C0402
HSIP
HSIN
21 PCIE_TXP3_LAN
21 PCIE_TXN3_LAN
GND
* C38 to C42 are for U2 RTL8111B

VDD1A pins, such as 22 and 28.
Only For 8101E application
C545
C546
21 PCIE_RXP3_LAN
21 PCIE_RXN3_LAN
GND
Remove Q8 and Q9 and use CT12, CT15, L18 and L20 for RTL8101E application.
GND
Remove CT12, CT15, L18 and L20 for RTL8111B & RTL8100E application.
C418
Pin 2 and Pin4

connect to the
outer shield
of the Crystal
and need to connect
to GND for
EMI
XTAL1
C40
C37
C46
C49
C52
C45
C56
C65
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
0.1u
C0402
C424
GND
BLOCK A is only for RTL8101E
application.
R82
R7 value should be 2.49K

(1%) for all application.
+V1.5S
RSET
E1
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCTRL18
AVDD33_1
MDIP0
MDIN0
AVDD18_1
MDIP1
MDIN1
AVDD18_2
MDIP2
MDIN2
AVDD18_3
MDIP3
MDIN3
AVDD18_4
VDD15_1
VDD33_1
GND
CTRL18
AVDD33
MDI0+
MDI0AVDD18
MDI1+
MDI1AVDD18
MDI2+
MDI2AVDD18
MDI3+
MDI3AVDD18
DVDD15
VDD33
Remove R70 for 8111B and 8100E

AVDD18
R507
V_DAC
POP =
GIGALAN Connector
E1
GND
27p
C0402
Only is R50 used when 93C56 is used. NC if

93C46 is used.
VDD33
B
U6
EECS_LAN 1
EESK_LAN 2
EEDI_LAN 3
EEDO_LAN4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
U9
0.1u
C0402
2.49K_1%
R0603
GND
FB51
330R
FB0805
POP = NA
1u
C0603
VDD33
8
7
6
5
CS VCC
SK
DC
DI ORG
DO GND
C43
0.1u
C0402
AT93C46-10TI-2.7
tssop65p570-8n
RSET
VCTRL15
GVDD
CKTAL2
CKTAL1
AVDD33_2
VDD15_11
LED0
LED1
LED2
LED3
VDD33_4
VDD15_10
NC9
NC8
VDD15_9
GND
C55
R48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EESK
EEDI
VDD33_3
EEDO
EECS
VDD15_8
NC7
VDD15_6
NC6
NC5
VDD15_5
VDD33_2
ISOLATEB
NC4
NC3
VDD15_4
NC1
NC2
LANWAKEB
PERSTB
VDD15_2
EVDD18_1
HSIP
HSIN
EGND_1
REFCLK_P
REFCLK_N
EVDD18_2
HSOP
HSON
EGND_2
VDD15_3
1M
R0603
XTAL2
C58
RTL8111B-GR
GND
C41
0.1u
C0402
DVDD15
C39
0.1u
C0402
GND
330R
FB0805
POP =
10u
C0805
C38
VDD33
DVDD15
22u
C0805
FB52
C69
R478
C44
Only For 8101E application
POP = NA
this cap are for U2 RTL8111B VDD1 pins-- 15, 21,

32, 33, 38, 41, 43, 49, 52 and 58.
DVDD15
15K
R0603
Only For 8111B and 8100E application
GND
CRTL15
POP = NA
CRTL15
GVDD
XTAL2
XTAL1
AVDD33
DVDD15
R81
27p
X4
C0402
25MHZ
osc-b276x197mil-4
3K
R0603
EESK_LAN
EEDI_LAN
VDD33
EEDO_LAN
EECS_LAN
DVDD15
GND
VDD33
VDD33
DVDD15
R47
1K
R0402
DVDD15
VDD33
ISOLATEB
R43
15K
R0603
DVDD15
GND
POP =
POP =
POP =
C548
C549
0.01u
C0402
0.01u
C0402
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PAD1
1
2
3
4
5
6
7
8
9
10
11
12
GND
12PIN
SMD-CN-50P-12
<Variant Name>
GND
Amoi IT Division.
Title
GND
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
LAN
Sheet
1
25
of
49
hexainf@hotmail.com
POP =
MDI1+
MDI1V_DAC
MDI2+
MDI2V_DAC
MDI3+
MDI3-
22,42,48
21,29,40,42,45,48
R585
49.9
LANWAKEB
PERSTB
DVDD15
EVDD18
HSIP
HSIN
EGND
REFCLK+
REFCLKEVDD18
HSOP
HSON
EGND
DVDD15
R584
49.9
PCIE_WAKE#
BUF_PLT_RST#
R583
49.9
PAD2
MDI1-
MDI1+
MDI0+
MDI0-
R586
49.9
E2
MDI0-
MDI0+
CN5
+V5A
+V3.3S
D
FB12
330R
FB0805
FB10
330R
FB0805
U14 ALC260-VE
tqfp50p450x450-48n
1
9
4
7
C300
2
10u
C3216
0.1u
C0402
0.1u
C0402
AVDD2
AVDD1
AVSS2
AVSS1
38
25
42
26
NC1
NC2
SPDIFI/EAPD
SPDIFO
45
46
47
48
DVDD1
DVDD2
DVSS1
DVSS2
C339
C319
0.1u
C0402
0.1u
C0402
CT7
10u
C3216
C295
CT6
AGND
R305
20 ACZ_SDATAIN0
20 ACZ_SDATAOUT_C
20 ACZ_BITCLK_C
20 ACZ_SYNC_C
20 ACZ_RST#_C
39
R306 2
R0603
8
5
6
10
11
R0402
SDATA-IN
SDATA-OUT
BIT-CLK
SYNC
RESET#
C299
47p
C0402
POP = NA
27 MICL-VREFO
27 MICR-VREFO
27 AUD_MIC_IN_L
27 AUD_MIC_IN_R
C337
C352
1u
1u
C0805
C0805
C326
C338
1u
C0805
1u
C324
C0805
1u
C0805
R331
4.7K
R350
4.7K
R341
34
13
R319 2 20K
1 R0402
JDREF
40
R311 2 10K
1 R0402
POP = NA
R312 2 4.99K_1%1 R0402
POP = NA
GPIO1
GPIO0
44
43
GPIO3
GPIO2
3
2
28
32
21
22
MIC1-VREFO-L
MIC1-VREFO-R
MIC1-L
MIC1-R
18
CD-L
19
CD-GND
20
CD-R
12
PCBEEP
LINE_OUT_L
LINE_OUT_R
35
36
17
16
15
14
23
24
31
30
29
MIC2-R
HP_OUT_L
MIC2-L
HP_OUT_R
LINE2-R
MONO_OUT
LINE2-L
LINE1-L
LINE1-R
VREF
LINE2-VREFO
MIC2-VREFO
LINE1-VREFO-L
39
41
37
2 0
R0603
MUTE_MIC
27
R330
20K
R0402
AGND
33
1u
C0805
R308
4.7K
R0402
R0402
2
R0402
DCVOL
Sense B
Sense A
C296
R351
4.7K
+V5A
C318
C314
1u
1u
C0805
C0805
R0402
47 MIC2-VREFO
C313
C309
C359
C360
C351
0.1u
0.1u
0.1u
0.1u
0.1u
C350
0.1u
C0805
C0805
C0805
C0805
C0805
C0805
27
R352 2
R346 2
1 0 R0402
1 0 R0402
LINE_OUT_L
LINE_OUT_R
27
27
AC_VREF
B
AGND
47 AUD_MIC2_IN_R
47 AUD_MIC2_IN_L
CT8
C353
10u
C3216
AGND
0.1u
C0402
AGND
FB11
AGND
60R
FB0805
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
ALC260 Codec
B
Sheet
26
of
49
+V5A
HP
FB16
HP_OUT_L
FB15
330R
FB0805
600R
FB0603
TH-CN-1180P-6N
1
2
6
3
4
5
FB18
HP_OUT_R
FB14
330R
FB0805
600R
FB0603
GND J10
conect to claw
R355
2
VDD
1
21
20
EARPHONE_SEL
U16
MAX9755ETI+ HPOUTL
tqfn50p440x440-28n
HPOUTR
14
HP_OUT_L
13
HP_OUT_R
OUTL-
GAIN
OUTL+
26
23
VSS
12
11
GND2
C1N
24
GND1
C1P
CPVSS
CPGND
EARPHONE_SEL
R317
10
SP_OUT_R-
PCB Footprint = R0402
10K
R0603
Q26
DTC144EUA
sot65p210-3n-2132
SP_OUT_LSP_OUT_L+
INL
FB20
600R
FB0603
GND
INR
16
BIAS
HPS
PVDD2
17
R324
0
1
220p
C0603
SP_OUT_R+
18
HPVDD
28
15
SHDN#
PGND1
1u
C0805
C361
220p
C0603
AGND
OUTR-
CPVDD
25
22
C355
C
1K
R0402
100p
C0402
C358
AGND
OUTR+
PVDD1
GND-THERM
NC1
NC2
PGND2
C322
1u
C0805
1u
C0805
26 LINE_OUT_L
29
1
27
2
AGND
AGND
C348
R336
10K
AGND
4.7u
C0805
C336
0.1u 0.1u
C0402
C0402
19
26 LINE_OUT_R
C335C334
4.7u
C0805
R325
R326
10K
10K
POP = NA
29,47 MUTE_KBC#
C317
C340
1K
C349
R0603
R356
100p
C0402
C311
GND
1u
C0805

FB0805-4
GND
AGND
90Rx2
SP_OUT_R+
C354
1u
C0805
SP_OUT_R-
2
5
GND
3
1
2
3
4
CH2
AGND
J3
4pin
88260-0400
FB0805-4
SP_OUT_LSP_OUT_L+
90Rx2
2
3
CH3
MUTE_MIC
FB19
26 AUD_MIC_IN_R
26 AUD_MIC_IN_L
26
5
4
3
6
2
1
FB17
600R
FB0603
AUD_MIC_IN_L
MUTE_MIC
J9
AUD_MIC_IN_R
600R
FB0603
C357
C362
100p
C0402
100p
C0402
TH-CN-1180P-6N
HP
GND
GND
26 MICL-VREFO
MICR-VREFO
MICL-VREFO
R358
4.7K
R0402
R357
4.7K
R0402
conect to claw
AGND
A
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
8
Date:
2
www.amoi.com.cn
M515
Sheet
Name
Rev
Audio speaker&earphone
B
27
Sheet
1
of
49
hexainf@hotmail.com
26 MICR-VREFO
Modem CON
+V3.3A
C277
1u
C0805
J2
R297
20 ACZ_SDATAOUT_M
20 ACZ_SYNC_M
20 ACZ_SDATAIN1
20 ACZ_RST#_M
R299
39
R0603
R0603
1
3
5
7
9
11
2
4
6
8
10
12
Modem
smd-moden-80x580p-12
R298
10K
R0603
R301
0
ACZ_BITCLK_M
R0603
20
R300
10K
R0603
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Modem CON
Sheet
1
28
of
49
+V3.3A
+V3.3A_KBC
+V3.3A_KBC
+V3.3A_KBC
1
+V3.3A_KBC
CT2
W_LAN_I
BT_ON_I
MUTE#_I
TOUCHPAD_EN_I
C35
10u
FAN_ON_A
COUNT_A
30 FAN_ON
30 KBC_FAN_SPEED1
A68
A1
B33
A76
SA_GPIO0
RXD/GPIO62/Bat2
DCD#/GPIO68/Bat2
ADC0/DBM_GPIO0
B76
B52
OUT10/PWM0
GPIO19/FANTACH3
TBDATA
TBCLK
R42
R45
20,48 LPC_AD[3..0]
10K
10K
20,48 LPC_FRAME#
20 ICH_DRQ#0
21,25,40,42,45,48 BUF_PLT_RST#
8
CLK_KBCPCI
21,22,48 PM_CLKRUN#
KBC PULL UP
+V3.3A
SMC_WAKE_SCI#
SMC_EXTSMI#
R78
R75
10K
10K
H_A20GATE
H_RCIN#
SMC_RUNTIME_SCI#
I2C_CLK_K
I2C_DATA_K
INT_R
R70
R71
R441
R61
R443
R54
10K
10K
10K
10K
10K
10K
B8
A5
B6
A6
A7
B7
A9
100 R0402B5
B10
A8
22,48 INT_SERIRQ
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
R50
47
47
TBDATA
TBCLK
41
INT_R
48
RESET_G
41 TOUCH_GPIO1
TP49
TP13
TP53
+V3.3S
1.8432Mhz_IN
SDEBUG_CLK
SDEBUG_DATA
GPIO81/IMDAT
GPIO80/IMCLK
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX
GPIO39/SPDIN/TIN4
LGPIO77/1.8432MHz_IN
GPIO74/MSDATA/SPCLK
GPIO73/MSCLK/SPDOUT
A67
9 CPU_TEMP_DBUS
B47
A50
A4
B4
B3
B2
B1
B48
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
KSO0/SGPIO30
KSO1/SGPIO31
KSO2/SGPIO32
KSO3/SGPIO33
KSO4/SGPIO34
KSO5/SGPIO35
KSO6/SGPIO36
KSO7/SGPIO37
KSO8/GPIO26
KSO9/GPIO27
KSO10/GPIO28
KSO11/GPIO29
KSO12/OUT8/KBRST
KSO13/GPIO18
GPIO4/KS014
GPIO5/KSO15
A23
B21
B20
B19
B18
B17
B16
A17
B15
A16
A15
B14
A14
B13
A53
B51
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
I2C1A_DATA/GPIO44
I2C1A_CLK/GPIO76
B54
A58
DAC1
B67
DAC2
SA_GPIO1
DTR#/GPIO67
A70
B65
A34
ADC6/DBM_GPIO6/Bat2
ADC7/DBM_GPIO7/Bat2
B69
A72
SPI interface
SENSOR0/DBM_GPIO8
THERMAL SENSOR
+V3.3A_KBC
+V3.3A_KBC
R76
R64
10K
10K
C33
5
SMC_ONOFF#
ADP_IN#
U5
0.1u
22,35 VR_PWRGD_CK410
4
2
3
22,33,34,36 PM_SLP_S3#
A66
A64
R74
10K
B60
B11
22,48 PM_SUS_STAT#
A52
22 PM_RSMRST#
B50
22 PM_PWRBTN#
A20
22 SMC_RUNTIME_SCI#
A2
TP10
B38
41 TOUCH_GPIO2
B22
32 RSMRST#_PWRGD
HW_PROTECT#
B63
TP51
R79
0 POP = NA B59
22 SMC_WAKE_SCI#
A61
22,33,36 PM_SLP_S4#
B62
31 SMC_ONOFF#
A46
A47
VCC1RST#
31 ADP_IN#
22,33,34,36 PM_SLP_S3#
SN74LVC1G08DCKR
sot65p190-5
TP46
20
LPCS_PME#
R59
H_A20GATE
22 SMC_EXTSMI#
20
H_RCIN#
0 POP = NA A80
B45
B61
1K
A63
R67
IN2/TIN5
IN0
OUT9/PWM2
GPIO84/LPCPD#
GPIO0/KSO16
GPIO1/KSO17
OUT0/PWM3
TXD/GPIO63
DSR#/GPIO64
CTS#/GPIO66
HW_PROTECT#/DBM_GPIO10
GPIO16/FANTACH2
GPIO15/FANTACH1
SMC_ONOFF#
POWER
PWRGD
VCC1_RST#
Key Board
Matrix
GPIO36/32KHz_OUT/A20M
EC_SCI#/GPIO24
OUT7/SMI#
OUT8/KBRST
32
34
36
39
30
41
43
KSI0/SGPIO40
KSI1/SGPIO41
KSI2/SGPIO42
KSI3/SGPIO43
KSI4/SGPIO44
KSI5/SGPIO45
KSI6/SGPIO46
KSI7/SGPIO47
DEBUG
Interface
Bat Charge
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
C36
Q9
Q10
Q11
Q12
Q8
Q13
Q14
B68
A29
B28
A30
B29
A31
B34
A37
B35
A38
B36
A39
B37
B39
A41
B40
A42
A43
B42
A44
B43
TOUCH PAD
LGPIO70/SPCLK
LGPIO64/SPDIN
LGPIO60/SPDOUT
B66
B72
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
LPC interface
A55
A56
A12
B56
B57
A60
DAC_VCC
ADC_VCC
A19
VSS_PLL
DBM_AGND
A77
A33
B32
A35
A24
B24
A25
B25
A26
A27
B26
A28
FAN interface
B41
B12
SPCLK1 B55
SPDIN1
B75
SPDOUT A62
TP48
TP11
TP14
SER_IRQ
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LRESET#
PCI_CLK
CLKRUN#
FRD
FWR
FCS
FRD#
FWR#
FCS#
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
Share Flash Interface

+V5S
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
FA0
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
45
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A-1/Q15
VCC1
VSS1
VSS2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RST#
OE#
CE#
WE#
RY/BY#
BYTE#
+V3.3A_KBC
0.1u
37
46
27
29
31
33
35
38
40
42
44
12
28
26
11
15
47
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
R44
10K
VCC1RST#
FRD
FCS
FWR
NC4
NC2
NC1
NC3
W_LAN_I
BT_ON_I
MUTE#_I
TOUCHPAD_EN_I
W_LAN_I
BT_ON
MUTE#
DISABLETOUCH
HOT KEY
U19
KH29LV800CBTC7
tsop50p1940-48n
14
10
9
13
47
47
47
47
AGND
VCC1_1
VCC1_2
VCC1_3
VCC1_4
VCC1_5
VCC1_6
VCC1_7
VCC1_8
A18
A79
+V3.3A_KBC
U8
VCC1_PLL
VCCO_BAT
0.1u
A3
A11
A13
B27
A36
B46
A59
A69
10K
10K
10K
10K
R63
R55
R37
R68
+V3.3A_KBC
R492
100K
46
THRM_BAT
C429
PIN12
PIN1
PIN8
PIN9
PIN5
PIN6
PIN3
PIN2
PIN7
PIN11
PIN13
PIN18
PIN14
PIN10
PIN17
PIN15
PIN16
PIN4
PIN23
PIN22
PIN19
PIN20
PIN21
PIN24
47
47
47
47
47
47
47
47
1000p
C
PCB Footprint = C0402
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
+V3.3A_KBC
SMB_BS_DATA
SMB_BS_CLK
R455
R65
Please close
the KBC
possible
10K
10K
SMB_BS_DATA 46
SMB_BS_CLK 46
+V3.3A_KBC
Main Battery
48
A32
3G_ON
40
FF_I
MOT
R38
100K
0 I2C_DATA_K B53
I2C_CLK_K A57
R439
47,48 I2C_DATA
47,48 I2C_CLK
GFXPWRON
48
FF
48
MOT
FF
R41
FF_I
MOT
35 VR_PWRGOOD
48 CAM_EN
35 IMVP_VR_ON
35,37,40 ALL_SYS_VRPWRGD
TPM_TEST1
FIR/CIR interface
IRTX/GPIO71
IRRX/GPIO72
A40
GPIO8/IRRX2
A54
A48
GPIO6/IRMODE/IRRX3A
nPWR_LED/GPIO41
A22
B58
RTS#/GPIO65
RI#/GPIO75
B31
A49
B23
B30
FA22/GPIO35
BAT_LED#/GPIO40
GPIO9/IRTX2
FA20/GPIO33
B64
SENSOR1/DBM_GPIO9
Light sensor
DAC0
ADC4/DBM_GPIO4
A71
A74
GPIO10/IRMODE/IRRX3B
ADC1/DBM_GPIO1
ADC2/DBM_GPIO2
GPIO13/I2C2B_DATA
GPIO14/I2C2B_CLK
B49
B71
A75
A51
A21
ADC5/DBM_GPIO5
ADC3/DBM_GPIO3
OUT11/PWM1
A73
B70
A65
XOSEL
CLOCKI
XTAL1
XTAL2
A78
B9
B73
B74
TEST_PIN/FPGM
B44
&Inveter adjust
LED output
R72
100 R0402
BAT-DEK#
46
CHG
31,47
BAT-DEK#
R77
100K
QFN50P1200X1200-156N
THRM_BAT
46
TP17
BL_ADJ
LIGHT_SENSOR_VOLTAGE
41
TP15
CAP
47
NUM
47
POWER_GREEN 47
POWER_RED 47
LED_TOUCH
47
R62
WIRELESS_RFON 47,48
LED_BT
47
MUTE_KBC# 27,47
KBC_CLOCKIN_14.318
R69
1K
R437
1K
POP = NA
E1
KBC1122
TP16
Second battery
I2C1B_DATA/GPIO77/EMDAT
I2C1B_CLK/GPIO78/EMCLK
PAD
48
R46
FM MODULE
A10
A45
R49
100K
31 SMC_SHUTDOWN#
FA21/GPIO34
TP50
12p
X2
3
<Variant Name>
R60
10M
Amoi IT Division.
32.768KHZ

C54
Title
12p
Size
C
ENGINEER:
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
KBC_1
Sheet
1
29
of
49
hexainf@hotmail.com
C53
10
+V5S
R73
10K
R0603
R66
0
R0805
R0603
J4
D3
1SS355
+V5S
sod2514n
CT3
0.1u
C0402
0.1u
C0402
FGND
+V5S
D20 1SS355
3
C426
10u
C3216
POP = NA
3pin
TH-CN-125P-3AN
C57
R496
10K
R0603FGND
29 KBC_FAN_SPEED1
1
2
3
1
R58
FAN_ON
FAN_ON
Q7
SI2303BDS
sot95p280-3n-123
0.1u
C0402
Q8
DTC144EUAPOP = NA
sot65p210-3n-213
29
2K
C59
R0603
R80
2 N
P
sod2514n
Q34
DTC144EUA
sot65p210-3n-213
R501
10K
R0603
R502
100
R0402
C433
2700p
C0603
FB2
60R
FB0805
FGND
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_Budget
B
Sheet
30
of
49
10
Power Button Detect & Latch
Power
Sequence
05
+V_DC_IN
Q31
AO4419
so63p400-8
C395
1u
C0805
C1210
C32
4.7u
C31
4.7u
C1210
+V_DC
8
7
6
5
R431
390K
R0603
C30
4.7u
C1210
C34
0.1u
C0603
1
2
3
R447
47
R1206
PWRONLATCHG
GND
C398GND
0.1u
C0603
POP = NA
R427
100K
R0603
GND
Q33
BSS138
sot95p280-3n-gsd
G
S
PS_LATCH#
R39
1M
R0603
R40
1M
R0603
GND
Power Sequence
7AC 4BAT
47 POWSW#
D16
1SS355
P sod2514n
D18
1SS355
P sod2514n
D17
N
1SS355
P sod2514n
D19
N
1SS355
P sod2514n
ADP_IN#
29
G
SMC_ONOFF#
ACOK#
29
Q32
BSS138
sot95p280-3n-gsd
G
S
29 SMC_SHUTDOWN#
C28
0.1u
C0805
GND
ACOK#
CELLS
ICOMP
23
22
25
DCPRN
ACPRN
24
26
DCIN
CSON
19
17
VREF
PHASE
16
VCH
CHLIM
UGATE
15
R17
11.3K_1%
R0603
29
D
+V_DC_IN
BOOT
D
8
0
R0603
S
5
6
7
Charge current: 2A
+VBAT
L9
22uH
l-cdrh105r-2
R379
0.015_1%
R2512
Q6
SI4814DY
so63p400-8
C392
10u
C1210
C393
10u
C1210
C396
0.1u
C0603
GND
R3
100K_1%
R0603
GND
D14
1SS355
sod2514n
GND
VAC
R10
45.3K_1%
R0603
R8
VREF
R7
0
R0603
POP = NA
GND
GND
VDD
4.7
R0603
C6
1u
C0603
C29
1u
C0603
B
C15
4.7u
C1210
C10
4.7u
C1210
C11
0.1u
C0805
GND
<Variant Name>
Battery regulation voltage=4.2V

-5%+5%
GND
Amoi IT Division.
R5
0
R0603
POP = NA
R36
2.2
R0603
Iac=((VAC/VREF)*50+53)/Rac=3.43A
7AC
D15
SK34L
sod5227n
CHG_BAT_GATE
C9
0.1u
C0805
R6
VREF
Q30
AO4419
so63p400-8
C27
1u
C0805
14
GND
Ichg=((VCH/VREF)*70+30)/Rch=2.47A
13
GND
PGND
EP
VDDP
18
BGATE
LGATE
SGATE
ICM
GND
20
CSIP
VCOMP
100K_1%
R19
10K
R0603
CSIN
12
VREF
R15
R0603
21
11
C17
0.01u
C0402
CSOP
0
R0603
POP = NA
GND
100p
C0402
4
C18
100p
C0402
POP = NA
+VBAT
ISL6253HRZ
QFN50P500X500-28N
VADJ
C16
0
R0603
POP = NA
GND
U2
10
R14
R18
C394
0.1u
C0603
1
2
EN
VDD
DCSET
1
C19
6800p
C0402
GND
0
R0603
ACLIM
R24
1K
R0402
R25
29,47 CHG
R22
1K
R0402
POP = NA
3 CELLS
ACSET
28
27
VDD
4 CELLS
R20
100K_1%
R0603
GND
C23
0.1u
C0805
GND
Title
GND
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
hexainf@hotmail.com
R29
0
R0603
GND
C5
100p
C0402
POP = NA
Threshold:1.26V
R32
10K_1%
R0603
GND
+V_ADP_IN
R30
15
R0603
GND
R33
2.2
R0603
+V_DC_IN
3
2
1
R31
100K_1%
R0603
R34
100K
R0603
POP = NA
AC current limit: 3.53A

0.02_1%
R2010
5
6
7
8
C24
1u
C0805
R26
R433
100K
R0603
Q5
AO4419
8 so63p400-8 1
7
2
6
3
5
+V_ADP_IN
Rev
none
B
Sheet
31
of
49
+V5A_SYS
+V_DC
+V_DC_SYSTEM
F8 1
2 2A
f1206
+V_DC_IN
R543
100K
R0603
C520
R559
PULSE SKIP MODE
R556
0
R0402
POP = NA
100K
R0603
C518
0.22u
C0603
15p
C0402
R548
470p
C0603
R551
220K
R0603
R540
+V5A_SYS
EN3
UGATE3
26
PGOOD
LGATE3
25
COMP3
LDO3
24
FB3
PGND
23
SHDN#
SKIP#
R542
1
2
0.1u
C0603
22
LDO5
21
REF
LGATE5
20
10
GND
VCC
19
11
FB5
UGATE5
18
12
COMP5
PHASE5
17
0
13
R0603
EN5
BOOT5
16
14
CS5
OUT5
15
+V5A_SYS
C525
3
4.7u
C0805
+V3.3A
L8
3.3uH
l-ihlp-2525cz-01
Q28
SI4814DY
so63p400-8
C524
0.1u
C0805
4.7u
C0805
+V3.3A_SYS
C531
5
6
7
3
C521
+ CP16
150u
C7343
Q24
SI4814DY
so63p400-8
0.1u
C0402
8
R550
2.2
C519
R0603
0.1u
C0603
7
6
5
+V5A
L7
3.3uH
l-ihlp-2525cz-01
C516
0.1u
C0805
R539
2.49K_1%
R0603
Q44
BSS138
sot95p280-3n-gsd
C316
0.1u
C0402
VCC_6232
R538
C502
100K
G
R0603
Q45
BSS138
sot95p280-3n-gsd
2.2
C532
R0603
VIN
+V_DC
R568
28
27
C513
BOOT3
PHASE3
0
3
R0603
0
4
R0603
5
VREF_6232
C514
CS3
0
R0402
+V_DC_IN
R558
C556
0.01u R391
C0402 3.32K_1%
R0603
R566
OUT3
R555
R553
0
R0402
POP = NA
R565
C320
10u
C1210
C515
10u
C1210
+ CP15
150u
C7343
C291
0.1u
C0402
VREF_6232
R567
10K
R0603
ULTRASONIC PULSE SKIPPING MODE
+V3.3A
R392
10.7K_1%
R0603
29 RSMRST#_PWRGD
VCC_6232
FORCED PWM MODE
+V3.3A
1K
R0603
R554
2.49K_1%
R0603
332K_1%
R0603
C310
10u
C1210
R561
C509
10u
C1210
1
2
330p
C0603
U26
ISL6232
QSOP63P619-28N
C526
10p
C0402
C523
C505
0.1u
C0805
0.22u
C0603
+ CE3
100u
CAE660W800HN
1K
R0603
0.22u
C0603
100K
R0603
+V2.5S
U21
AAT3221
SOT23
+V3.3S
C458
0.1u
C0402
+V2.5S
VIN
VOUT
GND
ENBYP/ADJ
R508
39.2K_1%
R0603
C454
22p
C0402
C457
0.1u
C0402
R510
36.5K_1%
R0603
Vout=(39.2+36.5)/36.5*1.205=2.5V
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_System
B
Sheet
32
of
49
S3 & S5 Control
STATE S3
HI
S0
LO
S3
LO
S4/S5
F2
2A
f1206
+V_DC_DDR
C282
0.1u
C0603
C284
10u
C1210
C283
10u
C1210
CE2
+ 100u
CAE660W800HN
Vtrip(mV)=Rtrip(kohm) *10uA
Iocp=Vtrip/Rds(on)+Iripple/2
VDDQ
ON
ON
OFF(Discharge)
VTTREF
ON
ON
OFF(Discharge)
VTT
ON
OFF(HI-Z)
OFF(Discharge)
+V1.8
C
C512
0.1u
C0402
8
7
6
5
C285
10u
C1210
+V_DC
S5
HI
HI
LO
U25 TPS51116PWPtsop65p640-21n
20
VBST
VLDOIN
19
DRVH
VTT
1
2
18
LL
VTTGND
17
DRVL
VTTSNS
16
PGND
GND
+V0.9S
1
2
3
4
R541
+V5A
5.1K
15
R0603
14
13
+V5A
R545
10K
R0603
C510
4.7u
C0805
37 DDRVR_PWRGD
22,29,36 PM_SLP_S4#
R547
22,29,34,36 PM_SLP_S3#
R546
0
R0603
0
R0603
C511
0.1u
C0402
MODE
VTTREF
CS
V5IN
C507
10u
C0805
S5
11
S3
VDDSNS
VDDQSET
MODE
V5IN
VDDQ
S4/GND
C503
10u
C0805
M_VREF
+V5A
COMP
PGOOD
12
PAD
Q43
AO4430
so63p400-8
10
DISCHARGE MODE
No discharge
Tracking discharge
Non-tracking discharge
12,17,18
C508
0.033u
C0603
R552
0
R0402
POP = NA
E1
N
D7
10MQ040N
sod5225n
P
CP26
330u
C7343
POP = NA
1
2
3
0.1u
C0603
8
7
6
5
1.5uH
l-ihlp-2525cz-01
1
CP25
330u
C7343
+
2
C281
0.1u
C0402
L6
C506
+V1.8
R544
15K
R0603
B
POP =
R549
10K 1%
R0603
VDDQSET
GND
V5IN
FB Resistors
VDDQ (V)
2.5
1.8
Adjustable
VTTREF & VTT

VDDQSNS/2
VDDQSNS/2
VDDQSNS/2
NOTE
DDR
DDR2
1.5V< VDDQ<3V
(100*VDDQ-75)kohm
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_DDR2
Sheet
1
33
of
49
hexainf@hotmail.com
Q20
AO4422
so63p400-8
+V1.8
+V_DC_6227
+V_DC_6227
+V_DC
1
R316
10
R0603
F3
2A
f1206
Q21
SI4814DY
so63p400-8
R349
S
1.5K
R0603
GND
BOOT1
24
UGATE2
UGATE1
25
PHASE2
PHASE1
22
ISEN2
ISEN1
27
LGATE2
LGATE1
26
PGND2
PGND1
C287
10u
C1210
BOOT2
C306
0.1u
C0603
D
8
R310
1.5K
R0603
C288
10u
C1210
C290
0.1u
C0603
5
6
7
R353
0
R0402
20
VOUT2
VOUT1
19
VSEN2
VSEN1
10
PG2/REF
PG1
15
EN2
EN1
16
R347
C344
0.01u
C0402
Vo=0.9*(Ru+Rd)/Rd
R345
3.32K_1%
R0603
R344
19.1K_1%
R0603
R342
1K
R0402
POP = NA
1K
21
R0603
17
C341
0.01u
C0402
18
SOFT2
OCSET2
SOFT1
12
OCSET1
11
R309
3.3uH
l-ihlp-2525cz-01
CP12
330u
C7343
CP10
330u
C7343
POP = NA
C255
0.1u
C0402
0
R0402
V1.05S_VRPWRGD
R315
1K
R0603
C305
0.01u
C0402
U15
ISL6227CA-T
ssop63p520-28n
R318
1K
R0402
POP = NA
R307
10.7K_1%
R0603
C294
0.01u
C0402
Vo=0.9*(Ru+Rd)/Rd
R314
15K
R0603
R343
51K
R0603
+V1.5S
L4
Q16
SI4814DY
so63p400-8
14
28
DDR
23
+V_DC_6227
5
6
7
13
C343
4.7u
C0805
+ CP14
330u
C7343
3.3uH
l-ihlp-2525cz-01
D10
1SS355
sod2514n
1
+ CP13
330u
C7343
C239
0.1u
C0402
L5
0.1u
C0603
MAX=4A
C0603
+V5S
+V1.05S
C
0.1u
C307
1
2
C346
VIN
C278
10u
C1210
VCC
C286
10u
C1210
D11
1SS355
sod2514n
N
C272
10u
C1210
2
1
C289
0.1u
C0603
C342
4.7u
C0805
+V_DC_6227
C323
0.1u
C0402
+V5S
+V5S
R313
51K
R0603
+V3.3S
R327
10K
R0603
Rocset=10.3V/[Ioc*rDS/(Risen+140ohm)+8uA]
V1.05S_VRPWRGD
35,37 V1.05S_VRPWRGD
22,29,33,36 PM_SLP_S3#
C297
0.1u
C0603
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_VCCP&VCC_GMCH
Sheet
1
B
34
of
49
+V3.3S
FOR DEBUG
Place these TPs together, and place +V1.05S & GND near them
U12
SN74LVC1G04DCKR
sot65p190-5
4
VR_PWRGD_CK410
C164
0.1u
C0603
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
+V_DC
22,29
2
1
TP18
TP19
TP20
TP21
TP22
TP23
TP24
F7
5A
f1206
C482
1u
D
C0805 POP = NA
+V_DC_CPU
100
CLK_EN#
R135
GND_6262
R136
470K_1%
R0603
0
R0603
C165
0.015u C0402
C175
5600p C0603
GND_6262
VR_TT#
NTC
SOFT
OCSET
GND_6262
0.1u C0603 POP = NA
Rfset(kohm)=(period(us)-0.5)*1.25
9
R150
32
PGND1
33
PVCC
31
NC
25
PGND2
29
UGATE2
27
C163
0.1u
C0603
C176
1u
C0805
C162
0.1u
C0603
C177
1u
C0805
+V5S
R148
1_1%
R0603
PHASE2
28
AGND
LGATE2
30
+V5S
GND_6262
C488
0.018u
C0603
C184
180p
VSUM
R223
10K
R0603
ISEN1
R179
1_1%
R0603
C233
0.22u
C0603
VCC_PRM
C190
0.22u
C0603
1K
R153
R0603
2K
R0603
10
C99
10u
C1210
C106
10u
C1210
C127
1u
C0805
C87
0.1u
C0603
L15
+VCC_CORE_2
Q38
AO4430
so63p400-8
D4
10MQ040N
sod5225n
C0402
R213
R158
Q39
AO4430
so63p400-8
ISEN2
C487
0.068u
C0402
C486
0.018u
C0603
R232
1.5K_1%
R0603
Q40
AO4422
so63p400-8
22
23
24
GND_6262
Q41
AO4422
so63p400-8
4
C178
0.22u
C0603
C91
10u
C1210
POP = NA
VSSSENSE
R236
2.2
R0603
POP = NA
C241
1000p
C0402
POP = NA
G1=Rn/(Rn+Rs)=0.888
3
2
1
10
D6
10MQ040N
sod5225n
+V_DC_CPU
3
2
1
VCCSENSE
+VCC_CORE
0.36uH
lm1150x1000n
GND_6262
ISEN1
10
CE1
+ 100u
CAE660W800HN
+VCC_CORE_1
Q11
AO4430
so63p400-8
5
6
7
8
BOOT2
FB2
49
VDD
ISEN2
ISEN1
FB
12
GND
10 R0603
POP = NA
10 R0603
POP = NA
R162
C135
0.1u
C0603
L18
3
2
1
Q10
AO4430
so63p400-8
C88
1u
C0805
Q9
AO4422
so63p400-8
34
LGATE1
C160
0.22u
C0603
C116
10u
C1210
5
6
7
8
37
39
40
41
42
43
45
46
44
38
VID1
VID2
VID3
VID4
VID5
VID0
PHASE1
26
21
2.67K_1%
R0603
36
C90
10u
C1210
GND_6262
COMP
VIN
R159
C0603
BOOT1
C89
10u
C1210
POP = NA
VW
20
470p
35
11
VSUM
C186
10
R156
R151
R0603
VO
619_1% R0603
3.57K_1%
165K_1%
R0603
19
C0402
DFB
R139
270p
18
C174
DROOP
1500p C0402
RTN
C169
17
51K R0603
16
R141
15
C167
Q42
AO4422
so63p400-8
UGATE1
U11
ISL6262CRZ-T
qfn50p700x700-49n
13
VCC_PRM
VID6
RBIAS
VR_ON
PGD_IN
DPRSTP#
VSEN
R138
PSI#
VDIFF
14
9 H_PROCHOT#
60uA*Rntc>1.18V
147K_1%
R0603
PGOOD
+V_DC_CPU
9 PSI#
DPRSLPVR
29 VR_PWRGOOD
CLK_EN#
3V3
48
R134
10K
R0603
47
C159
1u
C0805
10
5
6
7
8
+V1.05S
R235
150
R0402
H_VID[6..0]
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
+V3.3S
3
2
1
CLK_EN#
29
5
6
7
8
IMVP_VR_ON
5
6
7
8
C483
3
2
1
R526
29,37,40
5
6
7
8
470
R0603
9,20 H_DPRSTP#
ALL_SYS_VRPWRGD
3
2
1
R527
22 PM_DPRSLPVR
100K R0603
POP = NA
1K
R0603
0.1u
C0603
5
6
7
8
R524
PM_DPRSLPVR_1
3
2
1
R0402
3
2
1
R518
PM_EXTTS#1
5
6
7
8
12
R222
2.2
R0603
POP = NA
C235
1000p
C0402
POP = NA
0.36uH
lm1150x1000n
R216
1.5K_1%
R0603
VSUM
R219
10K
R0603
ISEN2
R172
1_1%
R0603
C230
R0603
0.22u
C0603
VCC_PRM
C224
1u
C0805
GND_6262
VCC_PRM
Rdrp2=(2*Rdroop/(G1*DCR)-1)*1k=3.3k ohm
2k
C205
0.068u
C0402
C197
0.33u
C0603
R177
R0603
11.3K_1%
R188
10K
R0402
+V_DC_CPU
R189
R193
2.61K_1%
R0603
VSUM
GND_6262
10
R0603
C208
C0402
0.01u
GND_6262
Rn=5.96K
R209
0
R0805
Place between Inductors
GND_6262
+VCC_CORE
North Side Secondary
1
+ CP7
330u
C7343
C215
1u
C0805
C207
0.1u
C0603
POP = NA
hexainf@hotmail.com
+ CP22
330u
C7343
1
+ CP21
330u
C7343
1
+ CP5
330u
C7343
1
+ CP6
330u
C7343
POP = NA
1
+ CP2
330u
C7343
South Side Secondary
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PWR_VCORE
B
Sheet
35
of
49
S3 Shut Down Power control

+V_DC
+V5A
+V3.3A
C304
1u
C0805
8
7
6
5
Q47
AO4422
so63p400-8
4
Q48
AO4422
so63p400-8
4
1
2
3
+V_DC
1
2
3
C303
1u
C0805
8
7
6
5
R51
100K
+V5S
R320
1K
R0603
R56
100K
D
+V3.3S
C557
0.1u
C0603
Q49
BSS138
sot95p280-3n-gsd
1K
R0603
Q23
BSS138
sot95p280-3n-gsd
G
S
R323
22,29,33,34 PM_SLP_S3#
C
Power Discharge Circuit

+VCC_CORE
Q12
BSS138
sot95p280-3n-gsd
S
Q14
BSS138
sot95p280-3n-gsd G
S
Q15
BSS138
sot95p280-3n-gsd G
R203
47
R0603
R233
470
R0603
R266
220
R0603
Q13
BSS138
sot95p280-3n-gsd G
S
Q22
BSS138
sot95p280-3n-gsd
R303
1M
R0603
22,29,33,34 PM_SLP_S3#
Q18
BSS138
sot95p280-3n-gsd G
S
Q19
BSS138
sot95p280-3n-gsd G
R234
47
R0603
+V1.05S
R302
100K
R0603
R295
97.6_1%
R0603
+V0.9S
R296
97.6_1%
R0603
+V1.5S
+V3.3A
+V3.3S
+V5S
+V1.8
+V3.3A
R278
470
R0603
R338
100K
R0603
Q17
BSS138
sot95p280-3n-gsd
G
Q29
BSS138
sot95p280-3n-gsd
R339
1M
R0603
<Variant Name>
Amoi IT Division.
22,29,33 PM_SLP_S4#

Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
S3_S4_CNTR&Discharge
Sheet
1
B
36
of
49
+V3.3S
C26
0.1u
C0402
33 DDRVR_PWRGD
ALL_SYS_VRPWRGD
29,35,40
+V3.3S
U3
SN74LVC1G08DCKR
sot65p190-5
R35
10K
R0603
C25
0.1u
C0402
11
13
1
4
DELAY_VR_PWRGOOD 2
3
20
PM_ICH_PWROK
22
U4
SN74LVC1G08DCKR
sot65p190-5
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
System_PWRGD
B
Sheet
37
of
49
hexainf@hotmail.com
CLAW32
CLAW33
CLAW31
1
CLAW
CLAW
CLAW
CLAW16
MARK1
MARK8
MARK6
MARK5
1
MARK3
MARK2
MARK7
CLAW34
1
CLAW
MARK4
CLAW35
1
CLAW
CLAW
CLAW8
1
MARK9
MARK12
MARK14
MARK10
MARK11
MARK13
CLAW7
CLAW
CLAW13
1
CLAW
CLAW
CLAW36
CLAW11
CLAW23
CLAW25
1
1
1
CLAW
CLAW
CLAW
CLAW
CLAW20
CLAW19
1
1
CLAW
CLAW
CLAW4
1
CLAW
CLAW17
CLAW18
CLAW22
CLAW15
1
1
CLAW
CLAW
CLAW
CLAW
CLAW5
CLAW10
CLAW9
1
CLAW3
CLAW12
1
1
CLAW21
CLAW6
1
1
CLAW
1
1
CLAW
CLAW
CLAW
CLAW
CLAW
CLAW
CLAW2
CLAW24
CLAW14
CLAW1
1
1
1
1
CLAW
CLAW
CLAW
CLAW
<Variant Name>
Amoi IT Division.
Title
Size
E
ENGINEER:
5
<EngName>
1
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
ME
B
Sheet
38
of
49
LVDS
R375
0
R0402
CN_L_DDC_CLK
R376
0
R0402
CN_L_DDC_DATA
12 GM_LA_CLKN
R370
0
R0402
CN_LA_CLKN
40,41
12 GM_LA_CLKP
R369
0
R0402
CN_LA_CLKP
40,41
12 GM_LA_DATAN0
R373
CN_LA_DATAN0
40,41
12 GM_LA_DATAN1
R371
0
R0402
CN_LA_DATAN1
40,41
12 GM_LA_DATAN2
R377
0
R0402
CN_LA_DATAN2
40,41
12 GM_LA_DATAP0
R372
0
R0402
CN_LA_DATAP0 40,41
12 GM_LA_DATAP1
R374
0
R0402
CN_LA_DATAP1 40,41
12 GM_LA_DATAP2
R378
0
R0402
CN_LA_DATAP2 40,41
12 L_DDC_CLK
40,41
12 L_DDC_DATA
0
R0402
40,41
CRT
12
GM_CRT_R
R367
0
R0402
CN_CRT_R
12
GM_CRT_G
R366
0
R0402
CN_CRT_G 40,48
12
GM_CRT_B
R359
0
R0402
CN_CRT_B 40,48
R361
0
R0402
CN_CRT_DDC_CLK
R360
0
R0402
CN_CRT_DDC_DATA
12 GM_CRT_HSYNC
R362
39
R0402
CN_CRT_HSYNC
40,48
12 GM_CRT_VSYNC
R363
39
R0402
CN_CRT_VSYNC
40,48
12
L_BKLTEN
R364
1K
R0402
CN_L_BKLTEN 40,41
12
L_VDDEN
R365
1K
R0402
CN_L_VDDEN
12 GM_CRT_DDC_DATA
40,48
B
40,48
40,41
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
GFX SWITCH
B
Sheet
39
of
49
hexainf@hotmail.com
12 GM_CRT_DDC_CLK
B
40,48
R11
R16
PEG_RXN0
PEG_RXP0
PEG_RXN1
PEG_RXP1
PEG_RXN2
PEG_RXP2
PEG_RXN3
PEG_RXP3
PEG_RXN4
PEG_RXP4
PEG_RXN5
PEG_RXP5
PEG_RXN6
PEG_RXP6
PEG_RXN7
PEG_RXP7
PEG_RXN8
PEG_RXP8
PEG_RXN9
PEG_RXP9
PEG_RXN10
PEG_RXP10
PEG_RXN11
PEG_RXP11
PEG_RXN12
PEG_RXP12
PEG_RXN13
PEG_RXP13
PEG_RXN14
PEG_RXP14
E1
PEG_RXN15
PEG_RXP15
CN14
CONN-BTB
1 SMD-CN-80X455P-100N
100
2
99
3
98
4
97
5
96
6
95
7
94
8
93
9
92
10
91
11
90
12
89
13
88
14
87
15
86
16
85
17
84
18
83
19
82
20
81
21
80
22
79
23
78
24
77
25
76
26
75
27
74
28
73
29
72
30
71
31
70
32
69
33
68
34
67
35
66
36
65
37
64
38
63
39
62
40
61
41
60
42
59
43
58
44
57
45
56
46
55
47
54
48
53
49
52
50
51
CLK_PCIE_VGA 8
CLK_PCIE_VGA# 8
PEG_TXN0
PEG_TXP0
PEG_TXN[15..0] 12
PEG_TXP[15..0] 12
PEG_TXN1
PEG_TXP1
39,41 CN_LA_CLKP
39,41 CN_LA_CLKN
PEG_TXN2
PEG_TXP2
39,41 CN_LA_DATAN2
39,41 CN_LA_DATAP2
PEG_TXN3
PEG_TXP3
PEG_TXN4
PEG_TXP4
12 MCH_CFG_20
PEG_TXN5
PEG_TXP5
22 GFX_PRSN#
PEG_TXN6
PEG_TXP6
R368
39,41 CN_LA_DATAN1
39,41 CN_LA_DATAP1
0
R0402
39,41 CN_LA_DATAN0
39,41 CN_LA_DATAP0
GFX_PRSN#
39,41 CN_L_DDC_DATA
39,41 CN_L_DDC_CLK
29,35,37 ALL_SYS_VRPWRGD
+V3.3S
PEG_TXN7
PEG_TXP7
29
PEG_TXN8
PEG_TXP8
GFXPWRON
+V5S
PEG_TXN9
PEG_TXP9
PEG_TXN10
PEG_TXP10
+V_DC
PEG_TXP15
PEG_TXN15
CN11
CONN-BTB
1 SMD-CN-80X455P-60N
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21
40
22
39
23
38
24
37
25
36
26
35
27
34
28
33
29
32
30
31
CN_CRT_R
39,48
C
CN_CRT_G 39,48
CN_CRT_B 39,48
CN_CRT_DDC_DATA 39,48
CN_CRT_DDC_CLK 39,48
CN_CRT_HSYNC 39,48
CN_CRT_VSYNC 39,48
CN_L_BKLTEN 39,41
CN_L_VDDEN 39,41
+V1.8
E2
12 PEG_RXN[15..0]
12 PEG_RXP[15..0]
R0402 0
R0402 0
POP = NA
E1
9,12,20 PM_THRMTRIP#
22 SMB_ALERT#
BUF_PLT_RST#
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
E2
21,25,29,42,45,48
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
GPU Connector
B
Sheet
40
of
49
LCD CON"
cable
1 GND
2 VDD
3 VDD
4 VEEDID
5 NC1
6 CLKEDID
7 DATAEDID
8 RxIN09 RxIN0+
10GND
11RxIN112RxIN1+
13GND
14RxIN215RxIN2+
16GND
17RxCLKIN18RxCLKIN+
19GND
20GND
1 VDD
2 VDD
3 L_DDC_CLK_V/CLKEDID
4 L_DDC_DATA_V/DATAEDID
5 GND
6 LA_DATAP0/RxIN0+
7 LA_DATAN0/RxIN08 GND
9 LA_DATAP1/RxIN1+
10LA_DATAN1/RxIN111GND
12LA_DATAP2/RxIN2+
13LA_DATAN2/RxIN214VEEDID
15LA_CLKN/RxCLKIN16LA_CLKP/RxCLKIN+
LCD_VCC
+V3.3S
FB1
2 Q2
SI2316DS
sot95p280-3n-123
3
+V_DC
C7
1000p
C0402
R9
47K
180R
FB0603
C1
+V_DC
C547
10u
C0805
20LCD_BACK
19GND
18BJ_ENABLE
17BL_ADJ
F1
2A
f1206
C8
1u
C0805
0.01u
C0402
R0603
0.01u
C0402
Q4
BSS138
sot95p280-3n-gsd
G
S
LCD_BACK
C3
0.1u
C0402
C4
R12
10K
R0603
LCD_BACK 1
GND 2
BJ_ENABLE 3
BL_ADJ 4
IPEX 30PIN CON"
Q3
BSS138
sot95p280-3n-gsd
J1
+V3.3A
29 TOUCH_GPIO1
29
INT_R
29 TOUCH_GPIO2
5pin
SMD-CN-100P-5L5
4
3
2
1
E2
39,40 CN_L_VDDEN
+V3.3S
22
17
18
19
20
17
18
19
20
R4
10K
R0603
4
2
CN_LA_DATAP0 39,40
CN_LA_DATAN0 39,40
Q1
BSS138
Gsot95p280-3n-gsd
CN_L_BKLTEN 39,40
CN_LA_DATAP1 39,40
CN_LA_DATAN1 39,40
+V3.3S
CN_LA_DATAP2 39,40
CN_LA_DATAN2 39,40
R2
10K
R0603
CN_LA_CLKN 39,40
CN_LA_CLKP 39,40
BLON
BL_ADJ
29
LCD_BACK
LID
LCD
SMD-CN-100P-20L
22,47
R1
10K
R0603
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
LCD Connector
B
Sheet
41
of
49
hexainf@hotmail.com
E2
C2 U1 SN74LVC1G02DCKR
sot65p190-5
0.1u
C0402
1
CN_L_DDC_CLK 39,40
CN_L_DDC_DATA 39,40
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
E1
B
LCD_VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
E1
+V3.3S
CN1
10
J
+V3.3A
USB_OC4#
R587
10K
R0603
+V3.3A
Express Card CONN
U28
BUF_PLT_RST#
+3.3V_NEWCARD
C555C554
PERST#
10u 0.1u
C0805
C0402
POP = NA
6
20
1
2
4
3
5
8
16
7
SYSRST
SHDN
STBY
3.3VIN1
3.3VIN2
3.3VOUT1
3.3VOUT2
PERST
NC
GND
PAD
21,25,29,40,45,48
+V3.3A
OC
RCLKEN
AUXIN
AUXOUT
1.5IN2
1.5IN1
1.5OUT2
1.5OUT1
CPPE
CPUSB
19
18
17
15
14
12
13
11
10
9
+V3.3AUX_NEWCARD C553C552
+V1.5S
10u 0.1u
C0805
C0402
POP = NA
+1.5V_NEWCARD
C551C550
CPPE#
CPUSB#
TPS2231PW
POP = NA
POP = NA
10u 0.1u
C0805
C0402
POP = NA
E1
21
R588
10K
R0603
POP = NA
POP = NA
+V3.3A
USB_OC4#
R354
R348
10K
R0603
21
10K
R0603
+V3.3A
U17
BUF_PLT_RST#
+3.3V_NEWCARD
C331C332
PERST#
10u 0.1u
C0805
C0402
1
2
3
4
5
6
7
8
9
10
SYSRST
SHDN
STBY
3.3VIN1
3.3VIN2
3.3VOUT1
3.3VOUT2
PERST
NC
GND
PAD
21,25,29,40,45,48
+V3.3A
OC
RCLKEN
AUXIN
AUXOUT
1.5IN2
1.5IN1
1.5OUT2
1.5OUT1
CPPE
CPUSB
20
19
18
17
16
15
14
13
12
11
+V3.3AUX_NEWCARD C347C356
+V1.5S
10u 0.1u
C0805
C0402
+1.5V_NEWCARD
C330C321
CPPE#
CPUSB#
10u 0.1u
C0805
C0402
+1.5V_NEWCARD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CPUSB#
8,17,18,22 SMB_CLK_S2
8,17,18,22 SMB_DATA_S2
+V3.3AUX_NEWCARD
C301C293C298
USB_PN4
USB_PP4
22,25,48 PCIE_WAKE#
PERST#
+3.3V_NEWCARD
10u 0.1u 1u C308C312C315

C0805
C0402
C0603
10u 1u 0.1u C329C328C327
C0805
C0603
C0402
10u 0.1u 1u
C0805
C0402
C0603
CPPE#
8 CLK_PCIE_NEWCARD#
8 CLK_PCIE_NEWCARD
21 PCIE_RXN4_NEWCARD
21 PCIE_RXP4_NEWCARD
21 PCIE_TXN4_NEWCARD
21 PCIE_TXP4_NEWCARD
GND1
USBUSB+
CPUSB#
RESERVED1
RESERVED2
RESERVED3
SMBCLK
SMBDATA
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V1
+3.3V2
CLKREQ#
CPPE#
REFCLKREFCLK+
GND2
PERNO
PERPO
GND3
PETN0
PETP0
GND4
PAD2
21
21
PAD1
CN7A
E1
E1
TPS2231PW
E2
NEWCARD_CONN
C
CN7B
E3
GND1
GND2
E4
NEWCARD_CONN
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
PCMCIA CNN
B
Sheet
42
of
49
10
+V3.3S
J
R560
10K
R0603
R557
10K
R0603
R564 R570
10K
10K
R0603 R0603
SDCDN
D25
N
1SS355
P sod2514n
MSINS
D23
N
1SS355
P sod2514n
CR_V3.3
C541
10u
C0805
C542
0.1u
C0402
1
2
5
6
SMCDN
D
D24
N
XDCDN
1SS355
P sod2514n
R571
1K
R0603
Q46
AO6409
ssot95p-6
3 G
S
C534
1u
C0603
R572
10K
R0603
+V3.3S
CPWR_V33
H
R577
47K
R0603
CPWR_V33
R578
3K
R0603
R579
3K
R0603
R580
3K
R0603
CN9
XDCDN
C544
0.1u
C0402
C504
0.1u
C0402
S4
X20
X18
SD-4P(VCC)
XD_18-2P(VCC2)
XD_18P(VCC1)
X19
X1
X9
S3
S6
M1
M10
E1
E2
XD_1-2P(GND1)
XD-1P(GND)
XD-9P(GND)
SD-3P(GND)
SD-6P(GND)
MS-1P(GND)
MS-10P(GND)
GND
GND1
X2
X3
X4
X5
X6
X7
X8
X10
X11
X12
X13
X14
X15
X16
X17
MS-2P(BS)
MS-4P(D0)
MS-5P(D2)
MS-6P(INS)
MS-7P(D3)
MS-8P(CLK)
MS-3P(D1)
M2
M4
M5
M6
M7
M8
M3
SD-SW-CD1
SD-7P(DAT0)
SD-8P(DAT1)
SD-9P(DAT2)
SD-1P(DAT3)
SD-2P(CMD)
SD-5P(CLK)
SD-SW-WP1(SW-WP1)
E3
S7
S8
S9
S1
S2
S5
E4
4IN1 TAI-SOL\
CONTROLOUT0
CARDDATA0
CARDDATA2
MSINS
CARDDATA3
CONTROLOUT1
CARDDATA1
SDCDN
CARDDATA4
CARDDATA5
CARDDATA6
CARDDATA7
CARDDATA0
CONTROLOUT0
CARDDATA2
CARDDATA15
CARDDATA14
CARDDATA13
CARDDATA12
CARDDATA11
CARDDATA10
CARDDATA9
CARDDATA8
CARDDATA7
CARDDATA6
CARDDATA5
CARDDATA4
CARDDATA3
CARDDATA2
CARDDATA1
CARDDATA0
CR_V3.3
R575
47K
R0603
C540
0.1u
C0603
SMWP
R574
6.34K_1%
R0603
CARDDATA1
CR_V3.3
R576
PLL VDD 2.5V
CR_V2.5
FB26
CR_V3.3
ANALOG POWER 3.3V
1
2
3
4
5
6
7
8
9
10
11
12
10K
R0603
FB25
180R
FB0603
180R
FB0603
R573
C535
0.1u
C0402
21
C539
21
0.1u
1.5K
R0603
USB_PP7
USB_PN7
C0402
C533
0.1u
C0402
POP = NA
CARDDATA15
CFWTN
CLED
CHIPRESETN
GNDA
VDDA
RPU
AVDD
DP
DM
AVSS
RREF
CARDDATA2
CARDDATA1
CARDDATA0
GND
VDD
CONTROLOUT0
CONTROLOUT1
CONTROLOUT2
CONTROLOUT3
CONTROLOUT4
CONTROLOUT5
XDCDN
U27
AU6366
tsqfp50p900x900-48n
CR_V2.5
C538
0.1u
C0402
36
35
34
33
32
31
30
29
28
27
26
25
R569
1K
R0603
CONTROLOUT0
CONTROLOUT1
CONTROLOUT2
CONTROLOUT3
CONTROLOUT4
CONTROLOUT5
C536
0.1u
C0402
POP = NA
C537
0.1u
C0402
POP = NA
13
14
15
16
17
18
19
20
21
22
23
24
SD/XD/SM/MS
CARDDATA3
CONTROLOUT4
CONTROLOUT3
CONTROLOUT1
CONTROLOUT2
CONTROLOUT5
SMWP
CARDDATA8
CARDDATA9
CARDDATA10
CARDDATA11
CARDDATA12
CARDDATA13
CARDDATA14
CARDDATA15
48
47
46
45
44
43
42
41
40
39
38
37
C543
0.1u
C0402
XD-2P(R/-B)
XD-3P(-RE)
XD-4P(-CE)
XD-5P(CLE)
XD-6P(ALE)
XD-7P(-WE)
XD-8P(-WP)
XD-10P(D0)
XD-11P(D1)
XD-12P(D2)
XD-13P(D3)
XD-14P(D4)
XD-15P(D5)
XD-16P(D6)
XD-17P(D7)
CARDDATA14
CARDDATA13
CARDDATA12
CARDDATA11
CARDDATA10
CARDDATA9
CARDDATA8
CARDDATA7
CARDDATA6
CARDDATA5
CARDDATA4
CARDDATA3
MS-9P(VCC)
PVDD
XI
XO
PVSS
VDD25V
VDDH
CPWR_V33
VSSH
MSINS
SMCDN
CFCDN
SDCDN
M9
XDCDN
SDCDN
MSINS
XI
XO
SMCDN
CR_V2.5
CR_V3.3
+V3.3S
CFCDN
C529
0.1u
C0402
C528
0.1u
C0402
OUTPUT: CARD POWER 3.3V
XO
R562
C517
33K
R0603
CPWR_V33
X5
12MHZ
osc-b276x197mil-4
20p
C0402
C522
C530
0.1u
C0402
C527
0.1u
C0402
R563
220K
R0603
XI
20p
C0402
X6
12MHZ
OSC380P500X320-2N
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
hexainf@hotmail.com
B
2
Rev
CARD READER
B
Sheet
43
of
49
+V5S
60R
FB0805
+V5_USB0_A
F6
1.1A
f1206
+V5_USB0
FB23
+V5_USB0
CP1
+
C443
C79
U10
21
USB_PP0
21
USB_PN0
CH4
90Rx2
VBUS
D_PLUS
GND2
GND3
GND4
D_MINUS
GND1GND5
21
D22
USB0005DP
c0402
POP = NA
0.1u
C0402
2
4
2
1
C78
1
FB0805-4
R99
562_1%
R0603
USB_OC0#
USB_OC0#
1
3
0.1u
C0402
150u 470p
C7343 C0603
R101
470
R0603
D21
USB0005DP
c0402
POP = NA
E1
E2
E3
E4
C
USB
THR-CN-250P1310-4N
conect to claw
+V5S
60R
FB0805
+V5_USB1_A
F4
1.1A
f1206
+V5_USB1
FB13
+V5_USB1
CP17
C333
+
U18
C345
USB_OC1#
USB_OC1#
21
USB_PP1
21
USB_PN1
USB_PN1
CH1
90Rx2
1
FB0805-4
3
2
2
4
1
C325
D12
USB0005DP
c0402
POP = NA
0.1u
C0402
D13
USB0005DP
c0402
POP = NA
VBUS
D_PLUS
GND2
GND3
GND4
D_MINUS
GND1GND5
150u 470p
C7343 C0603
USB_PP1
R340
562_1%
R0603
21
1
3
E1
E2
E3
E4
USB
THR-CN-250P1310-4N
0.1u
C0402
R337
470
R0603
conect to claw
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
USB
Sheet
1
44
of
49
DVDROM CON
+V5S
+V5S_ODD
FB24
20 IDE_PDD[15..0]
R105
8.2K
R0402
20
R102 39 R0603
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDIOW#
20 IDE_PDIORDY
20
INT_IRQ14
20
IDE_PDA1
20
IDE_PDA0
20 IDE_PDCS1#
+V3.3S
R108
ODD_LED#
10K
R0603
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
R120
470
R0603
LOUT
AGND
RESET#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND1
DIOW#
IORDY
INTRQ
DA1
DA0
CS0#
DASP#
+5V2
+5V4
GND3
GND5
CSEL
NC49
E2
R104
4.7K
R0402
BUF_PLT_RST#
E2
+V3.3S
21,25,29,40,42,48
E1
E1
J5
ROUT
GND8
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
MDARQ
DIOR#
GND2
DMACK#
IOCS16#
PDIAG#
DA2
CS1#
+5V1
+5V3
+5V5
GND4
GND6
GND7
NC50
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
C120
C109
C114
C461
0.1u
C0603
0.1u
C0603
0.1u
C0603
10u
C1206
60R
FB0805
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ 20
IDE_PDIOR# 20
IDE_PDDACK#
20
IDE_PATADET 22
IDE_PDA2
20
IDE_PDCS3#
20
R107
10K
R0603
ODD
TH-CN-160X110P-50AN
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
DVDROM
Sheet
1
45
of
49
hexainf@hotmail.com
10
Power Sequence
1BAT
120R
FB1206
FB21
120R
FB1206
CN10
1
F5
7A
f6125
R581
R582
29
29
THRM_BAT
BAT-DEK#
THRM_BAT
29 SMB_BS_CLK
29 SMB_BS_DATA
R493
10
FB22
E1
C364
0.1u
C0603
+VBAT
0
0
R0603
1 PACK+1
2 PACK+2
3 R0603
CNT1
4 R0603
CNT2
5 SMBC
6 SMBD
7 TEMP
8 PACK-1
9 PACK-2
11
Battery Connector
BATTERY
SMD-CN-200P-9AN
E2
In Battery Package,
have internal 10K pull low,
so external pull high use 100K
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Battery Connector
B
Sheet
46
of
49
Keyboard Connector
+V3.3A_KBC
E1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PIN12
PIN1
PIN8
PIN9
PIN5
PIN6
PIN3
PIN2
R90
R87
R86
R89
R85
R83
R84
R88
10K
10K
10K
10K
10K
10K
10K
10K
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
Connector
+V3.3S
C96
21
21
0.1u
C0402
GND2
Button Function Board
CN4
1
2
3
4
5
6
USB_PP6
USB_PN6
E2
29
29
29
29
29
29
29
29
E1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
smd-cn-50p-6
6PIN
Connector
E2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
GND1
CN3
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
25pin
SMD-CN-100P-25N
E1
E2
E3
+V5S
21
21
2
4
6
8
10
12
USB_PP5
USB_PN5
29
LED_BT
J8
1
3
5
7
9
11
E4
E5
E6
Modem
C
SMD-CN-80X580P-12AN
+V5S
LSW2
C137C129
R333
4.7K R0402
R328
4.7K R0402
12
11
10
9
8
7
6
5
4
3
2
1
4.7u 0.1u
C0805
C0402
GND
CN6
12PIN
SMD-CN-50P-12
GND_TP
12
11
10
9
8
7
6
TBCLK
5
TBDATA
4
3
2
1
4PIN
SW_DTSM_4N
LSW1
TBCLK
TBDATA
429 4
29
2
4PIN
E1
26 MIC2-VREFO
PAD1
PAD2
E2
C477
C478
47p
C0402
47p
C0402
SW_DTSM_4N
GND
GND
GND
Connect to Touch
PAD
R334
R329
26 AUD_MIC2_IN_R
26 AUD_MIC2_IN_L
0
0
CN2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
29 W_LAN_I
29 BT_ON
31
+V3.3A_SYS
POWSW#
29 DISABLETOUCH
29 MUTE#
29,48 I2C_DATA
29,48 I2C_CLK
29,31 CHG
29 POWER_RED
29 POWER_GREEN
AGND
29 NUM
29 CAP
+V3.3S
E1
E1
E2
E2
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
SMD-CN-50P-24AN
20 ATA_LED#
22,41 LID
29,48
29
29
27,29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
WIRELESS_RFON
LED_BT
LED_TOUCH
MUTE_KBC#
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
KBC CON
Sheet
1
47
of
49
hexainf@hotmail.com
24pin
A
+V3.3S
+V1.5S
+V3.3A
D
BUF_PLT_RST#
BUF_PLT_RST#
21 USB_PN3
21 USB_PP3
E1
29 3G_ON
22,25,42 PCIE_WAKE#
29,47 WIRELESS_RFON
22 SMB_CLK
22 SMB_DATA
29
CAM_EN
21 USB_OC2#
+V_ADP_IN
CN12
60 60PIN
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
CN_CRT_VSYNC 39,40
CN_CRT_DDC_DATA 39,40
CN_CRT_DDC_CLK 39,40
CN_CRT_HSYNC 39,40
CN_CRT_B 39,40
CN_CRT_G 39,40
CN_CRT_R
39,40
USB_PN2
USB_PP2
21
21
CLK_PCIE_SOCKET2
CLK_PCIE_SOCKET2#
PCIE_RXN1_WLAN
PCIE_RXP1_WLAN
8
8
21
21
PCIE_TXN1_WLAN 21
PCIE_TXP1_WLAN 21
E3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+V5S
21,25,29,40,42,45
E4
E5
E6
E2
GND
GND
CN13
TPM_TEST1
PM_SUS_STAT#
INT_SERIRQ
PM_CLKRUN#
29
TPM_TEST1
22,29 PM_SUS_STAT#
22,29 INT_SERIRQ
21,22,29 PM_CLKRUN#
RESET_G
FF
MOT
E1
29
RESET_G
29,47 I2C_CLK
29,47 I2C_DATA
29 FF
29 MOT
E4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PCIE_RXN2_WWLAN
PCIE_RXP2_WWLAN
21
21
PCIE_TXN2_WWLAN
PCIE_TXP2_WWLAN
21
21
E3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
E2
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLK_TPM
E5
E6
60PIN
20,29 LPC_FRAME#
20,29
LPC_AD0
20,29
LPC_AD1
20,29
LPC_AD2
20,29
LPC_AD3
8
CLK_TPM
GND
GND
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
5
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
Rev
Touch PAD and LED
B
Sheet
48
of
49
10
J
Change List:
Date
Page Change Description
B
<Variant Name>
Amoi IT Division.
Title
Size
C
ENGINEER:
<EngName>
Date:
www.amoi.com.cn
M515
Sheet
Name
hexainf@hotmail.com
Rev
Touch PAD and LED
B
Sheet
49
of
49

Amoi M515 REV B

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5

INTEL NAPA Platform

Part Value Prefix : "@" means nopop

295 Lane, Zuchongzhi Road, Zhangjiang,

Friday, December 22, 2006

Friday, December 22, 2006

labbeled SMB_ICH_xx come out of ICH,

IRQ ROUTING & SMBUS

Friday, December 22, 2006

+V1.05S(For Core,CPU I/O)

295 Lane, Zuchongzhi Road, Zhangjiang,

Friday, December 22, 2006

POWER Delivery Architectural Block Diagram

G3 shut down power

S4,S5 shut down power

S3 shut down power

DDR2 POWER Module

1.05/1.5V POWER Module

SYSTEM POWER Module

2.5V POWER Module

295 Lane, Zuchongzhi Road, Zhangjiang,

Friday, December 22, 2006

Friday, December 22, 2006

Power Down Sequence

Need confirm the power sequency

CPU Power Down Sequence

295 Lane, Zuchongzhi Road, Zhangjiang,

Friday, December 22, 2006

1:Set pin36/35 to CPU_ITP

1:Set pin17/18 to 100MHZ

1:Set pin32/33 as clock request pin

Friday, December 22, 2006

Intel ITP DEBUG PORT

07.13:debug port NC comfirm

Friday, December 22, 2006

Place these inside socket

Place these inside

Place these inside socket

If use Low Inductance Low-Frequency Decoupling Cap

Place these inside socket

Friday, December 22, 2006

Trace should be 10-mil wide

Signal voltage level = 0.3125*Vcc1_05

Trace should be 10-mil wide

Signal voltage level = 2/3 of Vcc1_05

Signal voltage level = 0.3125*Vcc1_05

Friday, December 22, 2006

MCH Strapping Options Summary

Reserve PCIE Graphics Lanes

0 = Dynamic ODT Disabled

Friday, December 22, 2006

Friday, December 22, 2006

Friday, December 22, 2006

Friday, December 22, 2006

Friday, December 22, 2006

Layout Note: Place these Hi-Freq

Friday, December 22, 2006

Layout Note: Place these Hi-Freq

Friday, December 22, 2006

Friday, December 22, 2006

RTCRST# requeres 18-25ms delay.

Distance between the ICH-7 M

ICH7 internal VR enable strap

Place within 500mils