High Institute for Engineering & Technology, AL-Obour

Electrical Eng. Dept, 4th Year, Electronics & Comm. Section

Course Title :

Electronics for Instrumentations ELC (426)

Sheet 6

Instructor: Dr. Eng. Ibrahim F.Tarrad

Eng. Saad ELsayed

Problem 6.1: A PLL is locked onto an incoming signal with a frequency of 1 MHz at
a phase angle of 50 o. The VCO signal is at a phase angle of 20 o. The peak amplitude
of incoming signal is 0.5V and that of the VCO output signal is 0.7V.
a. What is the VCO frequency?
b. What is the value of the control voltage being fed back to the VCO at this
point?
Problem 6.2: The output frequency of a certain VCO changes from 50 KHz to 65 KHz
when the control voltage increases from 0.5 V to 1 V. What is the conversion gain, K?
Problem 6.3: If the conversion gain of a certain VCO is 20 KHz/V, how much
frequency deviation does a change in control voltage from 0.8 V to 0.5 V produce? If
the VCO frequency is 250 KHz at 0.8 V, what is the frequency at 0.5 V?
Problem 6.4: A PLL is locked onto an incoming signal with peak amplitude of 250
mV and a frequency of 10 MHz at a phase angle of 30 o. The 400 mV peak VCO signal
is at a phase angle of 15 o.
a. What is the VCO frequency?
b. What is the value of the control voltage being fed back to the VCO at this point?
Problem 6.5:
a. Draw a basic block diagram for the PLL.
b. When the PLL is locked, derive the control voltage being fed back to the VCO
at this point.
c. Name two conditions for a PLL to acquire lock.
Problem 6.6: For the PLL shown in figure, determine the free running frequency, the
lock range, and the capture range.