SCI

Synchronize Communication Interface

RS-232
in S12

Freescale MCU/DSP

Asynchronies Serial Communication

SCI
BUAD RATE:
1 Bit / Sec = 1 Buad (Bit Per Second, BPS)
standard rate(very wide bound wades ):
110, 300, 600, 1200, 2400, 4800, 9600, 19200,38400115200

data format:
b0------------b7

Start Bit
1
Data Bits 5, 6, 7, 8
Parity Bit Even Odd or None
Stop Bit 1, 1.5, 2(at least)

Asynchronies Serial Communication

Use Not Return to Zero (NRZ) code
T & R is synchronized by start bit detection
R Clock = T Clock x 16 (baud rate x 16), slow
3,5,7 clock detect fowling edge of start bit
8,9,10 detect bits value
(Anti-Noise )
The maximum speed: bus rate /16
Duplex and Half Duplex

Asynchronies Serial Communication

and RS232C

Signals Voltage Levers

1= -3V ~ - 15V
0 = +3V ~ + 15V (150 feet)

Signals definitions
DTE
3
2
5
7
8
6
9
4

/ DCE
TxD
RxD
GND
RTS
CTS
DSR
DCD
DTR

out
in
out
in
in
in
out

(9 pins D type Connectors)

TxD
RxD
GND
RTS
CTS
DSR
DCD
DTR

Transmit Data
Receive Data
Require To Send
Clear To Send
Data Set Ready
Data Care Detected
Data Terminal Ready

Asynchronies Serial Communication

RS232C
Only for ASCII
3 wires connection (25 pins D type Connector)
DTE / DCE
2 TxD
3 RxD
7 GND
4 RTS
5 CTS
6 DSR
8 DCD
20 DTR

out
in
out
in
in
in
out

TxD
RxD
GND
RTS
CTS
DSR
DCD
DTR

(Transmit Data )
(Receive Data)
(Ground)
(Require to Send)
(Clear to Send)
(Data Terminal Ready)
(Data Carry Detected)
(Data Set Ready)

Ready always, or XON/XOFF protocol, ASCII only!

Asynchronies Serial Communication

RS232C
DTE ( 9 pins connector) in PC
1 protection ground
2 RxD in
3 TxD out
5
6
7
8
9
4

GND
DSR
RTS
CTS
DCD
DTR

in
out
in
in
out

RxD (Receive Data)

TxD (Transmit Data )
GND
DSR
RTS
CTS
DCD
DTR

(Ground)
(Data Terminal Ready)
(Require to Send)
(Clear to Send)

(Data Carrier Detected)

(Data Set Ready)

No Handshake, should use XON/XOFF protocol,ASCII only

SCI Based Other Communication Protocol

Modem
20 mA current loop
RS-485
Local Intercommunication Network (LIN)
Similar method to access other Modules like LIN,
SPI, CAN, J1850, Ethernet

ASCII Code (control)

$00
NUL
$08
BS
$10
DLE
$18
CAN

$01
SOH
$09
NT
$11
DC1
$19
EM

$02
STX
$0A
LF
$12
DC2
$1A
SUB

$03
ETX
$0B
VT
$13
DC3
$1B
ESC

$04
EOT
$0C
FF
$14
DC4
$1C
FS

$05
ENQ
$0D
CR
$15
NAK
$1D
GS

$06
ACK
$0E
SO
$16
SYN
$1E
RS

$07
BEL
$0F
SI
$17
ETB
$1F
US

ASCII Code (visible)

x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
2x
! #
3x 0 1 2 3
4x @ A B C
5x P Q R S
6x ` a b c
7x p q r s

$
4
D
T
d
t

% &
5 6 7
E F G
U V W
e
f g
u v w

(
8
H
X
h
x

)
9
I
Y
i
y

*
:
J
Z
j
z

+ , . /
; < = > ?
K L M N O
[
\ ]
^ _
k l m n o
{ | }
~ DEL

S12 SCI Module Registers

SCI0BDH
SCI0BDL

EQU
EQU

$C8
$C9

Baud Rate Register High

Low

SCI0CR1
SCI0CR2

EQU
EQU

$CA
$CB

Control Register1
SCI Control Register 2

SCI0SR1
SCI0SR2

EQU
EQU

$CC
$CD

Status Register 1
Status Register 2(SCISR2

SCI0DRH
SCI0DRL

EQU
EQU

$CE
$CF

Data Register High

SCI Data Register Low

SCI Initialization
Setup communication protocol:

Enable T & R in SCICR2

Write to Baud Rate Register Initial the baud rate,

Set Enable SCI bit in SCIRC1 Register, Use Default:

8bits, stop bits, Parity Check

Diff. Form MCU to MCU

SCI Control Register 1 : SCCR1

$CA

Reset

LOOPS SCISWAI RSRC

LOOPS=0
SCISWAI=0
RSRC =0
M=0
WARE=0
ILT =0
PE = 0
PT = 0

M WARE ILT PE
0
0
0
0

PT
0

Do Not in Self Loop Mode

SCI not stopped in wait mode
Receiver Source not from LOOP mode
8 Bits, not 9 Bits
Wake up Mode IS Idle, Not Address
Idle Counter form Start Bits
No Parity
If Parity, Use Even

Nice to Use Default !

SCI Control Register 2 : SCCR2

$CB

B7

SCTIE

TCIE SCRIE IDLE TE RE RWU SBK

SCTIE=0
TCIE =0
SCRIE=0
IDLE =0
TE = 0
RE = 0
RWU =0
SBK = 0

Transmit Buffer Empty IRQ Disabled

Transmit Complete IRQ Disabled
Receiver Buffer Full IRQ Disabled
Idle Line IRQ Disabled
Transmit Disabled
Receive Disabled
Receiver Is Not in Receiver Wake Up Mode
Transmit Break Bit, Not Break.

Enable SCI0 T & R

LDAA
STAA

# %00001100
SCI0CR2

; Initial SCI
; Enable T & R

OR you can use:

BSET SCI0CR2, # %00001100 ;Enable T&R

Try if it works

SCI Baud Rate Reg. SCIBD

SCIBD is a 16bit Reg. which has 13 Valid bits,
So, Valid data = 1 ~ 213-1 = 1~8191
9600 x 16 = 153600
24M / 153600 = 156.25
$9C = 16 x 9 + 12 = 156
LDAA
STAA

#$9C
SCI0BDL

; Set Baud Rate = 9600,

; $4E for 19200...

Discussion:
0 Not Valid!
Maximum baud Rate = ?

SCI Initialization
Already did in the debug
SCI0INIT LDAA #0C

; Initial SCI

STAA SCI0CR2

; Enable T & R

LDAA

; Set Baud Rate to 9600

#$9C

STAA SCI0BDL

; $4E for 19200...

CLR

; 8bit, No Parity..Not necessary

SCI0CR1

Transmit & Receive with SCI

SCI States Register ($CD)
B7
$CD

TDRE

TC

TDRE=1,
TC
RDRF=1,
IDLE
OR
NF
FE
PE

5
RDRF

4
IDLE

OR

NF

FE

PE

Transmit Data Reg. Empty

Transmit Complete
Receive Data Reg. Full
Line Idle
Over Run Error
Noise Error Flag
Frame Error
Parity Error

Transmit

Read Status

Routine OUTCH sends an

ASCII in B to SCI0

No

If Empty?
Yes

*
OUTCH
CHKSTS

ORG

$2000

LDA
BITA
BEQ
STAB
RTS

#$80
SCI0SR1
CHKSTS
SCI0DRL

Send [B]
; TDRE is at bit7
; SCI0 Status Register
; If bit clear, check again
; Write Transmit Data to

Transmit

Read Status

Routine OUTCH send an

ASCII in B to SCI0

No

If Empty?
Yes

*
OUTCH

ORG

$2000

BRCLR
STAB
RTS

SCI0SR1,#$80,*
SCI0DRL
;Write Transmit Data to

Send [B]

Use Macro in C :
#define get_char() {_asm BRCLR $CC,#$80,*; _asm STAB $CF ; }

OUTCH
*
OUTCH
CHKSTS

*
Or:
*
OUTCH

ORG

$2000

LDA
BITA
BEQ
STAB
RTS

#$80
SCI0SR1
CHKSTS
SCI0DRL

BRCLR
STAB
RTS

SCI0SR1,#$80,*
SCI0DRL
;Write Transmit Data to

; TDRE is at bit7
; SCI0 Status Register
; If bit clear, check again
; Write Transmit Data to

Write Out_char in C
#define
#define

SCI0SR1
SCI0DRL

0xcc;
0xcf;

Put_Char(char a)
{ while ((*SCI0SR1 & 0x80) == 0);
*SCI0DRL = c;
}

That may be a low lever I/O functions for C

INCH
INCH BRCLR SCI0SR1,$20,INCH ;Check if keyboard hit
LDAB SCI0DRL
RTS
#define SCI0SR1 0xcc;
#define SCI0DRL 0xcf;
char get_char();
{ while ((*SCI0SR1 & 0x20) == 0);
return(*SCI0DRL); }
Use Macro:
#define get_char() {_asm BRCLR $CC,#$20,*; _asm LDAB $CF ; }

Problems of Polling in I/O status

It keeps 100% CPU time :
For INCH:
BRCLR SCI0SR1,$20,* ; 4 Cycles
When CPU bus clock = 24M,
CPU run the instruction 6,000,000 times / Sec!

For OUTCH, 9600b/s, ~ 1mS/char

SCI Interrupts
There are 3 Interrupt sources in SCI:
Receive IRQ
Receiver Register Full Interrupt

Transmit IRQ
Transmit Register Empty Interrupt
Next Char can be written

Transmit Completed Interrupt

Drive one wire to three status or Receive

Before Enable IRQ Remember to Initial Vectors !

Because the Monitor, Victors moved !

SCI Control Register 2 : SCCR2

B7
$CB

SCTIETCIE SCRIE IDLE TE RE RWU SBK

SCTIE=1
TCIE =0
SCRIE=1
IDLE =0
TE = 0
RE = 0
RWU =0
SBK = 0

Transmit Buffer Empty IRQ Enabled

Transmit Complete IRQ Disabled
Receiver Buffer Full IRQ Enabled
Idle Line IRQ Disabled
Transmit Disabled
Receive Disabled
Receiver Is Not in Receiver Wake Up Mode
Transmit Break Bit, Not Break.

Enable the SCI Interrupt

Write to SCCR2 Interrupt control Register
to enable the IRQ:
B7
$CB

SCTIETCIE SCRIE IDLE TE RE RWU SBK

Initial the Victors before the enable!

Use CLI to Enable IRQ!

System Interrupt Vector Table 1

System Interrupt Vector Table 2

Debug: Move Vectors to User Area

V38

LDX
$EFD6
PSHX
RTS

*
*
FF8C

FFD6

FFFE

ORG

$FF8C ; Vectors table

FDB
FDB
FDB

V1
V2
V3

V37
V38
V39
.
V56
V57
V58

FDB
FDB
FDB

FDB
FDB
FDB

; PWM Emergency Shutdown

; Port P Interrupt
; MSCAN 4 transmit
.
; SCI 1
; SCI 0
; SPI0
; COP failure reset
; Clock Monitor fail reset
; Reset

SCI Receiver Interrupt Service Routine

SCI0SR1
SCI0DRL

EQU $CC
EQU $CF

; Status Reg.
; Data Reg.

SCI0ISR LDAA
SCI0SR1
; Clear IRQ !!!
LDAB
SCI0DRL
; Get the Char.
Put the char. Somewhere

RTI
ORG
DC.W

$EFD6
SCI0ISR

Stack Structure before IRQ

SP - 10 free byte

SP

SP - 9

free

SP - 8

free

SP - 7

free

SP - 6

free

SP - 5

free

SP - 4

free

SP - 3

free

SP - 2

free

SP - 1

free

SP

Last Valid Data

in the stock

Low Address

Stock Growth

High Address

Stack Structure after IRQ Response

After IRQ
SP=SP-9

Before IRQ
SP

Stack free byte

SP - 9

CCR

SP - 8

SP - 7

SP - 6

XH

SP - 5

XL

SP - 4

YH

SP - 3

YL

SP - 2

PCH

SP - 1

PCL

SP

Last Valid Data

in the stack

Low Address

Stack Growth

High Address

Stock Structure after RTI

SP - 10 free byte

After RTI
SP = SP+9

SP - 9

free

SP - 8

free

SP - 7

free

SP - 6

free

SP - 5

free

SP - 4

free

SP - 3

free

SP - 2

free

SP - 1

free

SP

Last Valid Data

in the stock

Low Address

Stock Growth

High Address

Summery of SCI Receive IRQ

Initial SCI ( Monitor did already for you)
Write Interrupt service Routine
Clear IRQ Flag Clear RDRF by reading SCI status register 1 (SCISR1)
with RDRF set and then reading SCI data register low (SCIDRL).
Get the Character
RTI

Initial INT Victor Table (Users victor Table)

Enable SCI Receive Interrupt
Enable System IRQ in CCR by CLI

Questions: How to Do the

Transmit Interrupt?
Reference book:
Embedded System Building Block
Jean J. Labrosse

How to write device driver?

What is IP?