F:\latest 877a\eeprom-prog01\eeprom_rw01.

asm
;----------------------------------------------------; EEPROM WRITE FIRST AND THEN READ THE WRITTEN ROUTINE
; PROGRAMMAR- SYED TASWAR MAHBUB
; BE CAREFUL REGARDING BANK CHANGING
; CLOCK- 20MHZ
;----------------------------------------------------PROCESSOR
INCLUDE
__CONFIG

PIC16F877A
"P16F877A.INC"
H'3F71'

TITLE : "EEPROM WRITE-READ ROUTINE"

;--------------------------------------------------------------------;POSITION OF THE FOLLOWING GPRS IN MEMORY MAP ARE MENTIONED IN INCLUDE
;FILE CITED ABOBE AND HENCE NOT REQUIRED TO MENTION HERE. BUT GIVEN
;HERE TO SHOW THE POSITIONS IN DIFFERENT DATA BANKS FOR NEW PROGRAMMARS.
;---------------------------------------------------------------------STATUS
EQU
0X03
PORTD
EQU
0X08
INTCON
EQU
0X0B
TRISD
EQU
0X88
;IN BANK1, SO BANK CHANGING REQUIRED
EEDATA
EQU
0X10C ;IN BANK2, SO BANK CHANGING REQUIRED
EEADR
EQU
0X10D ;IN BANK2, SO BANK CHANGING REQUIRED
EECON1
EQU
0X18C ;IN BANK3, SO BANK CHANGING REQUIRED
EECON2
EQU
0X18D ;IN BANK3, SO BANK CHANGING REQUIRED
;----------------------------------------------------------------------ORG
GOTO

0X00
INIT

;RESET VECTOR

;-------------- WRITE SEQUENCE SUBROUTINE -----------------------------WRITE_EE

BANKSEL
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF

WR_COMPL

EECON1
EECON1,7
EECON1,2
0X55
EECON2
0XAA
EECON2

;MOVING TO BANK3
;DISABLE EEPGD BIT TO ACCESS DATA MEMORY
;WREN
;WRITING SEQUENCE
;WRITING SEQUENCE
;WRITING SEQUENCE
;WRITING SEQUENCE

BSF
EECON1,1
BCF
EECON1,2
BANKSEL 0X0000

;ENABLE WR BIT
;DISABLE WREN BIT
;FALLING BACK TO BANK0

BANKSEL
BTFSC
GOTO
BANKSEL
RETURN

;MOVING TO BANK3
;TESTING WR BIT

EECON1
EECON1,1
WR_COMPL
0X0000

;FALLING BACK TO BANK0

;RETURN FROM SUB-ROUTINE WRITE_EE

;------------- READ SEQUENCE SUB-ROUTINE-------------------------------READ_EE

BANKSEL
MOVLW
MOVWF
BANKSEL
BCF
BSF
BANKSEL
MOVF
BANKSEL
RETURN

EEADR
0X00
EEADR
EECON1
EECON1,7
EECON1,0
EEDATA
EEDATA,W
PORTD

;MOVING TO BANK2
;USING 0 BYTE OF EEADR
;MOVING TO BANK3
;DISABLE EEPGD BIT TO ACCESS DATA MEMORY
;ENABLE RD BIT
;MOVING TO BANK2
;FALLING BACK TO BANK0

;--------- MAIN PROGRAM STARTS HERE -------------------------------------INIT

BANKSEL TRISD
CLRF
TRISD

;MOVING TO BANK1
;MAKING PORTB ALL BITS OUTPUT
1

F:\latest 877a\eeprom-prog01\eeprom_rw01.asm
BANKSEL PORTD
CLRF
PORTD

;FALLING BACK TO BANK0

BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
CALL
NOP
CALL
MOVWF

EEADR
0X00
EEADR
0XF1
EEDATA
WRITE_EE

;MOVING TO BANK2

READ_EE
PORTD

;0 BYTE OF EEADR NOW HAVING OXF1 VALUE

;CALLING THE WRITE SEQUENCE
;DOING NOTHING- WASTING 200 NANO SEC
;CALLING READ SEQUENCE
;SENDING EEADR 0 BYTE VALUE TO PORTD

GOTO

CIRCLE

;STAY HERE TILL RESET OR POWER OFF

START

CIRCLE

;USING 0 BYTE OF EEADR

;-------------------------------------------------------------------------------------------END
;--------------------------------------------------------------------------------------------