ENGR-43 Lec-07c Sp12 Sequenial-Logic FlipFlops

Engineering 43
Sequential
(FlipFlop) Logic
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx
But First WhiteBoard Work

For the Truth Table
Shown at right
Construct the Karnaugh
Map
Write The Minimized
Function Q(A,B,C,D)
Draw the Logic Circuit
Notice 1s in Rows
1, 5, 9, 13, 14, 15
Need only put 1s in these
locations; other cells
Assumed to be Zero
2
Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bruce Mayer, PE
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
Blank Map (NonStretching)

AB\CD 00
01
11
00
01
11
10
00
ABCD
ABCD
ABCD
ABCD
01
ABCD
ABCD
ABCD
ABCD
11
11
ABCD
ABCD
ABCD
ABCD
10
10
ABCD
ABCD
ABCD
ABCD
00
01

3
10 AB\CD
Bruce Mayer, PE
Stretchable Blank Map

4
Bruce Mayer, PE
More WhiteBoard Work

Implement This Function using ONLY
NAND Gates
F AC D A B C D A B
An Example of NAND-Gate Synthesis
NANDS are easier to construct than
ANDs, ORs, NORs
NANDs are the preferred gate for logic circuits
5
Bruce Mayer, PE
Memory Filled Logic

The Invert/AND/OR Combinatorial
Logic Circuits depended ONLY on the
Current Inputs; previous states did Not
affect the Current State
Combinatorial Logic is MEMORYLESS
In SEQUENTIAL Logic the Circuit

Output CAN Depend on the Previous
condition of the Circuit
Sequential Logic has MEMORY
6
Bruce Mayer, PE
Sequential Circuit
A sequential circuit
consists of a
feedback path,
and employs
some memory
elements
Combination
al outputs
Combination
al logic
Memory
outputs
Memory
elements
External
inputs
[Sequential circuit] = [Combinational

logic] + [Memory Elements]
7
Bruce Mayer, PE
Synchronous vs Asynchronous
Almost all Logic Chips Include a Clock
The Clock helps to Synchronize the
Operation of the Circuits.
The Clock is simply a very regular Hi/Lo
Pulse train
Logic Forms are divided into two groups:
SYNCHRONUS Depend on Clock
Asynchronous NO Clock-Dependency
8
Bruce Mayer, PE
Asynchronous S-R FlipFlop

Cross-coupled NOR gates
R
R
S
Q
Q'
Similar to inverter pair, with capability to

force Q to 0 (reset=1) or 1 (set=1)
0
R
S
Q'

9
n-1
Q
Q'
n-1
1
Bruce Mayer, PE
??
??
Q
Q'
NAND based SR FlipFlop

Cross-coupled NAND gates
S'
R'
S'
R'
Q'
Similar to inverter pair, with capability to

force Q to 0 (reset=0) or 1 (set=0)
NOR notes
Any HI input LO output
Any HI LO
All LO inputs HI output

All LO HI
10
NAND notes
Any LO input HI output
Any LO HI
All HI inputs LO output

All HI LO
Bruce Mayer, PE
State Behavior of SR FlipFlop

Transition Table
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Qn-1
0
1
0
1
0
1
0
1
Qn
0 hold
1 reset
0
0 set
1 not allowed
1
X
X
characteristic equation
Qn = S + RQn-1
R
Q'
REset
SET
Sequential (output depends on history

when inputs R=0, S=0) but asynchronous
11
Bruce Mayer, PE
SR FlipFlop Timing Behavior

R
Any HI input LO output

Any HI LO
All LO inputs HI output

Q'
S
Reset
Hold
Set
All LO HI
Reset
Set
Race
100
R
S
Q
Q
Races Produce UnPredictable OutPuts

12
Bruce Mayer, PE
Clocked SR FlipFlop
Control times when
R and S
inputs matter
Otherwise, the slightest glitch on R or S while
enable is low could cause change in value stored
Ensure R & S stable before utilized (to avoid
transient R=1, S=1)

13
Bruce Mayer, PE
Clocked SR FlipFlops
NOR-NOR
Implementation
Truth
Table
R
0
0
1
1
x
S En R S
Qn
0 0 1 1 NotAllowed
1 0 1 0 Reset to 0
0 0 0 1
Set to 1
1 x 0 0
Qn1
x 1 0 0
Qn1
x Dont Care
For NOR: any-HiLO; ALL-LOHi

14
Bruce Mayer, PE
Clocked SR FlipFlops
NAND-NOR
Implementation
Truth
Table
R
0
0
1
1
x
S C
Qn
0 x
Qn1
1 1
Set to 1
0 1 Reset to 0
1 1 NotAllowed
x 0
Qn1
x Dont Care

15
Circuit Symbol
Bruce Mayer, PE
SR FlipFlop Clock-Overide
Sometimes Need to Set or Reset the
FlipFlop withOUT Regard to the Clock
Note the position of Pr & Cl on the

3rd-Stage ORs (any HiHi)
Ensures Pr & Cl OverRide R, S, & C
16
Bruce Mayer, PE
Edge Triggered D FlipFlop

sensitive to
inputs only
near edge of
clock signal
(not while
steady )
holds D' when

clock goes low
0
R
Clk=1
Q
S
0

17
holds D when
clock goes low
Bruce Mayer, PE
Edge-Triggered FlipFlop Flavors

POSITIVE edge-triggered
Inputs sampled on RISING edge; outputs change
after RISING edge
NEGATIVE edge-triggered flip-flops

Inputs sampled on falling edge; outputs change
after falling edge
100
D
CLK
Qpos
Qpos'
Qneg
Qneg'
18
positive edge-triggered FF
negative edge-triggered FF
Bruce Mayer, PE
Edge Triggered D FlipFlop

4-NAND,
1-NOT
implementation
Truth Table for
All Postive-Going
Edge D-FFs
NAND:
any LO Hi
All HI LO
19
CLK
0
1
D Qn
x Qn1
x Qn1
0 0
1 1
Bruce Mayer, PE
Edge Triggered JK FlipFlop

A Toggling Flip Flop
Under A certain Control-Set: Q Q
Notice that Q does NOT go HI-for-sure or
LO-for-sure, and it does NOT remain STEADY
A NAND Nest:
Circuit Symbol

20
Bruce Mayer, PE
JK FlipFlop Toggle TruthTable

The Simplified Ckt
ReCall NAND
Any LO Hi
ALL Hi LO
Note that the

outputs feed back to
the enabling NAND
gates. This is what
gives the toggling
action when J=K=1
21
C
0
1
J
x
x
0
0
1
1
K
x
x
0
1
0
1
Qn
Qn1
Qn1
Qn1
0
1
Qn1
Notes
No Chg
No Chg
No Chg
Reset to 0
Set to 1
TOGGLE
Bruce Mayer, PE
Cascading FF Shift Register

Serial-in/Parallel-out Shift register
New value goes into first stage
While previous value of 1st stg goes into 2nd stg
The QN can be SAMPLED any time
IN
D Q
Q0
D Q
Q1
OUT
CLK

22
Bruce Mayer, PE
Example: Eliminate Inconsistency

Want to Send Async
SAME
Input
Input Value
to
TWO Places
Clocked
Synchronous
System
D Q
Synchronizer
Q0
Async
Input D Q
Clock
Clock
D Q
Q1
Q0
Q1
Clock
is asynchronous and
fans out to D0 and D1
one FF catches the
signal, one does not
inconsistent state may
be reached!
CLK
23
Q1
D Q
Clock
In
Q0
D Q
Bruce Mayer, PE
FlipFlops Summarized
Development of D-FF
Level-sensitive used in custom integrated
circuits
can be made with 4 pairs of gates
Usually follows multiphase non-overlapping
clock discipline
Edge-triggered used in programmable logic

devices
Good choice for data storage register

24
Bruce Mayer, PE
Historically J-K FF was popular but now
never used
Similar to R-S but with 1-1 being used to
toggle output (complement state)
Same Operation Can always be
implemented using D FlipFlops
Preset and Clear inputs are highly

desirable on flip-flops
Used at start-up or to reset system to a
known state
25
Bruce Mayer, PE
Reset (set state to 0) R
Synchronous: Dnew = R' Dold
Transition only when next clock edge arrives
Asynchronous: doesn't wait for clock,

quick but dangerous
Preset or Set (set state to 1) S

Synchronous: Dnew = Dold + S
Transition only when next clock edge arrives)
Asynchronous: doesn't wait for clock

quick but dangerous
26
Bruce Mayer, PE
WhiteBoard Work
Use Gates and a DFF to Implement the
JK-FF operation
C
0
1

27
J
x
x
0
0
1
1
K
x
x
0
1
0
1
Qn
Qn1
Qn1
Qn1
0
1
Qn1
Notes
No Chg
No Chg
No Chg
Reset to 0
Set to 1
TOGGLE
Bruce Mayer, PE
All Done for Today
IEEE
91-1984
Gates

28
Bruce Mayer, PE
Engineering 43
Appendix
Logic Syn
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
29
Bruce Mayer, PE
Row
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1

30
Bruce Mayer, PE

31
Bruce Mayer, PE
NAND Gate Synthesis

With the expression in SOP form
1. After any need inversions; In the first logic
level there are as many logic gates as
terms in the SOP expression
2. Each gate corresponds to a SINGLE
Term, and has, as inputs, the variables in
that term
3. The outputs of the First Logic-Level are
ALL inputs to a SINGLE (multi-input if
needed) NAND gate
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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

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Bruce Mayer, PE

ENGR-43 Lec-07c Sp12 Sequenial-Logic FlipFlops

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Engineering 43

But First WhiteBoard Work

Blank Map (NonStretching)

Engineering-43: Engineering Circuit Analysis

Stretchable Blank Map

Engineering-43: Engineering Circuit Analysis

More WhiteBoard Work

Memory Filled Logic

In SEQUENTIAL Logic the Circuit

[Sequential circuit] = [Combinational

Asynchronous S-R FlipFlop

Similar to inverter pair, with capability to

Engineering-43: Engineering Circuit Analysis

NAND based SR FlipFlop

Similar to inverter pair, with capability to

All LO inputs HI output

All HI inputs LO output

State Behavior of SR FlipFlop

Sequential (output depends on history

SR FlipFlop Timing Behavior

Any HI input LO output

All LO inputs HI output

Races Produce UnPredictable OutPuts

Engineering-43: Engineering Circuit Analysis

For NOR: any-HiLO; ALL-LOHi

Engineering-43: Engineering Circuit Analysis

Note the position of Pr & Cl on the

Edge Triggered D FlipFlop

holds D' when

Engineering-43: Engineering Circuit Analysis

Edge-Triggered FlipFlop Flavors

NEGATIVE edge-triggered flip-flops

Edge Triggered D FlipFlop

Edge Triggered JK FlipFlop

Engineering-43: Engineering Circuit Analysis

JK FlipFlop Toggle TruthTable

Note that the

Cascading FF Shift Register

Engineering-43: Engineering Circuit Analysis

Example: Eliminate Inconsistency

Edge-triggered used in programmable logic

Engineering-43: Engineering Circuit Analysis

Preset and Clear inputs are highly

Asynchronous: doesn't wait for clock,

Preset or Set (set state to 1) S

Asynchronous: doesn't wait for clock

Engineering-43: Engineering Circuit Analysis

All Done for Today

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

NAND Gate Synthesis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

Engineering-43: Engineering Circuit Analysis

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