Compal La-9631p r1.0 Schematics

A
Compal Confidential
2
Gx00/Gx00 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
AMD Mars XT / SUN Pro
2013-02-27
3
LA-9631P
REV:1.0
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/15
2012/07/11
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
1.0
LA-9631P
Date:
Wednesday, February 27, 2013
Sheet
E
of
60
Compal confidential
Project Name : VIWGP (14") / VIWGR (15")
Chief River
1
VRAM 512MB/1GB/2GB
MARS XT : DDR3 x 8
SUN PRO : DDR3 x 4
Intel
Processor
Ivy Bridge
PEG 8x
Gen2 / Gen3
AMD MARS XT M2 128 bits

/ SUN PRO M2 64 bits
Page 23~32
Memory Bus
Dual Channel
204pin DDRIII-SO-DIMM X2
Page 12, 13
BANK 0, 1, 2
DDR3
1600MHz
DDR3
1333MHz
DDR3
1066MHz
rPGA989
37.5mm x 37.5mm
Page 5~11
FDI *8
2.7GT/s
DMI2 *4
5GT/s
LVDS Conn.
Page 33
USB30 x2
HDMI Conn.
USB20 x6
Page 35
CRT Conn.
Page 34
LAN
RJ45 Conn.
Page 38
Left USB3.0 x2
PCIe Port 0
Atheros
AR8162/QCA8172(10/100)
PCIe x1
Page 37
Intel
PCH
Panther Point
SATA Gen3
Int. Camera
USB30 Port 0,1

Page 45
USB20 Port 9
Page 45
USB20 Port 3
Page 33
Touch Screen
Card Reader
USB20 Port 2
Page 45
USB20 Port 11 page 28
PCIe Port 1
Page 40
ODD Conn.
SATA
SATA Port 2
PCIe Mini Card

WLAN
Realtek RTS5170
HDD Conn.
SATA Port 0
FCBGA 989Balls
25mm x 25mm
Right USB2.0
Page 40
3
PCIe x1
Page 36
Audio Codec
CONEXANT
CX20757
AZALIA
Page 41
Page 14~22
Int. MIC Conn.
Int. Speaker Conn.
Audio Combo Jacks
Page 41
Page 41
Page 41
Sub-borad
SPI ROM
15"
14"
Power/B
HP & MIC
EC
2MB + 4MB
ENE KB9012
Page 14
Page 42
(LID)
LS9631
4
USB/B
Thermal Sensor
ODD/B
LS9632
Page 39
Touch Pad
Page 43
Int. KBD
Page 43
LS9634
IO/B
2011/06/15
Issued Date
(LED, LID)
LS9633
Compal Secret Data
Switch/B
(Card Reader)
2012/07/11
Deciphered Date
Title
Custom
LS9635
Date:
MB Block Diagram
Rev
1.0
LA-9631P
Sheet
E
of
60
BOARD ID Table
Voltage Rails
+5VS
+3VS
power
plane
+1.5VS
+V1.05S_VCCP
+5VALW
+1.5V
+VCC_CORE
+B
+VGA_CORE
+3VALW
+VCC_GFXCORE_AXG
+1.8VS
State
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
SIGNAL
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
STATE
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Full ON
Clock
+0.75VS
+1.05VS
Vcc
R694
Board ID
S0
S3
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
0
1
2
3
3.3V
Board ID / SKU ID Table for AD channel
100K +/- 1%
VAD_BID min
0 V
0.347V
0.423V
0.541V
R695
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
V AD_BID typ
0 V
0.354V
0.430V
0.550V
VAD_BID max
0 V
0.360V
0.438V
0.559V
EC AD
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
MP
PVT
DVT
EVT
S5 S4/AC
USB Port Table
UHCI0
UHCI1
EHCI1
UHCI2
EC SM Bus1 address
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011x
Thermal Sensor
0100 1100
PCH SM Bus address
UHCI3
UHCI4
AMD-GPU SM Bus address
EHCI2
UHCI5
UHCI6
Device
Address
Device
DDR_JDIMM1
1010 000x A0h
Internal thermal sensor 0100 0001 41h
DDR_JDIMM2
1010 010x A4h
BOM Structure Table
USB 2.0 Port
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3 External
USB Port
USB Port (Left Side)USB3.0
USB Port (Left Side)USB3.0
Touch Screen
Camera
USB Port (Right Side USB-BD)

Mini Card(WLAN)
Card Reader
SMBUS Control Table

SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
4
PCH_SMBCLK
KB9012
+3VALW
KB9012
+3VS
PCH
PCH_SMBDATA +3VALW
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
SML1CLK
PCH
SML1DATA
+3VALW
VGA
BATT
KB9012
SODIMM WLAN
+3VS
+3VGS
+3VGS
+3VALW
+3VS
Thermal
Sensor
X
V
PCH
X
V
+3VS
+3VALW
+3VS
+3VS
Item
BOM Structure
VIWGP (14")
14@
VIWGR (15")
15@
HDMI Logo
45@
LAN 10/100
8162@
LAN 10/100
8172@
LAN Switch mode
SWR@
LAN LDO Mode
LDO@
LAN Gas tube
GAS@
Camera
CMOS@
HDMI
HDMI@
PCH is HM76
HM76@
PCH is HM70
HM70@
PCH is NM70
NM70@
VGA is Mars XT
Mars@
VGA is Sun Pro
Sun@
For VGA
PX@
For VRAM and Strap
X76@
For UMA Strap
UMA@
Microphone
MIC@
Touch Screen
TS@
Connector
ME@
Board ID for EVT
EVT@
Board ID for DVT
DVT@
Board ID for PVT
PVT@
For USB2.0 (All PCH)
USB2@
For USB3.0 (HM76,HM70) USB3@
For share ROM
SROM@
For non-share ROM
NOSROM@
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
Size
B
Date:
Notes List
Document Number
Rev
1.0
LA-9631P
Sheet
E
of
60
Power-Up/Down Sequence
Mars XT VRAM STRAP
X76@
X76@
Vendor
UV5, UV6, UV7, UV8

UV9, UV10, UV11, UV12
R_pu
R_pd
RV20
RV27
ID
PS_3[ 3 ]
PS_3[ 2 ]
PS_3[ 1 ]
NC
ZZZ5 SA000067500
2GBytes MM2G@ 128Mx16 MT41J128M16JT-093G:K 1
8.45K
2K
Samsung 2048Mbits
ZZZ4 SA000068U00
2GBytes MS2G@ 128Mx16 K4W2G1646E-BC1A
4.75K
Micron 2048Mbits
ZZZ6
2GBytes MH2G@
Hynix 2048Mbits
SA000065300
128M16 H5TQ2G63DFR-N0C
4.53K
2K
ZZZ7
1GBytes MS1G@
Samsung 1028Mbits
SA00004GS00
64Mx16 K4W1G1646G-BC11
6.98K
4.99K
4.53K
4.99K
4.75K
NC
2GBytes
Hynix 2048Mbits
ZZZ15 SA00006H400
MH2GN@ 128Mx16 H5TC2G63FFR-11C
"Mars" has the following requirements with regards to power-supply

sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/s.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
VDDR3(3.3VGS)
PCIE_VDDC(0.95VGSV)
Hynix 1024Mbits
ZZZ8 SA000041SB0
1GBytes MH1G@ 64Mx16 H5TQ1G63EFR-11C
ZZZ4
ZZZ5
VDDR1(1.5VGS)
ZZZ6
ZZZ15
ZZZ7
ZZZ8
VDDC/VDDCI(1.12V)
Samsung_2G
MS2G@
X7646738L01
Micron_2G
MM2G@
X7646738L02
Hynix_2G
Hynix_2G
MH2G@
X7646738L09
Samsung_1G
MS1G@
X7646738L03
MH2GN@
X7646738L10
Hynix_1G
MH1G@
X7646738L04
VDD_CT(1.8V)
PERSTb
Sun PRO VRAM STRAP
REFCLK
X76@
X76@
Vendor
UV9, UV10, UV11, UV12
R_pu
R_pd
RV20
RV27
Straps Reset
4.75K
Straps Valid
2K
Global ASIC Reset
ID
PS_3[ 3 ]
PS_3[ 2 ]
PS_3[ 1 ]
NC
8.45K
ZZZ9
2GBytes SS2G@
Samsung 4096Mbits
SA000068R00
256Mx16 K4W4G1646B-HC11
ZZZ10
2GBytes SM2G@
Micron 4096Mbits
SA000065D00
1
256Mx16/1866 MT41K256M16HA-107G:E
ZZZ11
2GBytes SH2G@
Hynix 4096Mbits
SA00006DG00
256MX16 H5TQ4G63MFR-11C
4.53K
2K
ZZZ12
1GBytes SS1G@
Samsung 2048Mbits
SA000068U00
128Mx16 K4W2G1646E-BC1A
6.98K
4.99K
Hynix 2048Mbits
ZZZ16 SA00006H400
SH1GN@ 128Mx16 H5TC2G63FFR-11C
4.53K
4.99K
ZZZ13
1GBytes SM1G@
Micron 2048Mbits
SA000067500
128Mx16 MT41J128M16JT-093G:K
3.4K
10K
ZZZ14
1GBytes SH1G@
Hynix 2048Mbits
SA000065300
128M16 H5TQ2G63DFR-N0C
4.75K
1GBytes
ZZZ9
ZZZ10
ZZZ11
ZZZ12
ZZZ13
ZZZ14
Micron_1G
Hynix_1G
T4+16clock
NC
ZZZ16
Samsung_2G
SS2G@
X7646738L05
Micron_2G
SM2G@
X7646738L06
Hynix_2G
SH2G@
X7646738L11
Samsung_1G
SS1G@
X7646738L07
SM1G@
X7646738L08
SH1G@
X7647538L01
Hynix_1G
SH1GN@
X7646738L13
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title
VGA Notes List
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
of
60
ZZZ1
14@
ZZZ2
14"_DIS_PCB_LA9631P
15"_DIS_PCB_LA9631P
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
+V1.05S_VCCP
DA6000WO100
PCB 0N2 LA-9631P REV0 M/B DIS 5
R1
24.9_0402_1%
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
<16>
<16>
<16>
<16>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<16>
<16>
<16>
<16>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
<16> FDI_FSYNC0
<16> FDI_FSYNC1
J18
J17
<16> FDI_INT
H20
<16> FDI_LSYNC0
<16> FDI_LSYNC1
J19
H17
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
R7
24.9_0402_1%
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
eDP_HPD
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP
EDP_COMP
eDP_COMPIO and ICOMPO signals

should be shorted near balls
and routed with typical
impedance <25 mohms
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PCI EXPRESS* - GRAPHICS
<16>
<16>
<16>
<16>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI
B27
B25
A25
B24
+V1.05S_VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
Intel(R) FDI
<16>
<16>
<16>
<16>
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_COMP
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane #

socket pin map definition
CFG2
*
PCIE_CRX_GTX_N[0..7]
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
JCPU1A
15@
DA6000WO000
PCB 0N1 LA-9631P REV0 M/B DIS 3
definition matches
0:Lane Reversed
<23>
PCIE_CRX_GTX_P[0..7]
C9
C10
C11
C12
C13
C14
C15
C16
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
<23>
PCIE_CTX_GRX_N[0..7]
0.22U_0402_10V6K PCIE_CTX_GRX_N7
<23>
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0
C25
C26
C27
C28
C29
C30
C31
C32
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
PCIE_CTX_GRX_P[0..15]
0.22U_0402_10V6K PCIE_CTX_GRX_P7
<23>
TYCO_2013620-2_IVY BRIDGE
ME@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title

PROCESSOR(1/7) DMI,FDI,PEG
Custom
Rev
1.0
LA-9631P
Date:
Sheet

1
of
60
JCPU1B
D
PROC_SELECT#
SKTOCC#
+V1.05S_VCCP
AL33
H_CATERR#
R9
62_0402_5%
AN33
<42> H_PECI
R15
56_0402_5%
1
2
H_PROCHOT#
<42,46,47,54> H_PROCHOT#
AL32
H_PROCHOT#_R
AN32
<19> H_THRMTRIP#
CATERR#
THERMAL
T48
PECI
PROCHOT#
THERMTRIP#
BCLK
BCLK#
CLOCKS
AN34
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
A28
A27
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
A16
A15
2
2
R12
R13
1 1K_0402_5%
1 1K_0402_5%
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP0 2 R16
SM_RCOMP1 2 R17
SM_RCOMP2 2 R18
+V1.05S_VCCP
H_DRAMRST# <7>
+V1.05S_VCCP
DDR3
MISC
C26
<19> H_SNB_IVB#
MISC
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
DDR3 Compensation Signals

RP13
TCK
TMS
TRST#
2
2
SM_DRAMPWROK
BUF_CPU_RST#
AR33
RESET#
ESD
TDI
TDO
XDP_TCK
XDP_TMS
XDP_TRST#
AR28
AP26
XDP_TDI
XDP_TDO
1
2
3
4
AR26
AR27
AP30
8
7
6
5
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
51_0804_8P4R_5%
C46
100P_0402_50V8J
ESD
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AL35 XDP_DBRESET#
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
R28
1 1K_0402_5%
+3VS
V8
C549
22P_0402_50V8J
R29
1
2 PM_DRAM_PWRGD_R
130_0402_5%
R27
10K_0402_5%
UNCOREPWRGOOD
XDP_PRDY#
XDP_PREQ#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
AP33
<19> H_CPUPWRGD
PM_SYNC
JTAG & BPM
AM34
<16> H_PM_SYNC
PWR MANAGEMENT
AP29
AP27
PRDY#
PREQ#
C45
47P_0402_50V8J
ESD
+3VALW
ME@
Buffered reset to CPU

+1.5V_CPU_VDDQ
+3VS
B
R30
200_0402_5%
+V1.05S_VCCP
1
PM_SYS_PWRGD_BUF
R32
75_0402_5%
R34
43_0402_1%
1
2
U2
74AHC1G09GW_TSSOP5
BUF_CPU_RST#
BUFO_CPU_RST# 4
NC
Y
A
1
2
3V
PCH_PLTRST#
PCH_PLTRST# <18>
SN74LVC1G07DCKR_SC70-5
O
A
+3VS
<16> PM_DRAM_PWRGD
U1
1 R161
2
10K_0402_5%
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PROCESSOR(2/7) PM,XDP,CLK
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
of
60
JCPU1C
JCPU1D
<13> DDR_B_D[0..63]
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
V6
<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2
AE8
AD9
AF9
<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
AB6
AA6
V9
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
AA5
AB5
V10
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
AH3
AG3
AG2
AH2
M_ODT0 <12>
M_ODT1 <12>
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS#[0..7] <12>
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS[0..7] <12>
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA[0..15] <12>
<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2
<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#
ME@
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
DDR SYSTEM MEMORY B
<12> DDR_A_D[0..63]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
AD2
R9
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
AE1
AD1
R10
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
AE4
AD4
AD5
AE5
M_ODT2 <13>
M_ODT3 <13>
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS#[0..7] <13>
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS[0..7] <13>
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA[0..15] <13>
ME@
+1.5V
H_DRAMRST#
<6> H_DRAMRST#
R38
1K_0402_5%
2
DDR3_DRAMRST# <12,13>
Q2
LBSS138LT1G_SOT-23-3
R39
4.99K_0402_1%
DDR3_DRAMRST#_R
R37
1K_0402_5%
<10,15> DRAMRST_CNTRL_PCH
@
1 R48
2
0_0402_5%
DRAMRST_CNTRL_PCH_R
Compal Secret Data
C35
0.047U 16V K X7R 0402
Eiffel used 0.01u

Module design used 0.047u
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
Custom
Rev
1.0
LA-9631P
Date:

PROCESSOR(3/7) DDRIII
Sheet
1
of
60
CFG Straps for Processor
CFG2
R41
1K_0402_1%
PX@
Interl request AH26 short GND

check on EVT phase
RSVD33
RSVD34
RSVD35
2 100_0402_1%
R88 1
2 100_0402_1%
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ31
AH31
AJ33
AH33
AJ26
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
@
R257
49.9_0402_1%
@
R255
49.9_0402_1%
VSS_VAL_SENSE
J20
B18
J15
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
L7
AG7
AE7
AK2
definition matches
0:Lane Reversed
CFG4
W8
R42
1K_0402_1%
AT26
AM33
AJ27
T8
J16
H16
G16
CFG4
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
RSVD5
VSS_AXG_VAL_SENSE
1: Normal Operation; Lane #

socket pin map definition
CFG2
RSVD24
RSVD25
RSVD27
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
AR35
AT34
AT33
AP35
AR34
CFG6
CFG5
1
T13
Display Port Presence Strap

RSVD37
RSVD38
RSVD39
RSVD40
RESERVED
R82 1
PAD
@
R252
49.9_0402_1%
RSVD32
@
R253
49.9_0402_1%
+VCC_CORE
RSVD28
RSVD29
RSVD30
RSVD31
AH27
AH26
PX@
R43
1K_0402_1%
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
@ R44
1K_0402_1%
AJ32
AK32
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
AM35
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AT2
AT1
AR1
B1
CFG7
1
KEY
B34
A33
A34
B35
C35
+VCC_GFXCORE_AXG
VCC_DIE_SENSE
VSS_DIE_SENSE
CFG4
CFG5
CFG6
CFG7
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG
CFG2
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
PEG Static Lane Reversal - CFG2 is for the 16x
JCPU1E
@R45
@
R45
1K_0402_1%
2
ME@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PROCESSOR(4/7) RSVD,CFG
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
of
60
JCPU1F
POWER
+V1.05S_VCCP
+VCC_CORE
8.5A
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
+V1.05S_VCCP
R46
75_0402_5%
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
R50
1 R47
2 43_0402_5%
1 130_0402_5%
VR_SVID_CLK series-resistors close to VR

VR_SVID_ALRT# <54>
VR_SVID_CLK <54>
VR_SVID_DAT <54>
+V1.05S_VCCP
0.1uF on power side

B
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
+VCC_CORE
Trace Impedance =27-33 ohm

Trace Length Matc < 25 mils
2
AJ35
AJ34
VCCSENSE <54>
VSSSENSE <54>
1
VCC_SENSE
VSS_SENSE
R51
100_0402_1%
VCCIO_SENSE
VSS_SENSE_VCCIO
B10
A10
VSSIO_SENSE_L
R74 & R79 put together

VSSIO_SENSE_L <52>
R54
100_0402_1%
VCCIO_SENSE <52>
1
R74 2VSSIO_SENSE
10_0402_1%
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO40
SVID
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
SENSE LINES
CORE SUPPLY
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
PEG AND DDR
QC=94A
DC=53A
+V1.05S_VCCP
R79
2
1
10_0402_1%
VSS_SENCE 100ohm +-1% pull-down to GND near processor

Compal Secret Data
Issued Date
2011/06/15
ME@
Deciphered Date
2012/07/11
Title
PROCESSOR(5/7) PWR,BYPASS
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
of
60
+1.5V_CPU_VDDQ
+1.5V
D
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
Q6
2
G
<15,7>
+V_DDR_REFA_R
+V_DDR_REFB_R
DRAMRST_CNTRL_PCH 2
G
Q9
2
G
R57
330K_0402_5%
@
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1
+VCC_GFXCORE_AXG
C97
0.047U_0603_25V7K
R616
10_0402_1%
Q4
2N7002H_SOT23-3
R885 R02
1
2
15K_0402_1%
1
3
RUN_ON_CPU1.5VS3
D
R56
82K_0402_5%
AP4800
Id=9.6A
U3
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
B+
DRAMRST_CNTRL_PCH
<45> SUSP
1
2
SENSE
LINES
1
C98
.1U_0402_16V7K
+V_DDR_REFA_R
+V_DDR_REFB_R
R78
1K_0402_1%
2
2
VREF
B4
D1
DDR3 -1.5V RAILS
+1.5V_CPU_VDDQ
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
1
1
C123
220U_6.3V_M
+VCCSA
SA RAIL
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
MISC
VCCPLL1
VCCPLL2
VCCPLL3
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
C122
10U_0603_6.3V6M
B6
A6
A2
C120
10U_0603_6.3V6M
C132
1U_0402_6.3V6K
C130
10U_0603_6.3V6M
C345
22U_0805_6.3V6M
+1.8VS_VCCPLL
+V_SM_VREF_CNT
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
M27 +VCCSA
M26
L26
J26
J25
J24
H26
H25
+ C128 @
330U_D2_2.5VY_R9M
H23
C22
C24
C126
10U_0603_6.3V6M
1.5A
0_0805_5%
2
AL1
R67
1K_0402_1%
+V_SM_VREF should
have 20 mil trace width
C125
10U_0603_6.3V6M
R69
1
+1.5V_CPU_VDDQ
VSS_AXG_SENSE <54>
R626
10_0402_1%
C124
10U_0603_6.3V6M
+1.8VS
AK35
AK34
C119
10U_0603_6.3V6M
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
GRAPHICS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCC_AXG_SENSE <54>
C117
10U_0603_6.3V6M
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
POWER
1.8V RAIL
+VCC_GFXCORE_AXG JCPU1G
+VCCSA_SENSE <51>
H_VCCSA_VID0
H_VCCSA_VID1
<51>
<51>
A19
ME@
IVY Bridge drives VCCIO_SEL low

VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
PROCESSOR(6/7) PWR
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
10
of
60
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
JCPU1I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
ME@
CompalME@
Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

PROCESSOR(7/7) VSS
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
11
of
60
+VREF_DQ_DIMMA
+1.5V
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A
<7> DDR_A_DQS[0..7]
JDIMM1
C133
.1U_0402_16V7K
C134
2.2U_0603_6.3V4Z
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
<7> DDR_CKE0_DIMMA
DDR_A_BS2
<7> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<7> M_CLK_DDR0
<7> M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
<7> DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
<7> DDR_CS1_DIMMA#
DDR_A_MA13
DDR_CS1_DIMMA#
205
G1
G2
RP16
DDR_A_DM2
+VREF_CA
DDR_A_D22
DDR_A_D23
+VREF_CB
DDR_A_D28
DDR_A_D29
8
7
6
5
1K_0804_8P4R_1%
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
<7>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_CS0_DIMMA#
M_ODT0 <7>
(10uF_0603_6.3V)*8
Layout Note:
Place near DIMM
(0.1uF_402_10V)*4
<7>
M_ODT1 <7>
+VREF_CA
+1.5V
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
2
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
1
+
C149 @
220U_6.3V_M
DDR_A_DQS#5
DDR_A_DQS5
VDDQ(1.5V) =
DDR_A_D46
DDR_A_D47
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_A_D52
DDR_A_D53
6*0603 10uf (PER CONNECTOR)
DDR_A_DM6
Layout Note:
Place near DIMM
VTT(0.75V) =
DDR_A_D54
DDR_A_D55
3*0805 10uf
7/28 Update connect GND directly
4*0402 1uf
+0.75VS
VREF =
DDR_A_D60
DDR_A_D61
1*0402 0.1uf
DDR_A_DQS#7
DDR_A_DQS7
1*0402 0.1uf
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 2.2uf
Layout Note:
Place near DIMM
SMB_DATA_S3 <13,15,36>
SMB_CLK_S3 <13,15,36>
+0.75VS
0.65A@0.75V
206
LCN_DAN06-K4806-0103
ME@
Compal Secret Data
Issued Date
1
2
3
4
C148
.1U_0402_16V7K
C156
.1U_0402_16V7K
+3VS
C155
2.2U_0603_6.3V4Z
+1.5V
DDR_A_D20
DDR_A_D21
C152
1U_0402_6.3V6K
DDR_A_D58
DDR_A_D59
1K_0804_8P4R_1%
C150
1U_0402_6.3V6K
DDR_A_DM7
<13,7>
DDR_A_D14
DDR_A_D15
C147
.1U_0402_16V7K
DDR_A_D56
DDR_A_D57
+VREF_DQ_DIMMB
DDR3_DRAMRST#
1
2
3
4
C146
.1U_0402_16V7K
DDR_A_D50
DDR_A_D51
+VREF_DQ_DIMMA
DDR_A_DM1
DDR3_DRAMRST#
8
7
6
5
C145
.1U_0402_16V7K
DDR_A_DQS#6
DDR_A_DQS6
RP15
DDR_A_D12
DDR_A_D13
C144
10U_0603_6.3V6M
DDR_A_D48
DDR_A_D49
+1.5V
DDR_A_D6
DDR_A_D7
C143
10U_0603_6.3V6M
DDR_A_D42
DDR_A_D43
<7> DDR_A_MA[0..15]
DDR_A_DQS#0
DDR_A_DQS0
C142
10U_0603_6.3V6M
DDR_A_DM5
DDR_A_D4
DDR_A_D5
C141
10U_0603_6.3V6M
DDR_A_D40
DDR_A_D41
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
<7> DDR_A_DQS#[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C140
10U_0603_6.3V6M
DDR_A_D34
DDR_A_D35
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C139
10U_0603_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C136
2.2U_0603_6.3V4Z
DDR_A_DQS#4
DDR_A_DQS4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C135
.1U_0402_16V7K
DDR_A_D32
DDR_A_D33
+1.5V
3A@1.5V
+VREF_DQ_DIMMA
2011/06/15
Deciphered Date
2012/07/11
4
Title

DDRIII-SODIMM SLOT1

Custom
Date:
Rev
1.0
LA-9631P

1
Sheet
12
of
60
+VREF_DQ_DIMMB
3A@1.5V
+1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
DDR_B_D0
DDR_B_D1
DDR_B_DM0
C157
.1U_0402_16V7K
1
C158
2.2U_0603_6.3V4Z
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
For Arranale only +VREF_DQ_DIMMB

supply from a external 1.5V voltage divide
circuit.
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
<7> DDR_CKE2_DIMMB
DDR_B_BS2
<7> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<7> M_CLK_DDR2
<7> M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
<7> DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_WE#
<7> DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
<7> DDR_CS3_DIMMB#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_CS2_DIMMB#
M_ODT2 <7>
(10uF_0603_6.3V)*8
Layout Note:
Place near DIMM
DDR_B_BS1 <7>
DDR_B_RAS# <7>
(0.1uF_402_10V)*4
<7>
M_ODT3 <7>
+VREF_CB
+1.5V
+VREF_CB
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
0.65A@0.75V
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
Layout Note:
Place near DIMM
VTT(0.75V) =
3*0805 10uf
4*0402 1uf
+0.75VS
1*0402 0.1uf
VDDSPD (3.3V)=
1*0402 0.1uf
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
1*0402 2.2uf
1*0402 2.2uf
SMB_DATA_S3 <12,15,36>
SMB_CLK_S3 <12,15,36>
+0.75VS
Layout Note:
Place near DIMM
206
TYCO_2-2013287-1
ME@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
C172
.1U_0402_16V7K
DDR_B_D36
DDR_B_D37
C171
.1U_0402_16V7K
G2
DDR_B_MA15
DDR_B_MA14
C170
.1U_0402_16V7K
G1
DDR_CKE3_DIMMB
C169
.1U_0402_16V7K
205
DDR_B_D30
DDR_B_D31
C168
+3VS
2
10K_0402_5%
DDR_B_DQS#3
DDR_B_DQS3
10U_0603_6.3V6M
1
R97
DDR_B_D28
DDR_B_D29
C167
C178
.1U_0402_16V7K
+3VS
C177
2.2U_0603_6.3V4Z
DDR_B_D22
DDR_B_D23
C176
1U_0402_6.3V6K
DDR_B_D58
DDR_B_D59
<7>
DDR_B_DM2
C174
1U_0402_6.3V6K
DDR_B_DM7
DDR_CKE3_DIMMB
DDR_B_D20
DDR_B_D21
10U_0603_6.3V6M
DDR_B_D56
DDR_B_D57
<12,7>
C166
DDR_B_D50
DDR_B_D51
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
10U_0603_6.3V6M
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DM1
DDR3_DRAMRST#
C165
DDR_B_D48
DDR_B_D49
DDR_B_D12
DDR_B_D13
10U_0603_6.3V6M
DDR_B_D42
DDR_B_D43
DDR_B_D6
DDR_B_D7
C164
DDR_B_DM5
<7> DDR_B_MA[0..15]
DDR_B_DQS#0
DDR_B_DQS0
10U_0603_6.3V6M
DDR_B_D40
DDR_B_D41
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
<7> DDR_B_DQS#[0..7]
DDR_B_D4
DDR_B_D5
10U_0603_6.3V6M
DDR_B_D34
DDR_B_D35
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C163
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C160
2.2U_0603_6.3V4Z
DDR_B_DQS#4
DDR_B_DQS4
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C159
.1U_0402_16V7K
DDR_B_D32
DDR_B_D33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
<7> DDR_B_D[0..63]
+1.5V
+VREF_DQ_DIMMB
Title

DDRIII-SODIMM SLOT2
Size
Document Number
Rev
1.0
LA-9631P
Date:

1
Sheet
13
of
60
PCH_RTCX1
W=20mils
+RTCBATT
PCH_RTCX2
@
R104
0_0402_5%
C179
1U_0603_10V4Z
Y1
1
2
32.768KHZ_12.5PF_CM31532768DZFT
C180
18P_0402_50V8J
CMOS setting
Shunt
Clear CMOS
Open
Keep CMOS
TPM setting
CLRP3
R99
1K_0402_5%
1
2
2
10M_0402_5%
R98
W=20mils
+RTCVCC
CLRP2
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
C181
18P_0402_50V8J
D
U4A
*
C
2 1K_0402_5%
HDA_SPKR
HIGH= Enable ( No Reboot )

LOW= Disable (Default)
<41> HDA_SPKR
+3V_PCH
@ 1 1K_0402_5%
G22
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
HDA_BIT_CLK
N34
HDA_SYNC
L34
HDA_SPKR
T10
HDA_RST#
K34
C34
Low = Disabled (Default)

High = Enabled [Flash Descriptor Security Overide]
R108
A34
1 1K_0402_5%
A36
ME_FLASH
<42> ME_FLASH
+3V_PCH
E34
G34
ME_FLASH
HDA_SYNC
This signal has a weak internal pull-down

On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
PCH_GPIO33
C36
PCH_GPIO13
N32
PCH_JTAG_TCK
J3
PCH_JTAG_TMS
H7
PCH_JTAG_TDI
K5
PCH_JTAG_TDO
H1
+5VS
RP12
<41> HDA_RST_AUDIO#
HDA_SYNC_R
HDA_RST#
1
2
3
4
Q10
1
HDA_SYNC
SPI_CLK_PCH_R
8
7
6
5
<41> HDA_SYNC_AUDIO
SPI_SB_CS0#
R878
1M_0402_5%
33_0804_8P4R_5%
FWH4 / LFRAME#
SRTCRST#
INTRUDER#
INTVRMEN
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
HDA_SDIN2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SDO
HDA_DOCK_EN# / GPIO33
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
HDA_DOCK_RST# / GPIO13
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TMS
SATAICOMPO
JTAG_TDI
JTAG_TDO
SATAICOMPI
SATA3COMPI
T3
Y14
T1
ME_FLASH
<41> HDA_SDOUT_AUDIO
RTCRST#
SATA3RCOMPO
HDA_BIT_CLK
For EMI
<41> HDA_BITCLK_AUDIO
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
PCH_SRTCRST#
HDA_SDIN0
<41> HDA_SDIN0
R106 2
D20
RTCX2
check with vender
SPI_SI
V4
SPI_SO_R
U3
Del Q10 check with codec

VDDIO using 3VALW
SPI_CLK
SATA3RBIAS
C38
A38
B37
C37
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
D36
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SPI_CS1#
SPI_MOSI
SPI_MISO
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
<42>
<42>
<42>
<42>
EC and Mini card debug port
LPC_FRAME# <42>
E36
K36
V5
SERIRQ
AM3
AM1
AP7
AP5
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SERIRQ <42>
SATA_DTX_C_IRX_N0 <40>
SATA_DTX_C_IRX_P0 <40>
SATA_ITX_C_DRX_N0 <40>
SATA_ITX_C_DRX_P0 <40>
HDD
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
SATA_DTX_C_IRX_N2 <40>
SATA_DTX_C_IRX_P2 <40>
SATA_ITX_C_DRX_N2 <40>
SATA_ITX_C_DRX_P2 <40>
ODD
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
SATA_COMP
R111
37.4_0402_1%
1
2
SATA3_COMP
R113
49.9_0402_1%
1
2
AB12
AB13
AH1
P3
SATALED#
V14
PCH_GPIO21
P1
BBS_BIT0_R
+V1.05S_VCCP
+V1.05S_VCCP
2
R115
750_0402_1%
RBIAS_SATA3
SPI_CS0#
SPI
R105 1
PCH_RTCRST#
RTCX1
SATA 6G
+3VS
C20
SATA
PCH_RTCX2
RTC
C182
1U_0603_10V4Z
(INTVRMEN should always be pull high.)
A20
IHDA
H
Integrated VRM enable
L
Integrated VRM disable
PCH_RTCX1
JTAG
INTVRMEN
CLRP3
SHORT PADS
C183
1U_0603_10V4Z
1
2
R103 20K_0402_5%
1
2
R100 20K_0402_5%
PCH_INTVRMEN
SM_INTRUDER#
2 330K_0402_5%
2 1M_0402_5%
R102 1
+RTCVCC
R101 1
CLRP2
SHORT PADS
+RTCVCC
Share ROM
@
RP2
SPI_SO_R
SPI_SI
SPI_CLK_PCH_R
SPI_SB_CS0#
PANTHER-POINT_FCBGA989
HM76@
SA00005FH70
S IC BD82HM76 SLJ8E C1 BGA 989P PCH C38!
1
2
3
4
SPI_CLK_PCH_R
U4
EC_SPI_SO
EC_SPI_SI
EC_SPI_CLK
EC_SPI_CS#
EC_SPI_SO <42>
EC_SPI_SI <42>
EC_SPI_CLK <42>
EC_SPI_CS# <42>
0_0804_8P4R_5%
+3V_ROM
HM70@
8
7
6
5
Share ROM
R124
33_0402_5%
@
SA00005MQ80
IC BD82HM70 SJTNV C1 BGA 989P PCH C38!
DPDG1.1
For EMI
C190
22P_0402_50V8J
@
U4
R127 1
2 SPI_WP#
3.3K_0402_5%
R129 1
2 SPI_HOLD#
3.3K_0402_5%
NM70@
+3V_ROM
U5
SPI_SB_CS0#
1 R131
2 SPI_SO_L
SPI_SO_R
SPI_WP#
0_0402_5%
@
+3VS
For EMI
RP17
R124;c190 close to U4.T3 pin

A
SA00005WU60
S IC BD82NM70 SLJTA C1 BGA 989P PCH C38!
<19> PCH_GPIO16
BBS_BIT0_R
SATALED#
PCH_GPIO16
SERIRQ
8
7
6
5
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
SPI_HOLD#
SPI_CLK_1
1 R133
2 SPI_CLK_PCH_R
0_0402_5% SPI_SI
@
W25Q64FVSSIQ_SO8
For EMI
SA000039A30
S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
1
2
3
4
10K_0804_8P4R_5%
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom
Rev
1.0
LA-9631P
Date:
Wednesday, March 06, 2013
Sheet
1
14
of
60
U4B
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
LAN
C
R153 1
R154 1
<37> CLK_PCIE_LAN#
<37> CLK_PCIE_LAN
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
For EMI
<37> CLKREQ_LAN#
+3V_PCH
WLAN
@
@
R152
R156 1
R165 1
<36> CLK_PCIE_WLAN1#
<36> CLK_PCIE_WLAN1
J2
1 10K_0402_5%
@
@
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_WLAN1#_R AB49
CLK_PCIE_WLAN1_R AB47
For EMI
<36> CLKREQ_WLAN#
+3VS
R158 2
Y40
Y39
M1
1 10K_0402_5%
AA48
AA47
PCH_GPIO20
V10
Y37
Y36
PCH_GPIO25
A8
Y43
Y45
PCH_GPIO26
L12
V45
V46
PCH_GPIO44
L14
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
A12
SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58
SML1DATA / GPIO75
DRAMRST_CNTRL_PCH
C8
PCH_SML0CLK
G12
PCH_SML0DATA
DRAMRST_CNTRL_PCH <10,7>
2 R139
1
1K_0402_5%
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CL_RST1#
SMB_DATA_S3 <12,13,36>
+3V_PCH
Q61A
2N7002DW-T/R7_SOT363-6
6
1
EC_SMB_CK2
+3V_PCH
EC_SMB_CK2 <24,39,42>
C13
E14
SML1CLK
M16
SML1DATA
VGA
EC
Thermal Sensor
+3VS
EC_SMB_DA2
EC_SMB_DA2 <24,39,42>
2N7002DW-T/R7_SOT363-6
Q61B
M7
+3V_PCH
T11
P10
R143
10K_0402_5%
R544
2.2K_0402_5%
CLK_REQ_VGA# <24>
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
SMB_DATA_S3
+3V_PCH
CL_DATA1
PEG_A_CLKRQ# / GPIO47
PCIECLKRQ0# / GPIO73
1 10K_0402_5%
2N7002DW-T/R7_SOT363-6
Q60B
CL_CLK1
DIMM1
DIMM2
Mini Card
+3VS
PCH_HOT# 2 R140
PERN4
PERP4
PETN4
PETP4
PERN6
PERP6
PETN6
PETP6
PCH_SMBDATA
3
PERN3
PERP3
PETN3
PETP3
PERN5
PERP5
PETN5
PETP5
C9
SMB_CLK_S3 <12,13,36>
+3V_PCH
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
M10
PCH_SML0CLK
1 R145
2 10K_0402_5%
@
AB37
AB38
CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
R168 1
R172 1
SMBDATA
1 10K_0402_5%
BG36
BJ36
AV34
AU34
PERN2
PERP2
PETN2
PETP2
PCH_SMBCLK
@
@
R545
2.2K_0402_5%
BE34
BF34
BB32
AY32
PCH_GPI011
H14
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
2 R134
E12
2 .1U_0402_16V7K
2 .1U_0402_16V7K
SMBCLK
1
1
SMBALERT# / GPIO11
C194
C195
PERN1
PERP1
PETN1
PETP1
BG34
BJ34
AV32
AU32
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
SMBUS
2 .1U_0402_16V7K
2 .1U_0402_16V7K
Link
1
1
Controller
<36> PCIE_PRX_DTX_N2
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
<36> PCIE_PTX_C_DRX_P2
C192
C193
CLOCKS
WLAN
PCI-E*
LAN
Q60A
2N7002DW-T/R7_SOT363-6
6
1 SMB_CLK_S3
PCH_SML0DATA
2 0_0402_5%
2 0_0402_5%
For EMI
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
+3V_PCH
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
+3VS
RP23
8
7
6
5
SML1DATA
EC_SMB_DA2
SML1CLK
EC_SMB_CK2
AM12
AM13
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R155 1
R157 1
2
2
10K_0402_5%
10K_0402_5%
BJ30
BG30
CLKIN_DMI2#
CLKIN_DMI2
R159 1
R160 1
2
2
10K_0402_5%
10K_0402_5%
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R162 1
R163 1
2
2
10K_0402_5%
10K_0402_5%
AK7
AK5
CLK_BUF_PCIE_SATA# R164 1
CLK_BUF_PCIE_SATA R166 1
2
2
10K_0402_5%
10K_0402_5%
K45
CLK_BUF_ICH_14M
R167 1
10K_0402_5%
H45
CLK_PCI_LPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
XCLK_RCOMP
1
2
3
4
2.2K_0804_8P4R_5%
+3V_PCH
+3VS
RP24
8
7
6
5
PCH_SMBCLK
SMB_CLK_S3
PCH_SMBDATA
SMB_DATA_S3
1
2
3
4
2.2K_0804_8P4R_5%
CLKIN_SATA_N
CLKIN_SATA_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
CLK_PCI_LPBACK <18>
PCH_GPIO56
E6
V40
V42
PCH_GPIO45
T13
V38
V37
PCH_GPIO46
K12
AK14
PCIE_CLK_8N AK13
PCIE_CLK_8P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP
R171
90.9_0402_1%
1
2
+V1.05S_VCCP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
XTAL25_IN
CLKOUT_PCIE7N
CLKOUT_PCIE7P
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
K43
1
2
R169 1M_0402_5%
F47
H47
27M_SSC
FLEX CLOCKS
AB42
AB40
CLKOUTFLEX0 / GPIO64
K49
XTAL25_OUT
PCH_GPIO67
PCH_GPIO67 <19>
BIOS Request SKU ID
C196
12P_0402_50V8J
OSC
NC
NC
OSC
4
1
Y2
1 25MHZ_10PF_7V25000014
C197
12P_0402_50V8J
HM76@
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (2/9) PCIE, SMBUS, CLK
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
15
of
60
+RTCVCC
DSWODVREN
R179
R183
1 330K_0402_5%
@
1 330K_0402_5%
U4C
Y
B
SYS_PWROK
@
R180
10K_0402_5%
+3VS
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<5>
<5>
<5>
<5>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
<5>
<5>
<5>
<5>
BC24
BE20
BG18
BG20
DMI
PCH_PWROK
<42,54> VGATE
@
U15
MC74VHC1G08DFT2G SC70 5P
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI_INT
+V1.05S_VCCP
1
R177
1
R178
BJ24
2
DMI_IRCOMP
49.9_0402_1%
2
RBIAS_CPY
750_0402_1%
BG25
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
4mil width and place

within 500mil of the PCH
<19> SYS_RST#
<42> SYS_PWROK
SYS_RST#
SYS_PWROK
DSWVRMEN
C12
K3
P12
L22
<42> PCH_PWROK
<6> PM_DRAM_PWRGD
PCH_PWROK
L10
PM_DRAM_PWRGD
B13
C21
<42> EC_RSMRST#
System Power Management
SUSACK# is only used on platform

that support the Deep Sx state.
FDI_LSYNC1
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
+3V_PCH
SUSWARN#
2
R192 1 300_0402_5%
R194
1 10K_0402_5%
SUSWARN#
R197
1 10K_0402_5%
EC_RSMRST#
K16
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A18
DSWODVREN
E22
EC_RSMRST#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
DSWODVREN - On Die DSW VR Enable

HEnable
LDisable
FDI_INT <5>
FDI_FSYNC0
<5>
FDI_FSYNC1
<5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
B9
PCIE_WAKE# <36>
N3
PM_CLKRUN#
G8
SUS_STAT#
N14
R299 10K_0402_5%
1
SUSCLK <42>
D10
PM_SLP_S5# <42>
H4
PM_SLP_S4# <42>
F4
PM_SLP_S3# <42>
PM_DRAM_PWRGD
E20
<42> PBTN_OUT#
<24,42,46,48> ACIN
D29 1
AC_PRESENT_R
H20
PWRBTN#
SLP_A#
ACPRESENT / GPIO31
SLP_SUS#
G10
Can be left NC when IAMT is not support on the platfrom
G16
CH751H-40PT_SOD323-2
PCH_GPIO72
RI#
E10
A10
BATLOW# / GPIO72
PMSYNCH
RI#
SLP_LAN# / GPIO29
AP14
K14
H_PM_SYNC
H_PM_SYNC <6>
Can be left NC if no use integrated LAN.
HM76@
+3V_PCH
R309
2 200K_0402_5%
AC_PRESENT_R
+3V_PCH
RP25
A
8
7
6
5
1
2
3
4
PCIE_WAKE#
RI#
EC_SMI#
EC_SMI# <19,42>
10K_0804_8P4R_5%
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (3/9) DMI,FDI,PM,
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
16
of
60
ENBKL
J47
M45
<42> ENBKL
<33> PCH_ENVDD
100K_0402_1%
P45
<33> PCH_PWM
<33> EDID_CLK
<33> EDID_DATA
+3VS
2 R206
2.37K_0402_1%
RP14
1
2
3
4
EDID_DATA
EDID_CLK
CTRL_DATA
CTRL_CLK
2.2K_0804_8P4R_5%
EDID_CLK
EDID_DATA
T40
K47
CTRL_CLK
CTRL_DATA
T45
P39
LVDS_IBG
AF37
AF36
LVD_VREF
AE48
AE47
AK39
AK40
<33> LVDS_ACLK#
<33> LVDS_ACLK
<33> LVDS_A0#
<33> LVDS_A1#
<33> LVDS_A2#
AN48
AM47
AK47
AJ48
<33> LVDS_A0
<33> LVDS_A1
<33> LVDS_A2
AN47
AM49
AK49
AJ47
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
RP20
1
2
3
4
AF40
AF39
DAC_BLU
DAC_GRN
DAC_RED
AH45
AH47
AF49
AF45
150_0804_8P4R_1%
Max = 800 mils
AH43
AH49
AF47
AF43
DAC_BLU
<34> DAC_BLU
<34> CRT_DDC_CLK
<34> CRT_DDC_DATA
CRT_DDC_CLK
CRT_DDC_DATA
R524
2.2K_0402_5%
CRT_IREF T43
T42
R211
1K_0402_1%
R559
2.2K_0402_5%
T39
M40
M47
M49
<34> CRT_HSYNC
<34> CRT_VSYNC
N48
P49
T49
DAC_RED
<34> DAC_RED
+3VS
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DAC_GRN
<34> DAC_GRN
LVDSB_CLK#
LVDSB_CLK
AM42
AM40
AP39
AP40
CRT_DDC_CLK
CRT_DDC_DATA
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
P38 HDMICLK_NB
M39 HDMIDAT_NB
AT49
AT47
AT40
HDMICLK_NB <35>
HDMIDAT_NB <35>
TMDS_B_HPD# <35>
AV42 TMDS_B_DATA2#_PCHHDMI@
AV40 TMDS_B_DATA2_PCH HDMI@
AV45 TMDS_B_DATA1#_PCHHDMI@
AV46 TMDS_B_DATA1_PCH HDMI@
AU48 TMDS_B_DATA0#_PCHHDMI@
AU47 TMDS_B_DATA0_PCH HDMI@
AV47 TMDS_B_CLK#_PCH HDMI@
AV49 TMDS_B_CLK_PCH
HDMI@
P46
P42
C200
C201
C202
C203
C204
C205
C206
C207
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_CLK-_CK <35>
HDMI_CLK+_CK <35>
HDMI D2
HDMI
HDMI D1
HDMI D0
HDMI CLK
CAP move on Conn, side
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_GREEN
CRT_RED
CRT
8
7
6
5
AP43
AP45
L_CTRL_CLK
L_CTRL_DATA
Digital Display Interface
LVDS
8
7
6
5
U4D
R438
D
HM76@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
B
Date:
PCH (4/9) LVDS,CRT,DP,HDMI

Document Number
Rev
1.0
LA-9631P
Sheet
1
17
of
60
PCH_GPIO2
DGPU_PWR_EN
PCH_GPIO4
PCH_GPIO3
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
8.2K_1206_10P8R_5%
D
+3VS
RP7
8
7
6
5
1
2
3
4
DGPU_HOLD_RST#
PCH_WL_OFF#
PCH_GPIO5
PCH_GPIO52
8.2K_0804_8P4R_5%
Pull-up resistors are not required

on these signals
R292
2 8.2K_0402_5%
PCH_GPIO51
R557
2 8.2K_0402_5%
PCH_GPIO53
B21
M20
AY16
BG46
USB3_RX1_N BE28
USB3_RX2_N BC30
USB3_RX3_N BE32
USB3_RX4_N BJ32
USB3_RX1_P BC28
USB3_RX2_P BE30
USB3_RX3_P BF32
USB3_RX4_P BG32
USB3_TX1_N AV26
USB3_TX2_N BB26
USB3_TX3_N AU28
USB3_TX4_N AY30
USB3_TX1_P AU26
USB3_TX2_P AY26
USB3_TX3_P AV28
USB3_TX4_P AW30
<44> USB3_RX1_N
<44> USB3_RX2_N
C
Boot BIOS Strap bit1 BBS1

<44> USB3_RX1_P
<44> USB3_RX2_P
Boot BIOS
Bit11 Bit10 Destination
GNT1#/
GPIO51
Reserved
Reserved
<44> USB3_TX1_N
<44> USB3_TX2_N
<44> USB3_TX1_P
<44> USB3_TX2_P
(Default)
SPI
LPC
<23> DGPU_HOLD_RST#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PCH_GPIO52
C46
C44
E40
PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#
D47
E42
F46
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
<25,42,51,53> DGPU_PWR_EN
B
<36> PCH_WL_OFF#
GPIO55
PCH_WL_OFF#
R215
U4E
2 1K_0402_5%
PCI_PME#
A16 swap overide Strap/Top-Block

Swap Override jumper
PCH_PLTRST#
<6> PCH_PLTRST#
Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default
22_0402_5% 1
22_0402_5% 1
<15> CLK_PCI_LPBACK
<42> CLK_PCI_EC
2 R219
2 R220
For EMI
K10
C6
CLK_PCI_LPBACK_R H49
H43
CLK_PCI_EC_R
J48
CLK_PCI_DB_R
K42
H40
RSVD1
RSVD2
RSVD3
RSVD4
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
TP21
TP22
TP23
TP24
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
RSVD28
RSVD29
AY7
AV7
AU3
BG4
AT10
BC8
D
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
USB Debug Port = Port1 and Port9
PIRQA#
PIRQB#
PIRQC#
PIRQD#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
USB
10
9
8
7
6
RSVD
+3VS
PCI
RP1
1
2
3
4
5
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
+3VS
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS#
USBRBIAS
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
C33
USBRBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N9 <44>
USB20_P9 <44>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <43>
USB20_P11 <43>
B33
PME#
Touch Screen
USB Camera
RIGHT USB
WLAN
B
CARD READER
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0# <44>
USB_OC4# <44>
For RIGHT USB2.0 Port
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
+3V_PCH
+3V_PCH
RP18
1
2
3
4
5
10
9
8
7
6
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
A
10K_1206_10P8R_5%
R222
1
2
0_0402_5%
PCH_PLTRST#
Compal Secret Data
Issued Date
R223
100K_0402_5%
2011/06/15
Deciphered Date
2012/07/11
Title
PCH (5/9) PCI, USB
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
(USB 3.0)
For LEFT USB3.0 Port
PLTRST#
HM76@
C208 @
1U_0402_6.3V6K
LEFT USB
1
R218 2
22.6_0402_1%
<23,36,37,42> PLT_RST#
LEFT USB
Within 500 mils
<44>
<44>
<44>
<44>
<44>
<44>
<33>
<33>
Rev
1.0
LA-9631P
Date:
Sheet
1
18
of
60
HM70
HM76
HM76@
HM70@
R707
R707
10K_0402_5%
2
Mars@
R704
Function
PCH_GPIO71
2
HM76@
R705
HM70@
R703
10K_0402_5%
1
0
PCH_GPIO71
Mars XT
Sun Pro
Reserved
NM70@
R703
PCH_GPIO70
+3VS
R706
200K_0402_5%
Sun@
NM70@
R702
PCH_GPIO69
NM70
Function
10K_0402_5%
PCH_GPIO70
+3VS
10K_0402_5%
PCH_GPIO69
+3VS
10K_0402_5%
10K_0402_5%
10K_0402_5%
U4F
PCH_GPIO6
H36
EC_SCI#
E38
EC_SMI#
C10
GPIO28
On-Die PLL Voltage Regulator

This signal has a weak internal pull up
<42> EC_SCI#
HOn-Die voltage regulator enable

LOn-Die PLL Voltage Regulator disable
R240
<16,42> EC_SMI#
2 1K_0402_5% PCH_GPIO28
+3V_PCH
R230 2 1K_0402_5%
PCH_GPIO12
C4
EC_LID_OUT#
G2
PCH_GPIO16
U2
BMBUSY# / GPIO0
TACH4 / GPIO68
TACH1 / GPIO1
TACH5 / GPIO69
TACH2 / GPIO6
TACH6 / GPIO70
TACH3 / GPIO7
TACH7 / GPIO71
<14> PCH_GPIO16
GPIO15
A20GATE
2 10K_0402_5%
<36> PCH_BT_ON#
PCH_GPIO27
<40> ODD_EN
+3V_PCH
PCH_BT_ON#
T5
ODD_EN
E8
PCH_GPIO27
E16
PCH_GPIO28
P8
R241
GPIO36, 37
When Unused as GPIO or SATA*GP
+3VS
Use 8.2K-10K pull-down
to ground.
2 10K_0402_5%
1 R242
+3VS
2 10K_0402_5%
<36> INTEL_BT_OFF#
+3VS
R250 @
10K_0402_5%
R244 @
10K_0402_5%
PCH_GPIO36
PCH_GPIO37
R881
10K_0402_5%
R547 @
10K_0402_5%
SATA4GP / GPIO16
INTEL_BT_OFF#
K1
PCH_GPIO35
K4
PCH_GPIO36
V8
PCH_GPIO37
M5
PCH_GPIO38
N2
PCH_GPIO39
M3
PCH_GPIO48
V13
PCH_GPIO49
V3
PCH_GPIO57
D6
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
PROCPW RGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
STP_PCI# / GPIO34
TS_VSS2
GPIO35
TS_VSS3
SATA2GP / GPIO36
TS_VSS4
SLOAD / GPIO38
NC_1
A45
A46
+3VS
BIOS Request SKU ID
A5
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
GPIO57
VSS_NCTF_17
RP10
+3VS
8
7
6
5
1
2
3
4
A6
PCH_GPIO39
SYS_RST#
PCH_BT_ON#
PCH_GPIO35
SYS_RST# <16>
B3
1
2
R246
UMA@
10K_0804_8P4R_5%
10K_0402_5%
R711
UMA@
10K_0402_5%
B47
BD1
BD49
BE1
BE49
PCH_GPIO38
BF1
PCH_GPIO67 <15>
BF49
10K_0402_5%
1
R298
PX@
R708
PX@
A
10K_0402_5%
PCH_GPIO67
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
+3VS
GATEA20 <42>
P5
KBRST#
AY10
KBRST#
KBRST# <42>
AY11
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
R226
2 10K_0402_5%
H_CPUPWRGD <6>
PCH_THRMTRIP#_R 1
R239
2
H_THRMTRIP#
390_0402_5%
H_THRMTRIP# <6>
T14
AY1
INIT3_3V
AH8
This signal has weak internal PU,can't pull low

+1.8VS
AK11
AH10
DMI Termination Voltage
AK10
NV_CLE
P37
Set to Vcc when HIGH

Set to Vss when LOW
2
1
R217
VSS_NCTF_15
NCTF
A44
P4
NV_CLE
SDATAOUT1 / GPIO48
VSS_NCTF_18
+3VS
AU16
SDATAOUT0 / GPIO39
A4
PCH_GPIO71
SATA3GP / GPIO37
PECI
CPU/MISC
PU on power side
R245
D40
PCH_GPIO70
A40
R236
10K_0402_5%
GPIO
<53> DGPU_PWROK
PCH_GPIO69
C41
LAN_PHY_PW R_CTRL / GPIO12
RCIN#
PCH_GPIO27 (Have internal Pull-High)

High: VCCVRM VR Enable
Low: VCCVRM VR Disable
PCH_GPIO68
B41
GPIO8
<42> EC_LID_OUT#
C40
BG2
Weak internal
PU,Do not pull low
BG48
A42
R216
2.2K_0402_5%
PCH_GPIO1
T7
PCH_GPIO0
H_SNB_IVB# <6>
1K_0402_5%
CLOSE TO THE BRANCHING POINT
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
PCH_GPIO38
PCH_GPIO67
Function
HM76@
SG(Optimus / PX)
Reserved
DIS
UMA
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (6/9) GPIO, CPU, MISC
Size
Document Number
Custom
Date:
Rev
1.0
LA-9631P
Sheet
19
of
60
AN19
+VCCAPLLEXP
This pin can be left as no connect in

On-Die VR enabled mode (default).
BJ22
AN16
AN17
AN21
AN26
AN27
+V1.05S_VCCP
AP21
Near AN16
AP23
C225
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C221
10U_0603_6.3V6M
AP24
AP26
AT24
AN33
AN34
+3VS
BH29
1
C227
.1U_0402_16V7K
This pin can be left as no connect in

On-Die VR enabled mode (default).
+V1.05S_VCCP
AP16
+1.05VS_VCCAPLL_FDI
BG6
AP17
+V1.05S_VCCP
AU20
CRT
VSSADAC
L1
2
+VCCADAC
1
U47
2
1mA VCCALVDS
LVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
60mA VCCTX_LVDS[3]
VCCTX_LVDS[4]
1
C213
0.01U_0402_16V7K
1
C214
.1U_0402_16V7K
PCH Power Rail Table

Refer to CPU EDS R1.5
+3VS
1_0603_1%
1
1
C215
10U_0603_6.3V6M
Voltage Rail
C395@
10U_0603_6.3V6M
V_PROC_IO
AK36
V5REF
AM38
AP36
AP37
+VCCTX_LVDS
1
V5REF_Sus
+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
AM37
VCCAPLLEXP
VCCIO[15]
VCCIO[16]
VCCIO[17]
C216
0.01U_0402_16V7K
1.05
0.001
0.001
C217
0.01U_0402_16V7K
0.001
Vcc3_3
3.3
0.228
VccADAC
3.3
0.001
VccADPLLA
1.05
0.075
VccADPLLB
1.05
0.075
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
3.709
C218
22U_0805_6.3V6M
+3VS
V33
1
VCC3_3[7]
V34
2
C219
.1U_0402_16V7K
+1.5VS
VCCIO[18]
VCCIO[19]
S0 Iccmax
Current (A)
0.1uH inductor, 200mA
Near V33
VCC3_3[6]
Voltage
AK37
VCCIO[28]
3711mA
VCCVRM[3]
AT16
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCDMI[1]
AT20
Near AB36
20mA VCCCLKDMI
+V1.05S_VCCP
AB36
1
C226
1U_0402_6.3V6K
VccASW
1.05
0.903
VccSPI
3.3
0.01
+V1.05S_VCCP
Near AT20
VCCIO[20]
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
6 uA
3.3
0.065
C220
1U_0402_6.3V6K
VCCIO[25]
VCCIO[26]
VCCDFTERM[1]
190mAVCCDFTERM[2]
VCC3_3[3]
+1.5VS
VCCADAC
U48
+3VS
HVCMOS
+V1.05S_VCCP
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
1mA
DMI
L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
1300mA
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
FDI
C212
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C209
10U_0603_6.3V6M
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
DFT / SPI
Near AA23
POWER
U4G
VCC CORE
+V1.05S_VCCP
VCCIO
VCCDFTERM[3]
VCCDFTERM[4]
AG16
VccSus3_3
VccSusHDA
3.3 / 1.5
0.01
VccVRM
1.8 / 1.5
0.167
Near AG16
+3V_ROM
AJ16
1
AJ17
C228
.1U_0402_16V7K
VccCLKDMI
1.05
0.075
VccSSC
1.05
0.095
20mA VCCSPI
V1
Near V1
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
HM76@
Share ROM
+1.8VS
AG17
C230
1U_0402_6.3V6K
Share ROM
+3VALW
+3VS
+3V_ROM
@
1 R413
2
0_0402_5%
@
Q21
AO3413_SOT23
@
R419
+5VALW
Q22
2
G
2N7002H_SOT23-3
@
@
R40
1
2
0_0402_5%
C237
.1U_0402_16V7K
Compal Secret Data
Issued Date
0_0402_5%
PCH_PWR_EN_R
1
C252
.1U_0402_16V7K
<42> PCH_PWR_EN
@
R418
100K_0402_5%
C243
.1U_0402_16V7K
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (7/9) PWR
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
20
of
60
Have internal VRM

+3VS
+V1.05S_VCCP
R268 @
0_0603_5%
2
1
+VCCACLK
Near T38
C235 @
.1U_0402_16V7K
T38
+3VS
DCPSUSBYP
VCCIO[32]
VCCIO[33]
BH23
AL24
+VCCSUS1
1
@ C239
1U_0402_6.3V6K
AA19
AA21
AA24
C242
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
AA26
AA27
AA29
AA31
AC26
C246
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
+V1.05S_VCCP
C244
1U_0402_6.3V6K
AC27
AC29
AC31
AD29
AD31
W21
W23
L6
1
2
10UH_LB2012T100MR_20%
1
W24
C253
1U_0402_6.3V6K
C187
22U_0805_6.3V6M
C250
220U_6.3V_M
C251
1U_0402_6.3V6K
+1.05VS_VCCA_A_DPL
VCCSUS3_3[8]
VCCIO[14]
DCPSUS[3]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
Near AA19
1
VCCAPLLDMI2
W26
W29
W31
W33
VCCASW[1]
VCCIO[34]
1010mA
VCCASW[2]
1mA V5REF_SUS
VCCASW[3]
Clock and Miscellaneous
2
+V1.05S_VCCP
119mA VCCSUS3_3[7]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
DCPSUS[4]
VCCSUS3_3[1]
1mA V5REF
VCCASW[16]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
N16
+1.5VS
C258
.1U_0402_16V7K
T24
V23
2
V24
P24
+3V_PCH
C238
.1U_0402_16V7K
+V1.05S_VCCP
T26
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
AN24
P34
+3V_PCH
+3V_PCH
+PCH_V5REF_RUN
N20
N22
2
P20
VCC3_3[2]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCIO[13]
C247
1U_0402_6.3V6K
+3VS
+5VALW
P22
1
AA16
C249
.1U_0402_16V7K
+V1.05S_VCCP
T34
BD47
+1.05VS_VCCA_A_DPL
BF47
C256
1U_0402_6.3V6K
AF17
AF33
AF34
AG34
Near AF33
+V1.05S_VCCP
1
AG33
C259
1U_0402_6.3V6K
C254
.1U_0402_16V7K
C262
1U_0402_6.3V6K
VCCIO[4]
95mA
+V1.05S_VCCP
1
AF13
C255
2 .1U_0402_16V7K
+5VS
AH13
2
AH14
C257
1U_0402_6.3V6K
R279
10_0402_5%
AF14
AK1
+3VS
D2
+VCCSATAPLL
+PCH_V5REF_RUN
1
+1.5VS
AF11
+V1.05S_VCCP
AC16
AC17
AD17
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
C248
1U_0603_10V6K
C261
1U_0402_6.3V6K
2
+VCCSST
V16
+1.05VM_VCCSUS
T17
V19
C263
.1U_0402_16V7K
+V1.05S_VCCP
DCPSST
DCPSUS[1]
DCPSUS[2]
VCCASW[22]
+V1.05S_VCCP
BJ8
Near BJ8
1
+RTCVCC
C266
.1U_0402_16V7K
A22
C269
.1U_0402_16V7K
C268
1U_0402_6.3V6K
C265
4.7U_0603_6.3V6K
V_PROC_IO 1mA
VCCRTC
MISC
VCCSSC
C240
0.1U_0603_25V7K
AJ2
HOn-Die PLL voltage regulator enable
VCCVRM[1]
VCCIO[2]
VCCASW[23]
VCCASW[21]
T21
V21
T19
+3V_PCH
HDA
Near AG33
80mA
VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCAPLLSATA
VCCIO[3]
+V1.05S_VCCP
VCCADPLLB
80mA
CPU
VCCIO[6]
VCCADPLLA
+PCH_V5REF_SUS
1
+1.05VS_VCCA_A_DPL
RTC
SATA
Near AF17
D1
+3VS
2
B
+3V_PCH
R275
10_0402_5%
W16
VCCIO[12]
Y49
+3V_PCH
T23
+3VS
VCCIO[5]
+VCCRTCEXT
T29
VCCASW[18]
@
1
JUMP_43X118
VCCASW[17]
VCCASW[19]
T27
C236
.1U_0402_16V7K
AL29
+V1.05S_VCCP
+3V_PCH
PJ1
2
C233
1U_0402_6.3V6K
VCC3_3[5]
USB
+VCCAPLL_CPY_PCH
P28
V12
+PCH_VCCDSW
P26
+3VALW
VCCIO[31]
2
HOn-Die PLL voltage regulator enable
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
VCCIO[30]
3mA
VCCDSW3_3
N26
T16
+V1.05S_VCCP
VCCIO[29]
C234
.1U_0402_16V7K
VCCACLK
POWER
U4J
AD49
PCI/GPIO/LPC
Near T16
C232
1U_0402_6.3V6K
C231
10U_0603_6.3V6M
2
D
+3V_PCH
1
10mA VCCSUSHDA
P32
1
HM76@
C271
.1U_0402_16V7K
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
Title

PCH (8/9) PWR

Custom
Rev
1.0
LA-9631P
Date:

1
Sheet
21
of
60
U4I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
HM76@
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
HM76@
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (9/9) VSS
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
22
of
60
<5> PCIE_CTX_GRX_P[7..0]
<5> PCIE_CTX_GRX_N[7..0]
PCIE_CTX_GRX_P[7..0]
UV1A
PCIE_CRX_GTX_P[7..0]
PART 1 0F 9
PCIE_CTX_GRX_N[7..0]
PCIE_CRX_GTX_P[7..0] <5>
PCIE_CRX_GTX_N[7..0]
LVDS Interface
PCIE_CRX_GTX_N[7..0] <5>
UV1D
AA38
Y37
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
Y35
W36
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
W38
V37
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
V35
U36
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
U38
T37
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
T35
R36
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
R38
P37
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
P35
N36
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
Y33
Y32
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV1
2 CV2
PX@
PX@
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
W33 PCIE_CRX_C_GTX_P1
W32 PCIE_CRX_C_GTX_N1
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV3
2 CV4
PX@
PX@
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
U33 PCIE_CRX_C_GTX_P2
U32 PCIE_CRX_C_GTX_N2
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV5
2 CV6
PX@
PX@
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
U30 PCIE_CRX_C_GTX_P3
U29 PCIE_CRX_C_GTX_N3
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV7
2 CV8
PX@
PX@
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
T33
T32
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV9 PX@
2 CV10 PX@
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
T30
T29
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV11 PX@
2 CV12 PX@
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
P33
P32
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV13 PX@
2 CV14 PX@
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
P30
P29
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
0.22U_0402_10V6K 1
0.22U_0402_10V6K 1
2 CV15 PX@
2 CV16 PX@
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PART 7 0F 9
RSVD/VARY_BL
RSVD/DIGON
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
NC#AF35
NC#AG36
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
M35
L36
L38
K37
K35
J36
J38
H37
H35
G36
G38
F37
F35
E37
NC
NC
NC
NC
PCI EXPRESS INTERFACE
N38
M37
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AK27
AJ27
LVDS CONTROL
LVTMDP
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
N33
N32
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
N30
N29
NC
NC
L33
L32
L30
L29
Mars@
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37
MARS XT M2 FCBGA 962
K33
K32
J33
J32
K30
K29
H33
H32
+3VGS
CLOCK
PCIE_REFCLKP
PCIE_REFCLKN
AB35
AA36
<18> DGPU_HOLD_RST#
CALIBRATION
2 PX@
1
AH16
1K_0402_5%
GPU_RST#
AA30
TEST_PG
PCIE_CALR_RX
Y29 RV3
1 PX@
1 PX@
2 1.69K_0402_1%
2 1K_0402_1%
+0.95VGS
<18,36,37,42> PLT_RST#
2
1
+0.95VGS
Y
A
GPU_RST#
PX@
UV2
MC74VHC1G08DFT2G SC70 5P
PERSTB
RV2
Y30 RV1
PCIE_CALR_TX
CLK_PCIE_VGA
CLK_PCIE_VGA#
<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#
PX@
Mars@
RV4
SA000061J60
100K_0402_5% S IC 216-0842000 A0 MARS XT M2 BGA C38!
UV1
Sun@
SUN PRO M2 C38
SA00006BA20
S IC 216-0841000 A0 SUN PRO M2 BGA C38!
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
ATI_MarsXTX_M2_PCIE/LVDS
Custom
Date:
Rev
1.0
LA-9631P
Sheet
E
23
of
60
SWAPLOCKA
SWAPLOCKB
NC
NC
DPA
NC
NC
NC
NC
NC
NC
NC
NC
DPB
NC
NC
NC
NC
NC
NC
NC
NC
DPC
NC
NC
NC
NC
NC
NC
NC
NC
AJ23
AH23
SMBCLK
SMBus
SMBDATA
AK26
AJ26
SCL
SDA
AH20
AH18
AN16
GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
CLK_REQ_VGA#
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB
GPU_VID3
GPU_VID4
AG32
AG33
DPD
NC
NC
NC
NC
GPU_GPIO0
@
DV1
RB751V_SOD323
1
2
<16,42,46,48> ACIN
<53> GPU_VID5
GPU_GPIO5
GPU_VID5
GPU_VID1
<53> GPU_VID1
THM_ALERT#
@ RV12 1
2 10K_0402_5%
GPU_VID2
<53> GPU_VID2
<15> CLK_REQ_VGA#
<53> GPU_VID3
<53> GPU_VID4
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
R
AVSSN
G
AVSSN
B
AVSSN
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC
NC
NC
NC
NC
NC
NC
GPIO_29
GPIO_30
NC_SVI2
NC_SVI2
NC_SVI2
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
PS_0
AC30
+1.8VGS
+VREFG_GPU
1 499_0402_1%
+VREFG_GPU
AH13
PX_EN
AL21
PS_1[5]
PCIE Transmitter De-emphasis Enable

0:Tx de-emphasis disabled
1:Tx de-emphasis enabled
PS_1[1]
PCIE Gen3 Enable

(NOTE:RESERVED for Thames/Seymour and should
be strapped to 0)
VGA control
0:VGA controller capacity enabled
1:VGA controller capacity disabled (for multi-GPU)
TX_DEEMPH_EN
GPU_GPIO5
RV5
1 100K_0402_5%
THM_ALERT#
RV6
1 2.2K_0402_5%
BIF_GEN3_EN_A
AV31
AU30
0:GEN3 not support at power-on

1:GEN3 supported at power-on
AR32
AT31
AT33
AU32
AU14
AV13
BIF_VGA DIS
PS_2[4]
ROMIDCFG[2:0]
PS_0[3..1]
BIOS_ROM_EN
PS_2[3]
AU16
AV15
AT17
AR16
AU20
AT19
AUD[1]
NA
AUD[0]
NA
MLPS
DBG_VREFG
PS_1
PS_2
XXX
Enable external BIOS ROM device

0:Disabled
1:Enabled
AT21
AR20
AU22
AV21
Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture size
If PS_2[3]=1, defines ROM type
100 - 512Kbit M25P05A
(ST)
101 - 1Mbit M25P10A
(ST)
101 - 2Mbit M25P20
(ST)
101 - 4Mbit M25P40
(ST)
101 - 8Mbit M25P80
(ST)
100 - 512Kbit Pm25LV010 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
AT15
AR14
00 - No audio function
01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
AT23
AR22
XX
HDMI must only be enabled on systems that are

legally entitled. It isthe responsibility of the system
designer to ensure that the system is entitled to
support this feature.
AD39
AD37
VGA_R
AE36
AD35
VGA_G
AF37
AE38
VGA_B
AC36
AC38
HSYNC
VSYNC
T24
CEC_DIS
AVDD
MarsCRB
120ohm
1
0.1u
1
1u
1
10u
1
T25
T26
T4
T6
+AVDD
AB34
RV11 1 PX@
2 499_0402_1%
AD34
AE34
+AVDD
(1.8V@70mA AVDD)
AC33
AC34
+VDD1DI
(1.8V@117mA VDD1DI)
V13
U13
AF33
AF32
AA29
AG21
AC32
AM34
PS_0
AD31
PS_1
AG31
PS_2
AD33
PS_3
PS_0[4]
Reserved for future ASIC
NOTE:ALLOW FOR PULLUP PADS FOR THE

RESERVED STRAPS BUT DO NOT INSTALL
RESISTOR
IF THESE GPIOS ARE USEED, THEY MUST KEEP
LOW AND NOT CONFLICT DURING RESET
RESERVED
PS_1[3]
Reserved
RESERVED
PS_1[2]
Reserved
RESERVED
NA
Reserved
RESERVED
NA
Reserved (for Thames/Whistler/Seymour only)
AUD_PORT_CONN_PINSTRAP[2]
PS_3[5]
PS_3[4]
PS_0[5]
STRAPS TO INDICATE THE NUMBER OF AUDIO

CAPABLE DISPLAY OUTPUTS
111 = 0 usable endpoints
000 = all endpoints are usable
+1.8VGS
1
2
@
LV1
0_0402_5%
+VDD1DI
AC31
AD30
AD32
Design
1
1
1
1
+1.8VGS
XXX
2
@
LV2
0_0402_5%
VDD1DI
120ohm
0.1u
1u
10u
CEC_1
HPD1
MarsCRB
1
1
1
1
Design
1
1
1
1
MLPS Strap
R_pu
R_pd
PS_0[5:1]
Bits[5:4]
11
Bits[3:1]
000
Capacitor
NC
NC
4.75K
BACO
PS_1[5:1]
01
001
82nF
8.45K
2K
PS_2[5:1]
11
000
NC
NC
PX_EN
PS_3
4.75K
PS_3[5:1]
11
XXX
NC
Mapping to VRAM type please refer to page 4
AK32
AL31
+TSVDD
CV32
2
@
1U_0402_6.3V6K
CV31
.1U_0402_16V7K
CV30
Design
1
1
1
1
(1.8V@13mA TSVDD)
+TSVDD
10U_0603_6.3V6M
MarsCRB
1
1
1
1
2
@
LV3
0_0402_5%
PX@
PX@
+1.8VGS
AJ32
AJ33
NC
NC
GPIO_28_FDO
NC
NC
TS_A
DDCVGACLK
DDCVGADATA
TSVDD
TSVSS
Mars@
AN21
AM21
@
CV26
AK30
AK29
VGA_SMB_DA2
QV3A @
2N7002DW-T/R7_SOT363-6
4
AJ30
AJ31
EC_SMB_CK2
<15,39,42>
EC_SMB_DA2
<15,39,42>
1@
CV27
2
PX@ 1 @
CV29
CV28
2
1
2
X76@ RV27
PX@RV28
PX@
RV28
PX@RV29
PX@
RV29
4.75K_0402_1%
4.75K_0402_1%
2K_0402_1%
PX@RV30
PX@
RV30
4.75K_0402_1%
Place CLOSE VGA CHIP
QV3B @
2N7002DW-T/R7_SOT363-6
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
ATI_MarsXTX_M2_Main_MSIC
Size
C
Date:
1
1
VGA_SMB_CK2
DPLUS
DMINUS
+3VGS
@
RV25
10K_0402_5%
AF29
AG29
THERM_D+
THERM_D2 GPIO_28_FDO
10K_0402_5%
2
10K_0402_5%
@
RV24
10K_0402_5%
2 @
2 @
1
@
RV26
1 PX@
RV31
AL29
AM29
@ RV23
8.45K_0402_1%
PS_0
PS_1
PS_2
PS_3
+3VGS
1 RV16
1 RV17
AL30
AM30
X76@ RV20
@ RV21
PX@RV22
PX@
RV22
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
2
0_0402_5%
0_0402_5%
<39> REMOTE1+
<39> REMOTE1-
NC
NC
+3VGS
AN20
AM20
NC
NC
THERMAL
AM19
AL19
AUX2P
AUX2N
DDC2CLK
DDC2DATA
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
Enable
AM23
AN23
AK23
AL24
AM24
0.01U_0402_16V7K
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
+1.8VGS
0.082U_0402_16V7K
Disable
T27
T28
AM27
AL27
0.01U_0402_16V7K
AUX1P
AUX1N
MLPS
VGA_CLK
VGA_DAT
0.01U_0402_16V7K
DDC1CLK
DDC1DATA
TESTEN
AM26
AN26
AD28
DDC/AUX
DEBUG
2
TESTEN
5.11K_0402_5%
2
1K_0402_5%
1
@
RV18
1 PX@
RV19
+3VGS
TSVDD
120ohm
0.1u
1u
10u
Default Setting
Transmitter Power Savings Enable

0:50% Tx output swing
1:Full Tx output swing
1 249_0402_1%
2
1 .1U_0402_16V7K
CV23
PX@
GPIO_28_FDO
AK24
DESCRIPTION OF DEFAULT SETTINGS
PS_1[4]
AR30
AT29
PX@
2 RV13
PX@
2 RV14
0.60 V level, Please

VREFG Divider ans
cap close to ASIC
MLPS
TX_PWRS_ENB
I2C
<53> GPU_GPIO0
STRAPS
+3VGS
AT27
AR26
1U_0402_6.3V6K
@
CV18
VGA_SMB_CK2
VGA_SMB_DA2
AU26
AV25
10U_0603_6.3V6M
@
CV19
NC
NC
DBG_CNTL0
NC
NC
NC
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23
STRAPS
AT25
AR24
.1U_0402_16V7K
@
CV17
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AU24
AV23
10U_0603_6.3V6M
@
CV22
AJ21
AK21
NC
NC
1U_0402_6.3V6K
@
CV21
AD29
AC29
MUTI GFX
GENLK_CLK
GENLK_VSYNC
.1U_0402_16V7K
@
CV20
GENLK_CLK
GENLK_VSYNC
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
PART 2 0F 9
T1
T2
CONFIGURATION STRAPS
UV1B
Document Number
Rev
1.0
LA-9631P
E
Sheet
24
of
60
UV1C
PART 9 0F 9
(MPLL_PVDD:1.8V@130mA )
1
XTALIN
XTALOUT
XO_IN
SPLL_PVDD
+SPLL_VDDC AN9
SPLL_VDDC
XO_IN2
AN10
SPLL_PVSS
CLKTESTA
CLKTESTB
NC_XTAL_PVDD
NC_XTAL_PVSS
AK10
AL10
Mars@
@
CV41
.1U_0402_16V7K
@
RV33
51.1_0402_1%
@
CV42
.1U_0402_16V7K
@
RV34
51.1_0402_1%
CV37
10P_0402_50V8J
AW35
AF30
AF31
(SPLL_VDDC:0.95V@100mA )
2
@
LV6
0_0402_5%
3
XTALOUT
OSC
2
OSC
NC
27MHZ 10PF +-20PPM X3G027000DA1H
AW34
.1U_0402_16V7K
PX@
CV40
1U_0402_6.3V6K
PX@
CV39
10U_0603_6.3V6M
PX@
CV38
+SPLL_VDDC
MPLL_PVDD
MPLL_PVDD
Design
1
1
1
1
H7
H8
AM10
+SPV18
+0.95VGS
XTALOUT
2
@
LV5
0_0402_5%
.1U_0402_16V7K
PX@
CV45
MarsCRB
1
1
1
1
AU34
NC
XTALIN
(SPLL_PVDD:1.8V@75mA )
1U_0402_6.3V6K
PX@
CV44
Design
1
1
1
1
10U_0603_6.3V6M
PX@
CV43
SPLL_VDDC
120ohm
0.1u
1u
10u
MarsCRB
1
1
1
1
2 1M_0402_5%
YV1
+MPV18
SPLL_PVDD
120ohm
0.1u
1u
10u
RV32 1
XTALIN
CV36
10P_0402_50V8J
+SPV18
+1.8VGS
AV33
0_0603_5%
LV4
PLLS/XTAL
Design
1
1
1
1
.1U_0402_16V7K
PX@
CV35
MarsCRB
1
1
1
1
1U_0402_6.3V6K
PX@
CV34
MPLL_PVDD
220ohm
0.1u
1u
10u
+MPV18
10U_0603_6.3V6M
PX@
CV33
+1.8VGS
+1.5V to +1.5VGS
+3VS to +3VGS
+1.5VGS
+3VS
+3VGS
300mil(7.2A)
AO4430: Rdson: 5.5mohm @ VGS=10V

UV4
AO4304L_SO8
RV39 @
470_0603_5%
RV37 PX@
RV38 PX@
20K_0402_5%
20K_0402_5%
CV47
@
RV36
470_0603_5%
2
G
@
QV7
2N7002H_SOT23-3
PX@
CV52
.1U_0402_16V7K
DGPU_PWR_EN#
PX@
QV6
2N7002H_SOT23-3
2
G
DGPU_PWR_EN#
3
@ QV1
2N7002H_SOT23-3
S
PX@
CV53
0.1U_0402_25V6
1
RV42 @
0_0402_5%
2
G
DGPU_PWR_EN
RV41
240K_0402_5%
2
1
PX@
PX@
QV2
2N7002H_SOT23-3
D
DGPU_PWR_EN# 2
G
S
1
1@
CV50
.1U_0402_16V7K
B+
1 PX@
CV49
4.7U_0603_6.3V6K
PX@
1U_0603_10V6K
+5VALW
300mil(7.2A)
1
2
3
PX@
CV46
8
7
6
5
4.7U_0603_6.3V6K
QV8
LP2301ALT1G_SOT23-3
PX@
PX@
CV48
4.7U_0603_6.3V6K
+1.5V
+1.8VS to +1.8VGS
4.7U_0603_6.3V6K
QV4
LP2301ALT1G_SOT23-3
PX@
RV35
100K_0402_5%
+1.8VGS
+5VALW
PX@
@
CV200
10U_0603_6.3V6M
PX@ 1
CV199
+3VALW
+1.8VS
470_0603_5%
@ R290
@
CV201
1U_0402_6.3V6K
PX@
1 RV46
@
2
DGPU_PWR_EN# 1 RV92
0_0402_5%
PX@
QV10
S 2N7002H_SOT23-3
DGPU_PWR_EN 2
G
DVT
62K_0402_5%
2
G
PX@
QV9
2N7002H_SOT23-3
DGPU_PWR_EN
1
<18,42,51,53> DGPU_PWR_EN
330K_0402_5%
PX@
1 RV45
DGPU_PWR_EN#
@
QV11
2
G
PX@
CV202
.1U_0402_16V7K
2N7002H_SOT23-3
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
ATI_MarsXTX_M2_BACO POWER
Size
Document Number
Custom
Date:
Rev
1.0
LA-9631P
Sheet
E
25
of
60
UV1G
PART 6 0F 9
GND
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Mars@
UV1F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
PART 8 0F 9
+1.8VGS
MarsCRB
1
1
1
+DP_VDDR
2
@
RV43
0_0402_5%
Design
1
1
1
AP20
AP21
AP22
AP23
AU18
AV19
(DP_VDDR:1.8V@237mA/link )
+DP_VDDR
AH34
AJ34
AF34
AG34
AM37
AL38
AM32
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
AW28
AW18
RV44 2
PX@ 1 150_0402_1%
AM39
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
AP13
AT13
AP14
AP15
NC
NC
DP_CALR
Mars@
MarsCRB
1
1
1
Design
1
1
1
AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32
AG22
VSS_MECH
VSS_MECH
VSS_MECH
A39
AW1
AW39
MECH#1
MECH#2
MECH#3
TV12
TV13
TV14
PAD
PAD
PAD
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
ATI_MarsXTX_M2_PWR_GND
Custom
Date:
DP_VDDC
0.1u
1u
10u
DP GND
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
DP_VDDR
CALIBRATION
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31
10U_0603_6.3V6M
PX@
CV56
DP_VDDR
0.1u
1u
10u
AN24
AP24
AP25
AP26
AU28
AV29
+0.95VGS
(DP_VDDC:0.95V@280mA/link )
DP_VDDC
1U_0402_6.3V6K
PX@
CV55
DP_VDDR
.1U_0402_16V7K
PX@
CV54
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
.1U_0402_16V7K
PX@
CV59
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1U_0402_6.3V6K
PX@
CV58
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10U_0603_6.3V6M
PX@
CV57
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
Rev
1.0
LA-9631P
Sheet
E
26
of
60
MarsCRB
1
1
1
1
Design
0
0
3
1
+3VGS
Design
1
1
1
0
.1U_0402_16V7K
PX@
CV91
CORE
2
+VDDC_CT
+VDDR3
1
(VDDR3:3.3V@25mA)
2
@
LV9
0_0402_5%
LV10
( VDDR4:1.8V@300mA)
0_0603_5%
I/O
AF23
VDDR3
AF24 VDDR3
AG23
VDDR3
AG24
VDDR3
AD12
AF11
AF12
AF13
+VDDR4
+VDDR3
+VDDR4
DVP
VDDR4
VDDR4
VDDR4
VDDR4
VOLTAGE
SENESE
AF28 FB_VDDC
AG28
TV15
<53> VSSSENSE_VGA
AH29
ISOLATED
CORE I/O
<53> VCCSENSE_VGA
FB_VDDCI
FB_GND
Mars@
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AF15
VDDR4
AG11
VDDR4
AG13 VDDR4
AG15
VDDR4
Route as differential pair
BIF_VDDC
BIF_VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
10U_0603_6.3V6M
PX@
CV65
1U_0402_6.3V6K
@
CV64
.1U_0402_16V7K
PX@
CV63
+1.8VGS
@
1
0_0603_5%
1
10U_0603_6.3V6M
PX@
CV85
+0.95VGS
1U_0402_6.3V6K
@
CV84
N27
T27
(PCIE_VDDC:0.95V@2.5A_GEN2.0 )
1U_0402_6.3V6K
PX@
CV83
+0.95VGS
PCIE_VDDR
0.1u
1u
10u
MarsCRB
0
2
1
Design
2
3
1
PCIE_VDDC
1u
10u
MarsCRB
7
2
Design
5
1
+0.95VGS
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
1U_0402_6.3V6K
PX@
CV82
LEVEL
TRANSLATION
VDD_CT
VDD_CT
VDD_CT
VDD_CT
BACO
1U_0402_6.3V6K
PX@
CV81
AF26
AF27
AG26
AG27
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37
+0.95VGS
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
(BIF_VDDC:0.95V@1.4A)
10U_0603_6.3V6M
PX@
CV88
2
@
LV8
0_0402_5%
1U_0402_6.3V6K
@
CV90
NC
NC
NC
NC
NC
NC
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD
1U_0402_6.3V6K
PX@
CV87
MEM I/O
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
0.01U_0402_16V7K
PX@
CV62
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
1U_0402_6.3V6K
PX@
CV80
.1U_0402_16V7K
PX@
CV79
.1U_0402_16V7K
PX@
CV78
.1U_0402_16V7K
PX@
CV77
.1U_0402_16V7K
PX@
CV61
.1U_0402_16V7K
PX@
CV76
(VDD_CT:1.8V@13mA )
10U_0603_6.3V6M
PX@
CV89
Design
1
1
3
1
+1.8VGS
VDDR4
220ohm
0.1u
1u
10u
.1U_0402_16V7K
PX@
CV97
MarsCRB
1
1
2
0
1U_0402_6.3V6K
PX@
CV95
VDDR3
120ohm
0.1u
1u
10u
+VDDC_CT
10U_0603_6.3V6M
PX@
CV92
MarsCRB
1
1
1
1
+1.5VGS
LV7
+PCIE_VDDR
PART 5 0F 9
Design
0
5
5
0
5
1
+1.8VGS
VDD_CT
120ohm
0.1u
1u
10u
1U_0402_6.3V6K
PX@
CV75
1U_0402_6.3V6K
PX@
CV74
1U_0402_6.3V6K
PX@
CV73
1U_0402_6.3V6K
Mars@
CV72
1U_0402_6.3V6K
PX@
CV71
10U_0603_6.3V6M
PX@
CV70
1U_0402_6.3V6K
PX@
CV94
MarsCRB
5
5
0
5
3
0
1U_0402_6.3V6K
PX@
CV96
VDDR1
0.01u
0.1u
1u
2.2u
10u
220u
10U_0603_6.3V6M
PX@
CV69
10U_0603_6.3V6M
Mars@
CV68
10U_0603_6.3V6M
Mars@
CV60
220U_B2_2.5VM_R35
CV66
(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR
UV1E
For GDDR5, MVDDQ = 1.5V

(VDDR1:1.5V@3A,GDDR5:1125MHz )
1U_0402_6.3V6K
PX@
CV86
+1.5VGS
PCIE
+VGA_CORE
VGA_CORE Cap in power side sheet
AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
+VGA_CORE
3
(VDDCI:0.9~1.15V@8.8A)
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
ATI_MarsXTX_M2_Power
Size
C
Date:
Document Number
Rev
1.0
LA-9631P
E
Sheet
27
of
60
UV1H
UV1I
PART 3 0F 9
+VDD_MEM15_REFDA
+VDD_MEM15_REFSA
GDDR5/DDR3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7
DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B
1 PX@
RV47
2
120_0402_1%
C34
D29
D25
E20
E16
E12
J10
D7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
A34
E30
E26
C20
C16
C12
J11
F8
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
CLKA1
CLKA1B
J14 CLKA1
H14 CLKA1#
<29,30> MDA[0..63]
MAA[15..0]
A_BA[2..0]
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
<29>
<29>
<29>
<29>
<30>
<30>
<30>
<30>
<29>
<29>
<29>
<29>
<30>
<30>
<30>
<30>
CLKA1 <30>
CLKA1# <30>
RASA0# <29>
RASA1# <30>
CASA0# <29>
CASA1# <30>
CSA0#_0 <29>
CSA1B_0
CSA1B_1
M13 CSA1#_0
K16
CSA1#_0 <30>
K26 WEA0#
L15 WEA1#
B_BA[2..0] <31,32>
A_BA[2..0] <29,30>
<29>
<29>
<29>
<29>
<30>
<30>
<30>
<30>
K24 CSA0#_0
K27
WEA0B
WEA1B
MAB[15..0] <31,32>
B_BA[2..0]
ODTA0 <29>
ODTA1 <30>
K20 CASA0#
K17 CASA1#
K21 CKEA0
J20 CKEA1
MAA[15..0] <29,30>
CLKA0 <29>
CLKA0# <29>
K23 RASA0#
K19 RASA1#
CKEA0
CKEA1
PART 4 0F 9
MDB[0..63]
<31,32> MDB[0..63]
MDA[0..63]
MAB[15..0]
CSA0B_0
CSA0B_1
CKEA0 <29>
CKEA1 <30>
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12
WEA0# <29>
WEA1# <30>
GDDR5/DDR3
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7
DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
H23 MAA13
J19 MAA14
M21 MAA15
M20
MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD
M12
NC
AH12 NC
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
H27 CLKA0
G27 CLKA0#
CASA0B
CASA1B
M27 MEM_CALRP0
A32
C32
D23
E22
C14
A14
E10
D9
CLKA0
CLKA0B
RASA0B
RASA1B
L27 NC
N12
NC
AG12
NC
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
J21 ODTA0
G19 ODTA1
ADBIA0/ODTA0
ADBIA1/ODTA1
L18
MVREFDA
L20 MVREFSA
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
MEMORY INTERFACE B
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MEMORY INTERFACE A
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST
Mars@
Mars@
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
T7
W7
ODTB0
ODTB1
L9
L8
CLKB0
CLKB0#
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
AD8 CLKB1
AD7 CLKB1#
T10 RASB0#
Y10 RASB1#
W10 CASB0#
AA10 CASB1#
<31>
<31>
<31>
<31>
<32>
<32>
<32>
<32>
<31>
<31>
<31>
<31>
<32>
<32>
<32>
<32>
<31>
<31>
<31>
<31>
<32>
<32>
<32>
<32>
ODTB0 <31>
ODTB1 <32>
CLKB0 <31>
CLKB0# <31>
RASB0# <31>
RASB1# <32>
CASB0# <31>
CASB1# <32>
P10 CSB0#_0
L10
CSB0#_0 <31>
AD10 CSB1#_0
AC10
CSB1#_0 <32>
U10 CKEB0
AA11 CKEB1
CLKB1 <32>
CLKB1# <32>
CKEB0 <31>
CKEB1 <32>
N10 WEB0#
AB11 WEB1#
WEB0# <31>
WEB1# <32>
T8
MAB13
W8 MAB14
U12 MAB15
V12
AH11 DRAM_RST#_R
2
10_0402_5%
DRAM_RST#_R
+VDD_MEM15_REFSB
CV100
120P_0402_50V9
PX@
RV58
100_0402_1%
PX@
RV57
4.99K_0402_1%
PX@
CV99
1U_0402_6.3V6K
2 Mars@
RV56
100_0402_1%
Mars@
CV98
1U_0402_6.3V6K
2 Mars@
1
+VDD_MEM15_REFDB
1
1 PX@
RV54
CV101
1U_0402_6.3V6K
2 PX@
RV59
100_0402_1%
PX@
2
51.1_0402_1%
1 PX@
RV53
RV52
40.2_0402_1%
PX@
1
2
<29,30,31,32> DRAM_RST#
+1.5VGS
1
2
+VDD_MEM15_REFSA
RV51
40.2_0402_1%
PX@
1
1
+VDD_MEM15_REFDA
RV55
100_0402_1%
Mars@
+1.5VGS
RV48
4.7K_0402_5%
@
RV50
40.2_0402_1%
Mars@
RV49
40.2_0402_1%
Mars@
+1.5VGS
1
+1.5VGS
+1.5VGS
Ball to RV57 < 1"

CV100 to RV57 < 200 mil
CV100 to RV53 < 1"
CV102
1U_0402_6.3V6K
2 PX@
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
ATI_MarsXTX_M2_MEM IF
Size
C
Date:
Document Number
Rev
1.0
LA-9631P
E
Sheet
28
of
60
UV6
UV5
MAA[15..0]
M2
N8
M3
<28,30> A_BA0
<28,30> A_BA1
<28,30> A_BA2
J7
K7
K9
<28> CLKA0
<28> CLKA0#
<28> CKEA0
<28>
<28>
<28>
<28>
<28>
K1
L2
J3
K3
L3
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
F3
C7
QSA2
QSA0
<28> QSA2
<28> QSA0
<28> DQMA2
<28> DQMA0
DQMA2
DQMA0
E7
D3
QSA#2
QSA#0
G3
B7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
T2
<28,30,31,32> DRAM_RST#
L8
J1
L1
J9
L9
BA0
BA1
BA2
Mars@
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
CLKA0# 1
RV61
Mars@2
40.2_0402_1%
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
<28> DQMA3
<28> DQMA1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
<28> QSA3
<28> QSA1
<28> QSA#3
<28> QSA#1
CLKA0
CLKA0#
CKEA0
J7
K7
K9
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
QSA3
QSA1
F3
C7
DQMA3
DQMA1
E7
D3
QSA#3
QSA#1
G3
B7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
J1
L1
J9
L9
E3
F7
F2
F8
H3
H8
G2
H7
MDA24
MDA30
MDA27
MDA29
MDA25
MDA28
MDA26
MDA31
D7
C3
C8
C2
A7
A2
B8
A3
MDA12
MDA10
MDA14
MDA11
MDA13
MDA9
MDA15
MDA8
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
L8
RV85
240_0402_1%
Mars@
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
DRAM_RST# T2
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
M2
N8
M3
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
X76@
96-BALL
SDRAM DDR3
X76@
+1.5VGS
CV195
0.01U_0402_16V7K
Mars@
+1.5VGS
Mars@
RV63
4.99K_0402_1%
+1.5VGS
A_BA0
A_BA1
A_BA2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
Mars@2
40.2_0402_1%
CLKA0 1
RV60
MDA0
MDA5
MDA1
MDA6
MDA3
MDA4
MDA2
MDA7
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
RV84
240_0402_1%
D7
C3
C8
C2
A7
A2
B8
A3
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
+1.5VGS
<28> QSA#2
<28> QSA#0
MDA23
MDA19
MDA22
MDA18
MDA21
MDA17
MDA20
MDA16
Mars@
RV62
4.99K_0402_1%
15mil
+VREFC_A1
1
2
Mars@
RV65
4.99K_0402_1%
Mars@
Mars@
CV124
@
1U_0402_6.3V6K
CV122
Mars@
1U_0402_6.3V6K
CV121
Mars@
1U_0402_6.3V6K
CV120
Mars@
1U_0402_6.3V6K
CV119
Mars@
1U_0402_6.3V6K
CV118
Mars@
1U_0402_6.3V6K
CV117
Mars@
1U_0402_6.3V6K
+1.5VGS
CV116
Mars@
10U_0603_6.3V6M
CV125
@
.1U_0402_16V7K
CV113
Mars@
1U_0402_6.3V6K
CV112
Mars@
1U_0402_6.3V6K
CV109
Mars@
1U_0402_6.3V6K
CV108
Mars@
1U_0402_6.3V6K
CV107
Mars@
1U_0402_6.3V6K
CV106
Mars@
1U_0402_6.3V6K
CV105
Mars@
10U_0603_6.3V6M
+1.5VGS
CV115
@
10U_0603_6.3V6M
+1.5VGS
CV104
.1U_0402_16V7K
CV103
.1U_0402_16V7K
+VREFC_A0
Mars@
RV64
4.99K_0402_1%
15mil
1
<28,30> MAA[15..0]
MDA[0..31]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
<28> MDA[0..31]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
VREFCA
VREFDQ
M8
H1
+VREFC_A0
M8
H1
+VREFC_A1
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

ATI_Whistler_M2_VRAM_A
Document Number
Rev
1.0
LA-9631P
1
Sheet
29
of
60
UV7
UV8
+VREFC_A2
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
<28> MDA[32..63]
<28,29> MAA[15..0]
MDA[32..63]
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA[15..0]
A_BA0
A_BA1
A_BA2
<28,29> A_BA0
<28,29> A_BA1
<28,29> A_BA2
<28> CLKA1
<28> CLKA1#
<28> CKEA1
<28>
<28>
<28>
<28>
<28>
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
<28> QSA4
<28> QSA5
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
QSA4
QSA5
F3
C7
DQMA4
DQMA5
E7
D3
QSA#4
QSA#5
G3
B7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA38
MDA36
MDA39
MDA34
MDA35
MDA33
MDA37
MDA32
D7
C3
C8
C2
A7
A2
B8
A3
MDA42
MDA44
MDA40
MDA46
MDA43
MDA45
MDA41
MDA47
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
+1.5VGS
<28> QSA6
<28> QSA7
DRAM_RST# T2
<28,29,31,32> DRAM_RST#
L8
Mars@
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
<28> DQMA6
<28> DQMA7
<28> QSA#6
<28> QSA#7
CLKA1
CLKA1#
CKEA1
J7
K7
K9
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
QSA6
QSA7
F3
C7
DQMA6
DQMA7
E7
D3
QSA#6
QSA#7
G3
B7
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
DRAM_RST# T2
RESET
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RV86
240_0402_1%
J1
L1
J9
L9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M2
N8
M3
<28> QSA#4
<28> QSA#5
DML
DMU
A_BA0
A_BA1
A_BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
ZQ/ZQ0
J1
L1
J9
L9
RV87
240_0402_1%
Mars@
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
<28> DQMA4
<28> DQMA5
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
+1.5VGS
BA0
BA1
BA2
M8
H1
+VREFC_A3
96-BALL
SDRAM DDR3
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA49
MDA51
MDA48
MDA52
MDA50
MDA53
MDA55
MDA54
D7
C3
C8
C2
A7
A2
B8
A3
MDA60
MDA57
MDA63
MDA56
MDA61
MDA59
MDA62
MDA58
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
C
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
X76@
+1.5VGS
B
+VREFC_A3
1
Mars@
Mars@
RV71
4.99K_0402_1%
Mars@
CV148
Mars@
1U_0402_6.3V6K
CV193
@
1U_0402_6.3V6K
CV147
@
.1U_0402_16V7K
CV146
Mars@
1U_0402_6.3V6K
CV145
Mars@
1U_0402_6.3V6K
CV144
Mars@
1U_0402_6.3V6K
CV141
Mars@
1U_0402_6.3V6K
+1.5VGS
CV139
Mars@
10U_0603_6.3V6M
CV136
Mars@
1U_0402_6.3V6K
CV135
Mars@
1U_0402_6.3V6K
CV134
@
.1U_0402_16V7K
CV164
Mars@
1U_0402_6.3V6K
CV132
Mars@
1U_0402_6.3V6K
CV154
Mars@
1U_0402_6.3V6K
CV152
Mars@
1U_0402_6.3V6K
CV128
Mars@
10U_0603_6.3V6M
+1.5VGS
CV138
@
10U_0603_6.3V6M
+1.5VGS
Mars@
RV70
4.99K_0402_1%
+VREFC_A2
15mil
15mil
CV126
.1U_0402_16V7K
CV196
0.01U_0402_16V7K
Mars@
CV127
.1U_0402_16V7K
Mars@
RV68
4.99K_0402_1%
Mars@2
40.2_0402_1%
Mars@
RV67
4.99K_0402_1%
Mars@2
40.2_0402_1%
CLKA1# 1
RV69
CLKA1 1
RV66
+1.5VGS
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

Document Number
Rev
1.0
LA-9631P
1
Sheet
30
of
60
UV9
<28> MDB[0..31]
<28,32> MAB[15..0]
MDB[0..31]
MAB[15..0]
<28> DQMB2
<28> DQMB0
QSB2
QSB0
F3
C7
DQMB2
DQMB0
E7
D3
QSB#2
QSB#0
G3
B7
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PX@ 2
40.2_0402_1%
DQSL
DQSU
T2
<28,29,30,32> DRAM_RST#
RESET
L8
CV197
0.01U_0402_16V7K
PX@
CLKB0# 1
RV73
<28> QSB#2
<28> QSB#0
J1
L1
J9
L9
RV88
240_0402_1%
PX@
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
PX@ 2
40.2_0402_1%
CLKB0 1
RV72
E3
F7
F2
F8
H3
H8
G2
H7
MDB19
MDB20
MDB22
MDB16
MDB23
MDB17
MDB21
MDB18
D7
C3
C8
C2
A7
A2
B8
A3
MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5
M8
H1
+VREFC_B1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
K1
L2
J3
K3
L3
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
J7
K7
K9
<28> CLKB0
<28> CLKB0#
<28> CKEB0
<28> QSB2
<28> QSB0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
M2
N8
M3
<28,32> B_BA0
<28,32> B_BA1
<28,32> B_BA2
<28>
<28>
<28>
<28>
<28>
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
<28> QSB3
<28> QSB1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
<28> DQMB3
<28> DQMB1
<28> QSB#3
<28> QSB#1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
B_BA0
B_BA1
B_BA2
M2
N8
M3
CLKB0
CLKB0#
CKEB0
J7
K7
K9
ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#
K1
L2
J3
K3
L3
QSB3
QSB1
F3
C7
DQMB3
DQMB1
E7
D3
QSB#3
QSB#1
G3
B7
DRAM_RST# T2
L8
1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
UV10
VREFCA
VREFDQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
RV89
240_0402_1%
PX@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
M8
H1
+VREFC_B0
96-BALL
SDRAM DDR3
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDB26
MDB30
MDB24
MDB29
MDB27
MDB28
MDB25
MDB31
D7
C3
C8
C2
A7
A2
B8
A3
MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+1.5VGS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
X76@
+1.5VGS
1
+1.5VGS
1
PX@
RV75
4.99K_0402_1%
PX@
RV74
4.99K_0402_1%
15mil
1
2
1
2
CV150
.1U_0402_16V7K
CV171
PX@
.1U_0402_16V7K
CV170
PX@
.1U_0402_16V7K
CV169
PX@
.1U_0402_16V7K
CV168
PX@
.1U_0402_16V7K
CV167
PX@
1U_0402_6.3V6K
CV166
PX@
1U_0402_6.3V6K
+1.5VGS
CV165
PX@
1U_0402_6.3V6K
+1.5VGS
CV162
PX@
10U_0603_6.3V6M
CV160
@
.1U_0402_16V7K
CV159
PX@
1U_0402_6.3V6K
CV158
@
.1U_0402_16V7K
CV156
PX@
1U_0402_6.3V6K
CV155
PX@
1U_0402_6.3V6K
CV130
@
.1U_0402_16V7K
CV183
PX@
1U_0402_6.3V6K
CV129
@
1U_0402_6.3V6K
PX@
RV77
4.99K_0402_1%
PX@
CV161
PX@
10U_0603_6.3V6M
+1.5VGS
CV149
.1U_0402_16V7K
PX@
RV76
4.99K_0402_1%
15mil
+VREFC_B1
+VREFC_B0
PX@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

ATI_Whistler_M2_VRAM_B
Document Number
Rev
1.0
LA-9631P
1
Sheet
31
of
60
UV11
MDB[0..31]
<28,31> MAB[15..0]
MAB[15..0]
M2
N8
M3
B_BA0
B_BA1
B_BA2
<28,31> B_BA0
<28,31> B_BA1
<28,31> B_BA2
J7
K7
K9
<28> CLKB1
<28> CLKB1#
<28> CKEB1
<28>
<28>
<28>
<28>
<28>
<28> QSB4
<28> QSB5
<28> DQMB4
<28> DQMB5
<28> QSB#4
<28> QSB#5
K1
L2
J3
K3
L3
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
QSB4
QSB5
F3
C7
DQMB4
DQMB5
E7
D3
QSB#4
QSB#5
G3
B7
DRAM_RST# T2
<28,29,30,31> DRAM_RST#
L8
J1
L1
J9
L9
PX@
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38
D7
C3
C8
C2
A7
A2
B8
A3
MDB44
MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB42
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
<28> QSB6
<28> QSB7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
<28> DQMB6
<28> DQMB7
<28> QSB#6
<28> QSB#7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
B_BA0
B_BA1
B_BA2
M2
N8
M3
CLKB1
CLKB1#
CKEB1
J7
K7
K9
ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#
K1
L2
J3
K3
L3
QSB6
QSB7
F3
C7
DQMB6
DQMB7
E7
D3
QSB#6
QSB#7
G3
B7
DRAM_RST# T2
L8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
M8
H1
+VREFC_B3
+1.5VGS
BA0
BA1
BA2
RV90
240_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<28> MDB[32..63]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
UV12
VREFCA
VREFDQ
J1
L1
J9
L9
RV91
240_0402_1%
PX@
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
96-BALL
SDRAM DDR3
X76@
E3
F7
F2
F8
H3
H8
G2
H7
MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48
D7
C3
C8
C2
A7
A2
B8
A3
MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60
+1.5VGS
BA0
BA1
BA2
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
+1.5VGS
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
DML
DMU
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
M8
H1
+VREFC_B2
96-BALL
SDRAM DDR3
X76@
+1.5VGS
2
2
PX@
1
1
CV194
@
1U_0402_6.3V6K
CV192
@
.1U_0402_16V7K
CV191
@
.1U_0402_16V7K
CV190
PX@
1U_0402_6.3V6K
PX@
CV189
PX@
1U_0402_6.3V6K
CV188
PX@
1U_0402_6.3V6K
CV187
PX@
1U_0402_6.3V6K
+1.5VGS
CV186
PX@
1U_0402_6.3V6K
CV185
PX@
10U_0603_6.3V6M
CV181
@
.1U_0402_16V7K
CV179
PX@
1U_0402_6.3V6K
CV178
PX@
1U_0402_6.3V6K
CV177
PX@
1U_0402_6.3V6K
CV176
PX@
1U_0402_6.3V6K
CV175
PX@
1U_0402_6.3V6K
CV174
PX@
10U_0603_6.3V6M
+1.5VGS
CV184
@
10U_0603_6.3V6M
+1.5VGS
PX@
RV82
4.99K_0402_1%
1
2
PX@
RV83
4.99K_0402_1%
+VREFC_B3
+VREFC_B2
CV173
.1U_0402_16V7K
CV198
0.01U_0402_16V7K
PX@
15mil
15mil
CV172
.1U_0402_16V7K
PX@
RV78
4.99K_0402_1%
PX@
RV80
4.99K_0402_1%
PX@ 2
40.2_0402_1%
PX@ 2
40.2_0402_1%
CLKB1# 1
RV81
CLKB1 1
RV79
+1.5VGS
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

Document Number
Rev
1.0
LA-9631P
1
Sheet
32
of
60
LCD POWER CIRCUIT
Camera
+3VS
W=60mils
+LCDVDD_CONN
W=60mils
U72
SS
EN
APL3512ABI-TRG_SOT23-5
R435CMOS@
150K_0402_5%
2
<17> PCH_ENVDD
(20 MIL)
1
C4
1500P_0402_50V7K
+3VS_CMOS
GND
CMOS@
Q83
LP2301ALT1G_SOT23-3
(20 MIL)
VIN
VOUT
+LCDVDD_CONN
4.7U_0603_6.3V6K
C516
+3VS
CMOS@
C518
.1U_0402_16V7K
1
R02
C519 @
10U_0603_6.3V6M
4.7V
<42> CMOS_ON#
1
R408
100K_0402_5%
C520 CMOS@
.1U_0402_16V7K
LCD Conn.
+LEDVDD
B+
@
R813
1
0_0805_5%
C541
4.7U_0805_25V6-K
@
JLVDS1
R509 1
2 0_0402_5%
BKOFF#
<17> PCH_PWM
<17> LVDS_ACLK
<17> LVDS_ACLK#
BKOFF#
<17> LVDS_A2
<17> LVDS_A2#
<17> LVDS_A1
<17> LVDS_A1#
<17> LVDS_A0
<17> LVDS_A0#
<17> EDID_DATA
<17> EDID_CLK
<42> BKOFF#
R716
10K_0402_5%
2
+3VS
+LCDVDD_CONN
(60 MIL)
+3VS
+3VS_CMOS
CMOS
For EMI
<18> USB20_P3
<18> USB20_N3
1 R688@
1 R684@
USB20_P3
USB20_N3
2 0_0402_5%
2 0_0402_5%
USB20_P3_R
USB20_N3_R
USB20_P3_R
USB20_N3_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G1
G2
G3
G4
31
32
33
34
ACES_88341-3001 ME@
L58 @
USB20_P3
USB20_N3
USB20_P3_R
USB20_N3_R
WCM-2012-900T_4P
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

LVDS/CAMERA
Custom
Date:
Rev
1.0
LA-9631P
Sheet
1
33
of
60
DAC_BLU
DAC_GRN
DAC_RED
GREEN
BLUE
1
10P_0402_50V8J
C527
1
2
3
4
RED
10P_0402_50V8J
C526
RP22
8
7
6
5
10P_0402_50V8J
C524
10P_0402_50V8J
C522
<17> DAC_BLU
10P_0402_50V8J
C523
<17> DAC_GRN
10P_0402_50V8J
C525
FCM1608CF-121T03 0603
1
2
L30
FCM1608CF-121T03 0603
1
2
L31
FCM1608CF-121T03 0603
1
2
L32
<17> DAC_RED
+5V_Display
150_0804_8P4R_1%
JCRT1
PAD
For EMI
T66
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
NC11
RED
CRT_DDC_DAT_CONN
GREEN
JVGA_HS_R
BLUE
JVGA_VS_R
CRT_DDC_CLK_CONN
@
C531
.1U_0402_16V7K
U10
1
<17> CRT_DDC_DATA
10
VIDEO1
VCC_DDC
VIDEO2
DDC_IN1
VIDEO3
DDC_IN2
DDC_OUT1
SYNC_IN1
DDC_OUT2
1
C6
2
0.22U_0402_10V6K
RED
GREEN
BLUE
CRT_DDC_DAT_CONN
+5V_Display
R31
4.7K_0402_5%
R33
4.7K_0402_5%
C537
.1U_0402_16V7K
VCC_VIDEO
8
3
<17> CRT_DDC_CLK
<17> CRT_VSYNC
<17> CRT_HSYNC
11
13
15
6
SYNC_IN2
GND
SYNC_OUT1
SYNC_OUT2
12
CRT_DDC_CLK_CONN
14
2
JVGA_VS 1 R411
22_0402_5%
JVGA_VS_R
16
2
JVGA_HS 1 R412
22_0402_5%
JVGA_HS_R
TPD7S019-15DBQR_SSOP16
@
C411
10P_0402_50V8J
BYP
VCC_SYNC
C412
10P_0402_50V8J
+3VS
16
17
CONTE_80431-5K1-152
ME@
+5VS
C529
.1U_0402_16V7K
G
G
Compal Secret Data
2011/06/15
Issued Date
2012/07/11
Deciphered Date
Title

CRT Connector
Custom
Date:
Rev
1.0
LA-9631P
Sheet
E
34
of
60
For EMI
+5V_Display
U73
+5VS
<17> HDMI_CLK-_CK
HDMI_CLK-_CK
HDMI_CLK+_CONN
L36
<17> HDMI_TX0-_CK
HDMI_TX0-_CK
R485
1M_0402_5%
HDMI@
HDMI@
HDMI_TX0+_CONN
HDMI_TX0-_CONN
.1U_0402_16V7K
1
D
TMDS_B_HPD#
<17> TMDS_B_HPD#
Q93
HDMI@
2N7002H_SOT23-3
1
C543
GND
2
W=40mils
IN
C544
HDMI_CLK-_CONN
<17> HDMI_TX0+_CK
HDMI_TX0+_CK
+3VS
WCM-2012HS-900T
OUT
HDMI@
<17> HDMI_CLK+_CK
L35
HDMI_CLK+_CK
2
.1U_0402_16V7K
AP2330W-7_SC59-3
ZZZ3
For CRT and HDMI
WCM-2012HS-900T
<17> HDMI_TX1+_CK
HDMI_TX1+_CK
<17> HDMI_TX1-_CK
HDMI_TX1-_CK
HDMI Logo
HDMI@
HDMI_TX1+_CONN
HDMI_TX1-_CONN
RO0000003HM
R488
20K_0402_5%
HDMI@
JHDMI1
L37
L38
HDMI_TX2+_CK
<17> HDMI_TX2-_CK
HDMI_TX2-_CK
+5V_Display
HDMIDAT_R
HDMICLK_R
HDMI@
HDMI_TX2+_CONN
HDMI_TX2-_CONN
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
WCM-2012HS-900T
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_DET
WCM-2012HS-900T
<17> HDMI_TX2+_CK
HDMI_TX0+_CONN
HDMI_TX1-_CONN
+3VS
HDMI_TX1+_CONN
HDMI_TX2-_CONN
Pull up R for PCH OR VGA SIDE
HDMI_TX2+_CONN
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
SUYIN_100042GR019M23DZL
ME@
2
+3VS
+5V_Display
45@
RP21
1
2
3
4
HDMIDAT_NB
HDMIDAT_R
HDMICLK_NB
HDMICLK_R
DVT
RP26
<17> HDMICLK_NB
HDMICLK_R
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_CLK+_CONN
HDMI_CLK-_CONN
8
7
6
5
Q63A
HDMI@
2N7002DW-T/R7_SOT363-6
2.2K_0804_8P4R_5%
HDMI@
<17> HDMIDAT_NB
5
6
7
8
HDMIDAT_R
680 +-5% 8P4R
HDMI@
Q63B
HDMI@
2N7002DW-T/R7_SOT363-6
RP27
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN
5
6
7
8
ESD
D32
1
D28
1
D33
1
680 +-5% 8P4R

HDMI@
HDMIDAT_R
9 10
HDMIDAT_R
HDMI_CLK-_CONN
9 10
HDMI_CLK-_CONN
HDMI_TX0+_CONN 9 10
HDMI_TX0+_CONN
HDMICLK_R
HDMICLK_R
HDMI_CLK+_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN 8
HDMI_TX0-_CONN
HDMI_DET
HDMI_DET
HDMI_TX1-_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN 7
HDMI_TX2+_CONN
HDMI_TX1+_CONN
HDMI_TX1+_CONN
HDMI_TX2-_CONN 6
HDMI_TX2-_CONN
YSCLAMP0524P_SLP2510P8-10-9
4
3
2
1
+3VS
1
4
3
2
1
2
G
Q95
HDMI@
2N7002H_SOT23-3
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
B
HDMI CONN
Document Number
Date: Wednesday, February 27, 2013
Rev
1.0
LA-9631P
Sheet
1
35
of
60
Mini Card for WLAN/WiMAX(Half)

1
+3VS
+3VS_WLAN
80mil
J6
1
+1.5VS
JUMP_43X79
@
<16> PCIE_WAKE#
JWLN1
R508 1
2 0_0402_5%
PCIE_WAKE#_WLAN
<19> PCH_BT_ON#
<15> CLKREQ_WLAN#
<15> CLK_PCIE_WLAN1#
<15> CLK_PCIE_WLAN1
+3VS_WLAN
1 R405
2
1K_0402_5%
For EC to detect
debug card insert.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
PCH_WL_OFF# <18>
PLT_RST# <18,23,37,42>
+3VS_WLAN
1 R501
1 R502
2 @ 0_0402_5%
2 @ 0_0402_5%
SMB_CLK_S3 <12,13,15>
SMB_DATA_S3 <12,13,15>
USB20_N10 <18>
USB20_P10 <18>
54
BELLW_80003-8041
ME@
R507
100K_0402_5%
3
53
DVT
<19> INTEL_BT_OFF#
100_0402_1%
R505
2
2
R506
100_0402_1%
INTEL_BT_OFF#_R
1
1
<42,43> EC_TX
<42,43> EC_RX
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Date:

Mini-Card/NEW Card/SIM
Document Number
Rev
1.0
LA-9631P
Sheet
E
36
of
60
For LAN & Green CLK
+3V_LAN
+3VALW
+LX
Close together
J10
LL2
1
2
10K_0402_5%
CL6
CL5
CL4
Note: Place Close to LAN chip

LL1 DCR< 0.15 ohm
Rate current > 1A
SWR@
4.7U_0603_6.3V6K
LAN_PWR_ON#
RL3
<42> LAN_PWR_ON#
@
QL1
LP2301ALT1G_SOT23-3
LL3
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
2
1
2
+1.1_AVDDL
+LX_R
+1.1_AVDDL_L
1U_0402_6.3V6K
10U_0603_6.3V6M
CL3
CL2
JUMP_43X79
LL1 SWR@
1
2 +LX
4.7UH_SIA4012-4R7M_20%
+LX_R
.1U_0402_16V7K
.1U_0402_16V7K
CL1
1000P_0402_50V7K
10U
@
CL7
.1U_0402_16V7K
SWR@SWR@SWR@
Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
UL1
RL4
+3V_LAN
8172@
+3V_LAN
2 4.7K_0402_5%
@
UL1
35
32
33
<15> CLK_PCIE_LAN#
<15> CLK_PCIE_LAN
RL7
<42> LAN_WAKE#
+3V_LAN
PCIE_WAKE#_R
2 0_0402_5%
RL9
PLT_RST#
25
26
2 4.7K_0402_5%
@
28
27
Vendor recommand reseve the

PU resistor close LAN chip
7
8
LAN_XTALO
LAN_XTALI
+3V_LAN
RL11 1
2 4.7K_0402_5%
AR8151/AR8161
RX_N
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
RX_P
REFCLK_N
REFCLK_P
PERST#
SMCLK
SMDATA
RBIAS
NC
TESTMODE
VDD33
LX
XTLO
XTLI
Near
Pin13
Near
Pin19
Near
Pin6
41
MDI0MDI0+
MDI1MDI1+
10
LAN_RBIAS
+3V_LAN
40
+LX
+1.7_VDDCT
24
37
+LX_R
MDI0MDI0+
MDI1MDI1+
<38>
<38>
<38>
<38>
Place Close to PIN1

1
CLKREQ#
DVDDL/PPS
DVDDL_REG/DVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL
+3V_LAN
RL8
2.37K_0402_1%
Place Close to PIN1
+LX
30K_0402_5%
+3V_LAN
AVDDH/AVDD33
AVDDH
AVDDH_REG
16
22
9
don't @ (could be B C cost done)
+3V_LAN
+2.7_AVDDH
+2.7_AVDDH
GND
AR8162-BL3A-R_QFN40_5X5
8162@
SA000052J20
IC AR8162-BL3A-R QFN 40P E-LAN CTRL
+2.7_AVDDH
CL22
.1U_0402_16V7K
CL20
CL19
1U_0402_6.3V6K
CL21
.1U_0402_16V7K
CL18
.1U_0402_16V7K
CL17
.1U_0402_16V7K
13
19
31
34
6
Place close to Pin16

12
11
15
14
18
17
21
20
RL10
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
W AKE#
VDDCT/ISOLAN
<15> CLKREQ_LAN#
RL12 if use LDO modue
CL16
10U_0603_6.3V6M
Atheros
TX_P
CL15
10U_0603_6.3V6M
36
CL14
1U_0402_6.3V6K
PCIE_PRX_C_DTX_P1 30
RL12
10K_0402_5%
2 LDO@ 1
mount
CL13
.1U_0402_16V7K
2 .1U_0402_16V7K
38
39
23
CL12
1000P_0402_50V7K
1
2
CL11 1
LED_0
LED_1
LED_2
1U_0402_6.3V6K
TX_N
CL25
PCIE_PRX_C_DTX_N1 29
.1U_0402_16V7K
CL26
2 .1U_0402_16V7K
CL24
.1U_0402_16V7K
CL9
1U_0402_6.3V6K
.1U_0402_16V7K
CL23
Place Close to Chip
CL8
CL10
SA000065410
S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL
1U_0402_6.3V6K
QCA8172-BL3A-R
.1U_0402_16V7K
PLT_RST#
<18,23,36,42> PLT_RST#
Near
Pin9
Near
Pin31
Near
Pin22
@
Near
Pin37
LAN_XTALI
LAN_XTALO
YL1
4
1
CL28
15P_0402_50V8J
Lenovo
NC
OSC
OSC
NC
3
2
1 25MHZ_10PF_7V25000014
CL29
15P_0402_50V8J
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
LAN-AR8162/8172
Size
Document Number
Custom
Date:
Rev
1.0
LA-9631P
Sheet
1
37
of
60
ESD
Place Close to TL1
@
DL1
AZC099-04S.R7G_SOT23-6
1
4
I/O1
I/O3
MDI1+
Reserve gas tube for EMI go rural solution

MDI0+
DL1
1'S PN:SC300001G00
2'S PN:SC300002E00
MDI0-
GND
VDD
I/O2
I/O4
For EMI
MDI1RL14
1
CL30
1
2
CHASSIS1_GND
75_0805_5%
10P_0603_50V
TL1
<37> MDI0+
<37> MDI0-
For EMI
<37> MDI1+
<37> MDI1-
CL31
0.01U_0402_16V7K
1
2
3
4
5
6
7
8
MDI0+
MDI0-
MDI1+
MDI1-
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
DLL1
BS4200N-C-LV_SMB-F2
GAS@
MDO0+
MDO0MCT
Place Close to TL1
MCT
MDO1+
MDO1-
For EMI
MHPC_NS681612A
JLAN1
MDO0+
MDO0-
MDO1+
MCT
MCT
MDO1-
MCT
MCT
CL63 1
2 0.1U_0603_50V7K
CL61 1
2 0.1U_0603_50V7K
CL64 1
2 0.1U_0603_50V7K
CL65 1
2 0.1U_0603_50V7K
ESD
PR1+
CHASSIS1_GND
B
PR1PR2+
PR3+
PR3PR2PR4+
GND
GND
9
10
PR4SANTA_130456-121
CHASSIS1_GND
ME@
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
B
Date:
LAN_Transformer
Document Number
Rev
1.0
LA-9631P
Sheet
1
38
of
60
2 Channel
+3VGS
C329
.1U_0402_16V7K
@
SMSC thermal sensor

placed near PCH
1
Lenovo
U9
<24> REMOTE1+
1
C587
2200P_0402_50V7K
<24> REMOTE1-
REMOTE1+
REMOTE1-
+3VGS
1 R335
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2 <15,24,42>
EC_SMB_DA2 <15,24,42>
6
5
4.7K_0402_5%
@
EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
H_3P8
H_3P3
H_3P3
H_2P8
@
FD3
@
FD4
H_3P8
@
FD2
H_3P8
@
FD1
H5
HOLEA
@
H18
HOLEA
H4
HOLEA
HDD
VGA_R
VGA_L
@
H3
HOLEA
CPU
@
H2
HOLEA
@
H1
HOLEA
FAN1 Conn
C
+5VS
@
H8
HOLEA
H_2P8
H_2P8
H_2P8
@
H10
HOLEA
R
@
H11
HOLEA
H_2P8
H_2P8
@
H17
HOLEA
@
H16
HOLEA
ACES_85205-04001
ME@
@
H7
HOLEA
C591
10U_0603_6.3V6M
@
H6
HOLEA
1
2
3
4
G5
G6
1
2
3
4
5
6
<42> EC_TACH
0_0603_5%<42> EC_FAN_PWM
JFAN1
R581
Issued Date
Deciphered Date
2012/07/11
Title
Fintek-Thermal IC/FAN/screw
Custom
4
Rev
1.0
LA-9631P
Date: Wednesday, February 27, 2013
M/B
Compal Secret Data

2011/06/15
M/B
2P8 * 9 pcd
H_3P0N
H_2P5X3P5N
Sheet
1
39
of
60
SATA HDD Conn.

Near Connector
0.01U_0402_16V7K
0.01U_0402_16V7K
<14> SATA_ITX_C_DRX_P0
<14> SATA_ITX_C_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
<14> SATA_DTX_C_IRX_N0
<14> SATA_DTX_C_IRX_P0
2
2
C596 1
C597 1
JHDD1
1 C184
1 C185
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
1
2
3
4
5
6
7
GND
RX+
RXGND
TXTX+
GND
1
R551
+3VS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
+3V_HDD
0_0805_5%
@
1
R550
+5VS
2
+5V_HDD
0_0805_5%
@
Near HDD
+5VS
@
C598
1000P_0402_50V7K
1
C599
.1U_0402_16V7K
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
GND
GND
23
24
SUYIN_127043FB022G278ZR
C602
10U_0603_6.3V6M
ODD Power Control

2
J9
1
+5VALW
FOR 15"
+5V_ODD
SATA ODD FFC Conn.
JUMP_43X79
+5VS
Place CAP in Sub BD

D
<14> SATA_ITX_C_DRX_P2
<14> SATA_ITX_C_DRX_N2
<14> SATA_DTX_C_IRX_N2
<14> SATA_DTX_C_IRX_P2
OUT
IN
<19> ODD_EN
2
GND
SATA_ITX_C_DRX_P2
SATA_ITX_C_DRX_N2
R401 1 15@
R402 1 15@
2 0_0402_5%
2 0_0402_5%
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
R403 1 15@
R404 1 15@
2 0_0402_5%
2 0_0402_5%
1
R710
@
R675
100K_0402_5%
1
2
R568
10K_0402_5%
@
JODD2
DVT
Q99
LP2301ALT1G_SOT23-3
@
C607
0.01U_0402_16V7K
@
C608
10U_0603_6.3V6M
<42> ODD_DA#
+3VS
1
2
3
4
5
6
7
8
9
10
SATA_ITX_DRX_P2_15
SATA_ITX_DRX_N2_15
SATA_DTX_IRX_N2_15
SATA_DTX_IRX_P2_15
2
ODD_DETECT#
0_0402_5%
+5V_ODD
ODD_DA#
1
2
3
4
5
6
7
8
9
10
GND
GND
@
1
R555 2
10K_0402_5%
11
12
HB_A051020-SAHR21
ME@
Q100
DTC124EKAT146_SC59-3
@
Co-lay
FOR 14"
SATA ODD Conn.

JODD1
Near Connector
SATA_ITX_C_DRX_P2 14@ C616 1
SATA_ITX_C_DRX_N2 14@ C615 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_ITX_DRX_P2_14
SATA_ITX_DRX_N2_14
SATA_DTX_C_IRX_N2 14@ C614 1

SATA_DTX_C_IRX_P2 14@ C613 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_IRX_N2_14
SATA_DTX_IRX_P2_14
1
2
3
4
5
6
7
ODD_DETECT#
+5V_ODD
ODD_DA#
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
GND
GND
15
14
ALLTO_C18518-11305-L
ME@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title

HDD/ODD/BT Connector
Custom
Date:

G
Rev
1.0
LA-9631P
Sheet
40
of
H
60
CX20751
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
Sense resistors must be

connected same power
that is used for VAUX_3.3
1
RA5
2 5.11K_0402_1%
RA6
2
Lenovo
JSENSE
+VREF_1V65
CA3 vendor suggest

change to 2.2U
1
2 20K_0402_1%
2 39.2K_0402_1%
1
1
RA7
RA8
+3VS
mount RA6 on the Jack Sense circuit

to configure Port-C for mono MIC.
10K_0402_1%
Don't support LINE_IN function

RA7 could be @
PLUG_IN
For Universal jack

D
+3VS
.1U_0402_16V7K
CA3
2 0_0402_5%
2.2U_0603_6.3V4Z
CA4
CA1
1U_0603_10V4Z
CA2
RA2
CA6
+3V_PCH
+3V_AVDD_HP
4.7U_0603_6.3V6K
2 0_0402_5%
CA5
.1U_0402_16V7K
+3VLP
.1U_0402_16V7K
+LDO_OUT_3.3V
RA1
AVDD_3.3 pinis output of

internal LDO. NOT connect
to external supply.
CA10
UA1
17
15
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CA23
.1U_0402_16V7K
CA22
CA19
.1U_0402_16V7K
CA21
CA20
.1U_0402_16V7K
CA18
4.7U_0603_6.3V6K
32
33
30
31
25
26
22
23
MICB_L
MICB_R
APPLE_MIC
NOKIA_MIC
HGNDA
HGNDB
HP_L
HP_R
Lenovo
Universal Jack
External MIC
MICB_L
RA17 1
2 100_0402_1%
MICB_R
RA18 1
2 100_0402_1%
RA20 1
2 3K_0402_5%
RA19 1
2 3K_0402_5%
+MICBIASB
RIGHT+
RIGHT-
21
19
20
1
CA29
2
1U_0603_10V4Z
CX20751-11Z_QFN40
41
wide 20MIL
1
2
CA37 .1U_0402_16V7K
1
2
CA45 .1U_0402_16V7K
<42> BEEP#
RA492
1
2
33_0402_5%
CA36
1
2
2.2U_0402_6.3V6M
CA46
1
2
2.2U_0402_6.3V6M
HP_L
HP_R
ESD
AVEE
FLY_P
FLY_N
<14> HDA_SPKR
SINGA_2SJ2352-000131F
ME@
HPOUT_L
HPOUT_L
HPOUT_R
HPOUT_R
HGNDB
HGNDB
HGNDA
HGNDA
PC_BEEP
SPK_R1SPK_R2+
SPK_L1SPK_L2+
Place colose to Codec chip
LA3
0_0603_5%
LA2
0_0603_5%
@
DA1
@
DA2
@
LA4
0_0603_5%
@
JSPK1
LA1
LA2
LA3
LA4
1
1
1
1
2
2
2
2
FCM1608CF-121T03
FCM1608CF-121T03
FCM1608CF-121T03
FCM1608CF-121T03
0603
0603
0603
0603
1
2
3
4
5
6
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
MIC1
CA41
For EMI
1U_0603_10V4Z
2
ME@
DA3
SPK_R1-_CONN
SPK_R2+_CONN
I/O4
I/O2
VDD
GND
I/O3
I/O1
SPK_L2+_CONN
ACES_85205-04001
2
A
SPK_L1-_CONN
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Custom
CX20751 Codec
Rev
1.0
LA-9631P
Date: Tuesday, March 05, 2013
1
2
3
4
G5
G6
+5VS
ESD
MIC_IN
CA44
.1U_0402_16V7K
WM-64PCY_2P
@
MIC_IN_C
GNDA
1
CA42
.1U_0402_16V7K
1
2
1000P_0402_50V7K
CA38
RA23
2.2K_0402_5%
1000P_0402_50V7K
CA43
For EMI
+MICBIASC
1000P_0402_50V7K
CA40
@
RA22
10K_0402_5%
1000P_0402_50V7K
CA39
ICH Beep
Headphone
LA1
0_0603_5%
EC Beep
PLUG_IN
For EMI
Lenovo
4
3
1
2
For Universal jack
+MICBIASB
+MICBIASC
LEFT+
LEFT-
PC Beep
HGNDB
HGNDA
HPOUT_L
HPOUT_R
SPK_R2+
SPK_R1-
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M
Internal SPEAKER
CA28 1
CA27 1
2 .1U_0402_16V7K
12
14
2 100_0402_1%
2 100_0402_1%
2 15_0402_5%
2 15_0402_5%
AZ5125-02S.R7G_SOT23-3
CA66 1
SPK_L2+
SPK_L1-
1
1
1
1
2 .1U_0402_16V7K
MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L
GPIO1/PORTC_R_MIC
PORTA_R
RA16
RA12
RA13
RA14
2 .1U_0402_16V7K
CA65 1
PORTD_A_MIC
PORTD_B_MIC
DMIC_DAT/GPIO1
HGNDA
DMIC_CLK / MUSIC_REQ/GPIO0
HGNDB
JHP1
APPLE_MIC
NOKIA_MIC
HP_L
HP_R
Please bypass caps very close to device.
JSENSE
34
35
GND
CA64 1
36
37
MIC_IN
PORTB_L_LINE
PORTB_R_LINE
Combo Jack
(Normal Open)
HGNDA, HGNDB 80mils
Internal analog MIC
PC_BEEP
SPKR_MUTE#
For EMI
AZ5125-02S.R7G_SOT23-3
For EMI
MICBIASB
MICBIASC
38
100P_0402_50V8J
1
40
JSENSE
100P_0402_50V8J
CA34
2
1
10
39
PC_BEEP
<42> EC_MUTE#
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
100P_0402_50V8J
CA33
2
1
HDA_SDOUT_AUDIO
LPWR_5.0
RPWR_5.0
CLASS-D_REF
13
16
11
CA31
2
1
2 33_0402_5%
RESET#
100P_0402_50V8J
CA32
2
1
5
8
6
4
For Layout
CA30
RA9
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
For Layout
2.2U_0603_6.3V4Z
<14> HDA_BITCLK_AUDIO
<14> HDA_SYNC_AUDIO
<14> HDA_SDIN0
<14> HDA_SDOUT_AUDIO
HDA_RST_AUDIO#
CA35
<14> HDA_RST_AUDIO#
+5VS
CA26
22P_0402_50V8J 33_0402_5%
29
@
1 RA21
.1U_0402_16V7K
@
CA11
.1U_0402_16V7K
.1U_0402_16V7K
@
CA7
27
28
24
HDA_RST_AUDIO#
.1U_0402_16V7K
CA15
10 mils
For EMI
1U_0603_10V4Z
CA9
.1U_0402_16V7K
+5VS
+LDO_1.8V
AVDD_3.3
AVDD_5V
AVDD_HP
Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low
resistance (<0.01 ohms)
VREF_1.65V
3
7
2
18
@
RA15
4.7K_0402_5%
FILT_1.8
VDD_IO
VDDO_3.3
DVDD_3.3
2 0_0402_5%
.1U_0402_16V7K
4.7U_0603_6.3V6K
CA25
2 0_0402_5%
CA24
.1U_0402_16V7K
+3V_PCH
RA4
CA17
+3VS
+3VS
CA16
ESD
RA3
@
4.7U_0603_6.3V6K
CA8
Should be same supply rail as used for

@
PCH HDA bus controller section
1U_0603_10V4Z
+3VS
Sheet
1
41
of
60
+3VLP
1@
C535
100P_0402_50V8J
0_0603_5%
KSO[0..15]
C47
22P_0402_50V8J
<43> KSO[0..15]
KSI[0..7]
<43> KSI[0..7]
ESD
+3V_EC
R600
2
EC_SMB_CK1
2.2K_0402_5%
R604
2
EC_SMB_DA1
2.2K_0402_5%
EC_SMB_DA2
EC_SMB_CK2
@
C665
100P_0402_50V8J
@
C666
100P_0402_50V8J
+3VALW
<43> KSO16
<43> KSO17
<47,48>
<47,48>
<15,24,39>
<15,24,39>
<53> EC_VGA_EN
<40> ODD_DA#
<46> ADP_ID_CLOSE
<39> EC_TACH
<37> LAN_WAKE#
<36,43> EC_TX
<36,43> EC_RX
<16> PCH_PWROK
<43> NOVO#
R608 1
100K_0402_5%
@
Share ROM
EC_TACH
LAN_WAKE#
EC_TX
EC_RX
PCH_PWROK
NOVO#
NUM_LED#: NC
122
123
<16> SUSCLK
<18,25,51,53> DGPU_PWR_EN
ODD_DA#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
@
R740
100K_0402_5%
@
C93
20P_0402_50V8
63
64
65
66
75
76
BATT_TEMP
68
70
71
72
ADP_90
V AD_BID typ
0 V
0.354V
0.430V
0.550V
VAD_BID max
0 V
0.360V
0.438V
0.559V
ADP_65 <47>
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
SPI Flash ROM
GPIO
GPIO
MP
PVT
DVT
EVT
+3VALW
BEEP# <41>
EC_FAN_PWM <39>
ACOFF <48>
BATT_TEMP <46,47>
GPU_IMON <53>
@
R694
100K_0402_1%
+5VALW
ADP_I <47,48>
ADP_ID
BRDID
ADP_ID <46>
BRDID
ENBKL <17>
83
84
85
86
87
88
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
USB_ON#
ADP_135
SYS_PWROK_R
TP_CLK
TP_DATA
EC_TS_ON#
119
120
126
128
EC_SPI_SO
EC_SPI_SI
EC_SPI_CLK
EC_SPI_CS#
R417 1
@
1 R593
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
100
101
102
103
104
105
106
107
108
10K_0402_5%
2 0_0402_5%
R695
PVT2@
20K_0402_1%
R695
PVT@
12K_0402_1%
R695
DVT@
15K_0402_1%
+5VS
EC_MUTE# <41>
USB_ON# <44>
ADP_135 <47>
SYS_PWROK <16>
TP_CLK <43>
TP_DATA <43>
+5VS
R603 1
2 4.7K_0402_5%
R598 1
2 4.7K_0402_5%
TP_CLK
EC_TS_ON# <44>
TP_DATA
ME_FLASH <14>
NTC_V <47>
BATT_TEMP
EC_SPI_SO <14>
EC_SPI_SI <14>
EC_SPI_CLK <14>
EC_SPI_CS# <14>
ACIN
1
C663
1
C664
1
R522
2
100P_0402_50V8J
2
100P_0402_50V8J
2
@ 4.7K_0402_5%
IMVP_IMON <54>
VGATE <16,54>
LAN_PWR_ON# <37>
BATT_CHG_LED# <43>
BATT_CHG_LED#
CAPS_LED#
CAPS_LED# <43>
PWR_LED# <43>
BATT_LOW_LED# <43>
SYSON <50>
VR_ON <54>
PM_SLP_S4# <16>
BATT_LOW_LED#
SYSON
H_PROCHOT# <46,47,54,6>
EC_RSMRST# <16>
EC_LID_OUT# <19>
EC_LID_OUT#
Turbo_V
R738 1
MAINPWON_R
BKOFF#
PBTN_OUT#
PCH_PWR_EN
110
112
114
115
116
117
118
LID_SW#
SUSP#
NUVOTON_VTT
PECI_KB9012
124
+V18R
KB9012QF A3 LQFP 128P_14X14
R695
100K_0402_1%
10K_0402_5%
+3VALW
97
98
99
109
73
74
89
90
91
92
93
95
121
127
USB_ON# 1
ADP_90 <47>
SPI Device Interface
Bus
EC AD
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
ADP_65
BEEP#
EC_FAN_PWM
ACOFF
EC_MUTE#
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
ECAGND
EC_TACH
10K_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
EC_SMI#
R605
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#
21
23
26
27
15K +/- 1%
20K +/- 1%
VAD_BID min
0 V
0.347V
0.423V
0.541V
R594
GND/GND
GND/GND
GND/GND
GND/GND
GND0
+3VS
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
11
24
35
94
113
<16>
<16>
<16,19>
<33>
77
78
79
80
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PWM Output
LAN_WAKE#
10K_0402_5%
2
R606
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
12K +/- 1%
Board ID / SKU ID Table for AD channel
<19> EC_SCI#
<47> BATT_LEN#
C661
.1U_0402_16V7K
EC_RST#
EC_SCI#
BATT_LEN#
12
13
37
20
38
<18> CLK_PCI_EC
<18,23,36,37> PLT_RST#
2
47K_0402_5%
2
1
R590
+3V_EC
10_0402_5%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
AGND/AGND
2
1
2
1
@ C660 22P_0402_50V8J @ R589
<19> GATEA20
<19> KBRST#
<14> SERIRQ
<14> LPC_FRAME#
<14> LPC_AD3
<14> LPC_AD2
<14> LPC_AD1
<14> LPC_AD0
R695
0
2 0_0402_5%
R669
2
43_0402_1%
C493
47P_0402_50V8J
+3VALW
ACIN <16,24,46,48>
EC_ON <49>
ON/OFF <43>
LID_SW# <43>
SUSP# <45,50,52>
2
G
Q37
2N7002H_SOT23-3
PROCHOT
BKOFF# <33>
PBTN_OUT# <16>
PCH_PWR_EN <20>
SA_PGOOD <51>
ACIN
EC_ON
Turbo_V <47>
PROCHOT <47>
MAINPWON <49>
LID_SW#
1 R618
2
100K_0402_5%
H_PECI <6>
+V1.05S_VCCP
NUVOTON_VTT
R410 1
2 0_0402_5%
EMC Request
SYSON
.1U_0402_16V7K
C492
ECAGND
U31
C667
4.7U_0603_6.3V6K
67
EC_VDD/AVCC
69
0
1
2
3
+EC_VCCA
9
22
33
96
111
125
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
1000P_0402_50V7K
C658
1000P_0402_50V7K
C659
C662
1000P_0402_50V7K
C656
.1U_0402_16V7K
2 ECAGND
2
L45
FBM-11-160808-601-T_0603
+EC_VCCA
C654
.1U_0402_16V7K
C653
.1U_0402_16V7K
+3V_EC
100K +/- 1%
Board ID
L44
FBM-11-160808-601-T_0603
1
2
1
3.3V
Vcc
R694
@ R416
1
+3V_EC
2
0_0603_5%
@
R304
+3VALW
SA00004OB30
S IC KB9012QF A4 LQFP 128P KB CONTROLLER
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

BIOS & EC I/O Port
Size
Document Number
Custom
Date:
Rev
1.0
LA-9631P
Sheet
42
of
60
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
<42>
JP3
1
2
3
4
+3VALW
<36,42> EC_TX
<36,42> EC_RX
1
2
3
4
ACES_85205-0400
ME@
@
R415
100K_0402_5%
@
1 R414
2
0_0402_5%
+3VLP
+3VALW
R642
100K_0402_5%
@
2
J12
1
R701
100K_0402_5%
NOVO#
<42> NOVO#
J11
1
D26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
JKB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
31
32
GND
GND
ME@
GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88514-2401
ACES_88514-3001
2
1
SHORT PADS
<42,43> KSO16
<42,43> KSO17
+3VLP
ME@
JKB1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
<42>
NOVO_BTN#
3
ON/OFF
DAN202UT106_SC70-3
@
2
SHORT PADS
ON/OFF
ON/OFF
+3VS
<42>
For EMI
LED1 14@
<42> PWR_LED#
PWR_LED#
JCR1
2
2 14@
1
+5VALW
R623
649_0402_1%
1 R687@
1 R683@
USB20_N11
USB20_P11
<18> USB20_N11
<18> USB20_P11
1
2
3
4
2 0_0402_5% USB20_N11_R
2 0_0402_5% USB20_P11_R
19-213A-T1D-CP2Q2HY-3T_WHITE
1
2
3
4
GND
GND
L57 @
+5VS
LED2 14@
<42> BATT_LOW_LED#
@
C696
JTP1
8
7
2 R764
1
470_0402_5%
ME@
15@
2 R627
1
0_0402_5%
1
@ D15
PSOT24C_SOT23-3
TP_3
2 R619
1 14@ TP_1
0_0402_5%
USB20_N11_R
USB20_P11_R
6
5
4
3
2
1
+3VALW
14@
+3VALW
LED5 14@
<42> BATT_CHG_LED#
BATT_CHG_LED#
2
2 14@
1
+5VALW
R765
649_0402_1%
JPWRB1
<42> LID_SW#
NOVO_BTN#
ON/OFF
1
2
3
4
5
6
7
8
D24
ESD
LED6 14@
<42> CAPS_LED#
CAPS_LED#
2 14@
1
+5VS
R2
649_0402_1%
1
2
3
4
5
6
GND
GND
ACES_88058-060N
ME@
L30ESD24VC3-2 3P C/A SOT23 ESD
5
6
CVILU_CF06041H0RB-NH
ME@
GND
GND
ACES_88058-060N
Lenovo
USB20_P11
C698 @
100P_0402_50V8J
.1U_0402_16V7K
C491
.1U_0402_16V7K
C490
6
5
4
3
2
1
TP_CLK
TP_DATA
TP_3
TP_2
TP_1
@ C697
100P_0402_50V8J
WCM-2012-900T_4P
HT-191UD5_AMBER
.1U_0402_16V7K
<42> TP_CLK
<42> TP_DATA
BATT_LOW_LED#
USB20_N11
SW4
14@
SMT1-05_4P
5
6
5
6
SW5
14@
SMT1-05_4P
TP_3
1
TP_2
3
SW6
15@
SMT1-05_4P
ESD
14"
VCC
CLK
CLK
DAT
DAT
VCC
5
6
5
6
15/17"
SW7
15@
SMT1-05_4P
TP_2
GND
JLED1
+5VALW
+3VALW
+5VS
LID_SW#
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
CAPS_LED#
TP_1
GND
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
HB_A091020-SAHR21
ME@
For 15"
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

ROM/KBD/PWR/CR/LED/TP Conn.
Document Number
Rev
1.0
LA-9631P
Sheet
43
of
60
ESD
@
D27
1 U3RXDN1
U3RXDN2 9 10
1U3RXDN2
U3RXDP1 8
2 U3RXDP1
U3RXDP2 8
2U3RXDP2
U3TXDN2 7
4U3TXDN2
U3TXDP2 6
5U3TXDP2
U3TXDN1 7
4 U3TXDN1
U3TXDP1 6
5 U3TXDP1
U2DN1
D31
I/O2
D22
D30
U3RXDN1 9 10
I/O4
GND
VDD
I/O1
I/O3
U2DP2
+5VALW
U2DP1
I/O2
I/O4
GND
VDD
I/O1
I/O3
+5VALW
U2DN2
For EMI
USB3.0
Intel_PCH_USB2.0
WCM-2012HS-900T
<18> USB20_N1
<18> USB20_P1
USB2@ 3
L55
Ext. USB2.0
U2DN2
U2DP2
U3RXDN2
U3RXDP2
Touch Screen
Left Ext.USB Conn. 2
Intel_PCH_USB3.0
+5VALW
+USB3_VCCA
WCM-2012HS-900T
+USB_VCCB
<18> USB3_RX2_N
RIGHT USB PORT X1
<42,44> USB_ON#
<18> USB3_RX2_P
U36
1
2
3
4
4
L54
8
GND VOUT 7
VIN VOUT 6
VIN VOUT 5
EN
FLG
G547I2P81U_MSOP8
W=80mils
USB3@ 3
JUSB2
9
1
8
3
7
2
6
4
5
U3TXDP2
SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
U3TXDN2
U2DP2
JTS1
USB_OC4# <18>
8
7
6
5
4
3
2
1
+3VS_TS
<18> USB20_N2
<18> USB20_P2
EC_TS_ON#
R726 1
TS@ 2 0_0402_5% TS_RST#
U2DN2
U3RXDP2
GND
GND
6
5
4
3
2
1
ACES_50208-00601-P01
ME@
<18> USB3_TX2_N
<18> USB3_TX2_P
1
1
C850USB3@
.1U_0402_16V7K
2 U3TXDN2_L
WCM-2012HS-900T
U3TXDP2_L
4
L53
C848 USB3@
.1U_0402_16V7K
U3RXDN2
2
USB3@ 3
U3TXDN2
U3TXDP2
Near HDMI Conn.

USB Debug Port
Right Ext.USB Conn.

JUSB3 ME@
+USB_VCCB
USB20_N9_C
@
R503
10_0402_5%
USB20_P9
1
L66
USB20_P9_C
WCM-2012HS-900T
@
R504
10_0402_5%
@
C1
1.2P_0402_50V8C
<18> USB20_P0
<42> EC_TS_ON#
R5581 @
100K_0402_5%
2
C1331
.1U_0402_16V7K
@
C2
1.2P_0402_50V8C
L51
Q156
LP2301ALT1G_SOT23-3
@
1
1
USB20_N9
1 0_0402_5% USB20_N9_C
1 0_0402_5%
USB20_P9_C
@
@
R868 2
R869 2
USB20_N9
USB20_P9
<18> USB20_N9
@
<18> USB20_P9
C715
470P_0402_50V7K
U2DN1
U2DP1
U3RXDN1
U3RXDP1
0_0402_5%
R5583
<18> USB20_N0
WCM-2012HS-900T
6
5
4
3
2
1
ACES_88058-060N
C714
220U_6.3V_M
Intel_PCH_USB2.0
+3VS_TS
1 TS@
+3VS
GND
GND
6
5
4
3
2
1
.1U_0402_16V7K
C1322
8
7
W=80mils
+USB_VCCB
USB2@
Left Ext.USB Conn. 1
Intel_PCH_USB3.0
WCM-2012HS-900T
<18> USB3_RX1_N
TS@
<18> USB3_RX1_P
+USB3_VCCA
W=80mils
USB3@
JUSB1
U3TXDP1
L50
U3TXDN1
U2DP1
For EMI
U2DN1
U3RXDP1
<18> USB3_TX1_N
<18> USB3_TX1_P
1
1
C849USB3@
.1U_0402_16V7K
2
U3TXDN1_L
U3TXDP1_L
C847USB3@
.1U_0402_16V7K
WCM-2012HS-900T
U3RXDN1
2
3
USB3@
U3TXDN1
U3TXDP1
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
Near Audio Jack
L49
Place TX AC coupling Cap (C843~C850). Close to connector

2A/Active Low
+5VALW
+USB3_VCCA
U35
<42,44> USB_ON#
USB_ON#
1
2
3
4
W=80mils
8
GND VOUT 7
VIN VOUT 6
VIN VOUT 5
EN
FLG
G547I2P81U_MSOP8
USB_OC0# <18>
1
+
C736
220U_6.3V_M
@
C735
470P_0402_50V7K
2011/06/15
Deciphered Date
2012/07/11
Title
USB3.0/Left USB Ports
Size
Document Number
Custom
Date:
Compal Secret Data
Issued Date
Rev
1.0

1
Sheet
44
of
60
+5VALW to +5VS
+5VALW
+3VALW to +3VS
+5VS
+3VALW
+3VS
2@
@
C725
1U_0603_10V4Z
B+
R647
470K_0402_1%
2 SUSP
G
Q108
2N7002H_SOT23-3
@
2
D
2
G
DVT
R650
Q111
0_0402_5%
2N7002H_SOT23-3
@
C727
2200P_0402_25V7K
SUSP
DVT
C726
2200P_0402_25V7K
82K_0402_5%
Q110
2N7002H_SOT23-3
15VS_GATE_R
1
5VS_GATE2 R649
D
2
G
SUSP
R646
150K_0402_5%
R645
470_0603_5%
@
2 SUSP
G
Q107
2N7002H_SOT23-3
@
C724
C723
1 2
1 2
B+
R644
470_0603_5%
@
4.7U_0603_6.3V6K
@
C722
1U_0603_10V4Z
C721
U39
8
1
7
2
6
3
5
4.7U_0603_6.3V6K
8
1
7
2
6
3
5
4.7U_0603_6.3V6K
C720
4.7U_0603_6.3V6K
U38
+1.5V to +1.5VS
+0.75VS
C719
1U_0603_10V4Z
+3VALW
+3VLP
Q112
0_0402_5%
@
1.5VS_GATE
@
R653
220K_0402_5%
OUT
Q117
DTC124EKAT146_SC59-3
SUSP
<10> SUSP
R652
220K_0402_5%
SUSP# 2
G
2N7002H_SOT23-3
+RTCVCC
2 SUSP
G
Q109
2N7002H_SOT23-3
@
C729
100K_0402_5%
R648
R651
1
2
.1U_0402_16V7K
R643
470_0603_5%
@
DVT
C718
4.7U_0603_6.3V6K
2
SUSP
G
Q115
2N7002H_SOT23-3
C717
1 2
S
2 SUSP
G
Q116
2N7002H_SOT23-3
@
3
1
R658
22_0603_5%
+1.5VS
Q8
LP2301ALT1G_SOT23-3
D
R659
470_0603_5%
@
4.7U_0603_6.3V6K
+1.5V
1 2
+V1.05S_VCCP
IN
GND
<42,50,52> SUSP#
R1110 @
100K_0402_5%
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
Custom
Date:
DC Interface
Rev
1.0
LA-9631P
Sheet
E
45
of
60
VIN
PF101
7A_24VDC_429007.WRML
PL101
SMB3025500YA_2P
1
2
JDCIN1
1
APDIN
PQ102A
2N7002KDW-2N_SOT363-6
1
PC108
0.1U_0402_16V7K
2
1
750_0402_1%
PR110
VIN
1000P_0402_50V7K
PC104
2
1
PC103
2
1
100P_0402_50V8J
PC102
2
1
ADP_ID_CLOSE <42>
PQ102B
1
PR111
100K_0402_1%
2N7002KDW-2N_SOT363-6
100K_0402_1%
ADP_ID <42>
+3VALW
PC109
680P_0402_50V7K
PR102
1
100P_0402_50V8J
ACES_50312-00541-001
@
2 APDIN1
PC101
2
1
1
2
3
4
5
1000P_0402_50V7K
1
2
3
4
5
2
PR108
10K_0402_1%
1
2
PR109
1
8
P
+
-
0.022U_0402_16V7K
5
6
ACIN <16,24,42,48>
PU101B
AS393MTR-E1 SO 8P OP
1.5M_0402_5%
PR105
1
1N4148WS-7-F_SOD323-2
2
1
PC106
2
1
47K_0402_1%
2
PR107
1
@
@
100K_0402_1%
P
G
+5VS
BATT_TEMP <42,47>
H_PROCHOT#
3
2
0.022U_0402_16V7K
ACES_50271-0020N-001
PC107
100P_0402_50V8J
2
1
PR106
1
@
PU101A
PQ101B
RTC Battery
JRTC1 @
1
2 1
3 2
4 GND
GND
PD104
PR101
1K_0603_5%
1
2
1.5M_0402_5%
+3VALW
@ PC105
2
1
PR104
+3VLP
+CHGRTC_R
2N7002KDW-2N_SOT363-6
4
3
PD101
S SCH DIO BAS40CW SOT-323
2
1
+RTCBATT
3
PR103
1K_0603_5%
1
2
1N4148WS-7-F_SOD323-2
PD105
2
1
+CHGRTC
PQ101A
2N7002KDW-2N_SOT363-6
<42,47,54,6> H_PROCHOT#
47K_0402_1%
+5VS
@
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PWR DCIN / RTC Battery
Custom
Rev
1.0
Gx00
Date:
Sheet
1
46
of
60
PF201
12A_65V_451012MRL
2
PL201
SMB3025500YA_2P
1
2
BATT+
15"
JBATT2 --->
14"
90W(DIS) : 6.65K 100W active 90W recovery

65W(UMA): 1.65K 70W active 65W recovery
PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
20120314
Change to +EC_VCCA from +3VLP
1
PC203
0.01U_0402_25V7K
D
<42,48> ADP_I
VL
6 1
2
1
PR228
5.9K_0402_1%
1
4
+3VLP
1.5M_0402_5%
PD201
PR205
PC207
100P_0402_50V8J
1N4148WS-7-F_SOD323-2
PU201A
1
2
PQ202B
2N7002KDW-2N_SOT363-6
2
PR213
100K_0402_1%
BATT_OUT <48>
ECAGND
PC208
0.068U_0402_16V7K~N
1
O
-
PQ202A
2N7002KDW-2N_SOT363-6
<42> ADP_135
2
1
<42,46,47> BATT_TEMP
100K_0402_1%
100K_0402_1%
PR210
47K_0402_1%
2
G
PR214
2
1
0.01U_0402_25V7K
PR202
75K_0402_1%
2
G
PR211
<42> ADP_90
PC202
1
2
+3VALW
VL
PR221
8.45K_0402_1%
D
2
G
<42> ADP_65
<42,47> PROCHOT
PR222
100K_0402_1%
PQ207
2N7002KW_SOT323-3
PR216
0_0402_5%
2
@
1
<42,47> PROCHOT
A/D
BATT_TEMP <42,46,47>
1
2
PR207
10K_0402_5%
2N7002KW_SOT323-3
PQ208
2N7002KW_SOT323-3
+3VALW
PR227
9.31K_0402_1%
<42> NTC_V
PR229
100K_0402_1%
1
2
PR206
6.49K_0402_1%
ADP_OCP_1
2
G
PQ201
PR225
PQ206
25.5K_0402_1%
2N7002KW_SOT323-3
<42> Turbo_V
+3VLP
PR215
<42,46,54,6> H_PROCHOT#
@
1
2
PR209
6.49K_0402_1%
SUYIN_200082GR007M229ZR
1
2
3
4
5
6
7
GND
GND
@
1
2
3
4
5
6
7
8
9
EC_SMB_DA1 <42,48>
JBATT2
100K_0402_1%
EC_SMB_CK1 <42,48>
+EC_VCCA
+3VS
PC201
1000P_0402_50V7K
2
1
PR204
100_0402_1%
EC_SMCA
EC_SMDA
JBATT1 --->
PH201
100K_0402_1%_TSM0B104F4251RZ
2
1
PR201
100_0402_1%
SUYIN_200082GR007M229ZR
VMB
@
JBATT1
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
PR226
12.7K_0402_1%
VMB2
PR220
B
@ PR223
1.5M_0402_5%
2
G
PQ205
2N7002KW_SOT323-3
@
PQ209
2N7002KW_SOT323-3
1N4148WS-7-F_SOD323-2
PD203
@ PC210
0.068U_0402_16V7K~N
PU201B
2
G
1
O
-
@ PC213
100P_0402_50V8J
2
1
2
1
@ PR217
100K_0402_1%
@ PR218
47K_0402_1%
2
1
@ PR208
75K_0402_1%
<42> BATT_LEN#
100K_0402_1%
VL
+3V_LDO
VMB
@ PU202
IN
OUT
+3V_LDO
SHDN#
GND
BYP
G9191-330T1U_SOT23-5
@
PC209
4.7U_0402_6.3V6M
@ PC212
22U_0603_6.3V6M
2
1
+5VALW
Compal Secret Data
@ PC211
1U_0402_16V6K
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PWR-BATTERY CONN/OTP
Custom
Rev
1.0
Gx00-CR
Date:
Sheet
1
47
of
60
B+
P3
P2
PQ301
AO4407AL_SO8
PQ302
AO4423L_SO8
PR301
0.01_1206_1%
CHG_B+
1
2
3
PC319
2200P_0402_50V7K
PC316
10U_0805_25V6K
DISCHG_G
VIN
2ACOFF-1
1SS355_SOD323-2
1
2
GND
SRP
17
PD301
REGN
16
4
1
3
2
1
15
14
13
2
1
PR318
10_0402_5%
11
6.8_0402_5%
1
12
PR317
2
RB751V-40_SOD323-2
PC312
1U_0603_25V6K
BQ24737VDD
PC324
0.1U_0402_25V6
2
1
1
PR320
PC317
2.2_0603_5%
0.047U_0603_16V7K
1
2
2
1
BST_CHG
2
G
PACIN
CHG1
SRP
BATT+
SRN
PC322
10U_0805_25V6K
2
1
BTST
PQ309
S TR MDS1525URH 1N SO8
5
6
7
8
PR319
10_1206_5%
2
ILIM
DH_CHG
2N7002KW _SOT323-3
PL302
PR324
10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%
LX_CHG
18
SCL
SRN
PR316
100K_0402_1%
ACN
2
ACP
3
CMPOUT
CMPIN
HIDRV
1U_0603_25V6K
19
PR323
4.7_1206_5%
+3VALW
10
PHASE
PU301
SDA
BQ24727RGRR_VQFN20_3P5X3P5
124737_SN
2
PR315
316K_0402_1%
1
2
IOUT
BM
<42,47> EC_SMB_CK1
VCC
BQ24737VCC
PC320
680P_0603_50V7K
<42,47> EC_SMB_DA1
PC314
20
PQ310
S TR MDS1521URH 1N SO8
100P_0402_50V8J
8
21
3
2
1
0.1U_0402_25V6
TP
5
6
7
8
PC304
1
2
ACDET
PQ313
P2
LODRV
PC303
1
2
3
1
3
ACOK
<42,47> ADP_I
6
392K_0402_1%
1
PR309
2
PR308
64.9K_0402_1%
1
2
2N7002KW_SOT323-3
<47,48> BATT_OUT
PD303
1SS355_SOD323-2
VIN
PR326
10K_0402_5%
PQ314
0.1U_0402_25V6
2
PR325
200K_0402_1%
PC308
2ACOFF-12
2
G
0.1U_0402_25V6
<42> ACOFF
1
PQ305
DTC115EUA_SC70-3
ACON
PR305
150K_0402_1%
2
P2-2
3
4
PQ306
2N7002KW _SOT323-3
2
BATT_OUT <47,48>
G
2N7002KDW-2N_SOT363-6
PR303
47K_0402_1%
1
2
PACIN
PACIN
PQ307B
1 2
3
6
1
<48> ACPRN
PR306
20K_0402_1%
PQ311
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PC311
PD302
1DISCHG_G-1
1
PC307
0.1U_0402_25V6
P2-1
PR321
47K_0402_1%
ACN
PQ307A
2N7002KDW -2N_SOT363-6
PR322
200K_0402_1%
1
2
ACP
PQ303
8
7
6
5
PC323
10U_0805_25V6K
2
1
PC301
5600P_0402_25V7K
2
1
PC302
0.1U_0603_25V7K
2
1
PR304
200K_0402_1%
1
PR302
47K_0402_5%
2
DTA144EUA_SC70-3
PQ304
PQ312
AO4407AL_SO8
PL301
1UH_PCMB061H-1R0MS_7A_20%
PC315
10U_0805_25V6K
1
2
PC313
@ 10U_0805_25V6K
8
7
6
5
PC310
@ 10U_0805_25V6K
1
2
3
1
2
3
8
7
6
5
VIN
DL_CHG
PC306
2
1
1
PC305
0.1U_0402_25V6
0.1U_0402_25V6
PC309
0.1U_0402_25V6
PR314
10K_0402_1%
1
2
BQ24737VDD
PR310
10K_0402_1%
3
A
1
S
PR312
2
2
G
2N7002KW_SOT323-3
PQ308
ACPRN <48>
ACIN <16,24,42,46>
PACIN
PR307
47K_0402_1%
12K_0402_1%
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
Size
Date:
CHARGER
Document Number
Rev
1.0
Gx00-CR
Sheet
W ednesday, February 27, 2013

1
48
of
60
PR411
1
3V5V_EN_R
3V5V_EN
PC432
0.047U_0402_25V7K
10K_0402_5%
PR414
0_0402_5%
@ PR415
2
0_0402_5%
3V5V_EN_R
PC439
1
2
3
1
PR401
0_0603_5%
+3VLP
PC414
4.7U_0603_6.3V6M
1 ENLDO_3V5V
S IC SY8208BQNC QFN 10P PWM
5V_VIN
PC418
0.1U_0402_25V6
2
1
PC421
0.1U_0603_25V7K
1
2
PR405
0_0603_5%
PC430
4.7U_0603_6.3V6M
PR407
2.2K_0402_5%
2
1
2@
PC438
470P_0402_50V8J
VL
S IC SY8208CQNC QFN 10P PWM
PC437
470P_0402_50V8J
2
1
+5VALWP
LDO
PG
1.5UH_PCMC063T-1R5MN_9A_20%
4.7_1206_5%
OUT
PL404
1
LX_5V
PR406
2
5V_SN
VCC
10
PC429
2
1
LX
680P_0603_50V7K
PC422
4.7U_0603_6.3V6M
1
2
3
GND
PC433
150U_D2_6.3VY_R15M
BST_5V
PC428
22U_0805_6.3V6M
PC427
22U_0805_6.3V6M
2
1
3V5V_EN
PC426
22U_0805_6.3V6M
2
1
BS
PC425
22U_0805_6.3V6M
2
1
EN1
PC424
22U_0805_6.3V6M
2
1
IN
EN2
5V_VCC
EC_ON
1K_0402_5%
PU402
8
<42> EC_ON
PR413
2
6800P_0402_25V7K
PC417
2200P_0402_50V7K
2
1
PC416
10U_0805_25V6K
2
1
PC420
10U_0805_25V6K
2
1
PC419
68P_0402_50V8J
2
1
PC436
1
2
PC423
22U_0805_6.3V6M
2
1
PL403
HCB2012KF-121T50_0805
1
2
B+
@
PR412
0_0402_5%
PC435
470P_0402_50V8J
LDO
+3VALWP
PC434
470P_0402_50V8J
2
1
PG
1.5UH_PCMC063T-1R5MN_9A_20%
PC413
22U_0805_6.3V6M
2
1
OUT
PC412
22U_0805_6.3V6M
2
1
SPOK
GND
PL402
1
LX_3V
1K_0402_5%
0.1U_0603_25V7K
10
LX
0.01U_0402_25V7K
PC411
22U_0805_6.3V6M
2
1
BST_3V 2
PR416
2
PC410
22U_0805_6.3V6M
2
1
PC402
1
2
PC409
22U_0805_6.3V6M
2
1
BS
EN2
EN1
IN
PC408
22U_0805_6.3V6M
2
1
IN
PC415
PR404
2
1 3V_SN
2
PC406
10U_0805_25V6K
2
1
PC405
10U_0805_25V6K
2
1
PC404
2200P_0402_50V7K
2
1
PC403
0.1U_0402_25V6
2
1
3V_VIN
680P_0603_50V7K
4.7_1206_5%
PL401
HCB2012KF-121T50_0805
1
2
PC401
68P_0402_50V8J
2
1
B+
PU401
B+
PC407
1U_0603_25V6K
2
1
1 ENLDO_3V5V
PR403
150K_0402_1%
2
1
PR402
499K_0402_1%
2
1
@ PJ401
1
+3VALWP
+3VALW
JUMP_43X118
MAINPWON
<42> MAINPWON
PR408
0_0402_5%
@ PJ402
1
2
PR409
1M_0402_1%
+5VALWP
PC431
4.7U_0402_6.3V6M
3V5V_EN
+5VALW
JUMP_43X118
Compal Secret Data
2011/06/15
Issued Date
2012/07/11
Deciphered Date
Title

+1.05VS_VCCP
Custom
Rev
1.0
Gx00-CR
Date:
Sheet
E
49
of
60
PL502
1
2
HCB2012KF-121T50_0805
UG_1.5V
Lo
Lo
Off
Off
Off
1
S4/S5
1
16
LG_1.5V
3
2
1
PR511
6.65K_0402_1%
2
1
PC513
2200P_0402_50V7K
PR515
4.7_1206_5%
@
PC517
680P_0603_50V7K
PC521
PC522
330U_2.5V_M 2
2 220U_6.3V_M
12
11
2
1
PR514
5.1_0603_5%
1
2
1
PR510
10K_0402_5%
+3VALW
+5VALW
+1.5VP
OCP min 20A
OVP min 1.65V
PC511
1U_0603_10V6K
PHASE
PGOOD
VDD
13
10
S5
PGOOD_1.5V
PR507
5.9K_0402_1%
2
1
1
JUMP_43X118
PJ505
@ PC508
0.1U_0402_16V7K
PJ504
2
+1.5VP
PR509
887K_0402_1%
2
1 1.5V_B+
PR505
0_0402_5%
PL501
1UH_PCMB104T-1R0MH_18A_20%
2
1
14
S5_1.5V
S3_1.5V
S3
FB
TON
VDDQ
6
1
17
BOOT
VDDP
PR502
64.9K_0402_1%
1
2
<42> SYSON
UGATE
18
19
VTTREF
CS
RT8207MZQW _W QFN20_3X3
PC506
0.033U_0402_16V7K
PGND
15
PC510
1U_0603_10V6K
2
1
GND
PC503
0.1U_0402_16V6K
LGATE
VTTSNS
+1.5VP
VLDOIN
VTTGND
20
PAD
+VTT_REFP
VTT
PC505
10U_0805_25V6K
PC504
10U_0805_25V6K
PU501
21
<42,45,50,52> SUSP#
B+
PR501
PC512
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2
BST_1.5V
+0.75VSP
3
2
1
LX_1.5V
PR503
0_0603_5%
Note: S3 - sleep ; S5 - power off
PC509
0.1U_0402_25V6
+1.5VP
On
Off
(Hi-Z)
On
On
On
On
Hi
Hi
Lo
Hi
S3
S0
0.75VSP
PC501
10U_0805_25V6K
VTT_REFP
1.5VP
PQ501
MDU1516URH_POWERDFN56-8-5
S5
PQ502
MDU1511RH_POWERDFN56-8-5
S3
STATE
PC520
4.7U_0805_25V6-K
1.5V_B+
+1.5VP
PR506
@
+1.5V
PC526
0.1U_0402_16V6K
5.76K_0402_1%
JUMP_43X118
@
PJ506
2
+0.75VSP
+0.75VS
JUMP_43X79
@
3
PU502
SY8033BDBC_DFN10_3X3
PC524
0.1U_0402_10V7K
PC519
0.1U_0402_25V6
1
2
PC518
68P_0402_50V8J
1
2
PC516
2200P_0402_50V7K
PC515
22U_0805_6.3VAM
1
2
PC514
22U_0805_6.3VAM
PR512
20K_0402_1%
+1.8VSP
PC525
68P_0402_50V8J
2
1
PR508
4.7_1206_5%
1
1 2
2
PJ507
2
+1.8VSP
+1.8VS
@ JUMP_43X79
1.8VSP_FB
1
PR504
1M_0402_5%
FB=0.6Volt
PC523
680P_0603_50V7K
1
2
0_0402_5%
LX
FB
EN
11
2 EN_1.8VSP
PC507 @
0.1U_0402_10V7K
<42,45,50,52> SUSP#
PR516
1.8VSP_LX
SVIN
TP
PVIN
NC
PC502
22U_0805_6.3VAM
LX
@ JUMP_43X79
PVIN
PG
10
1.8VSP_VIN
NC
PL503
1UH_PH041H-1R0MS_3.8A_20%
1
2
PJ502
2
+3VALW
PR513
10K_0402_1%
4
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

+1.5VP/+1.8VSP
Custom
Rev
1.0
Gx00-CR
Date:

D
Sheet
50
of
60
VID [0]
0
0
1
1
D
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
PJ601
2
+VCCSAP
+VCCSA
JUMP_43X118
PR613
+V1.05S_VCCP
output voltage adjustable network
+VCCSA
0.005_1206_1%
SY8037BDCC_DFN12_3X3
PL601
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
9
8
SVIN
LX
FB
PG
VOUT
EN
VID1
VID0
SA_PGOOD
PR601
100K_0402_5%
1
2
@
PR602
4.7_0603_5%
+3VS
5
1
@ PC605
680P_0402_50V7K
6
@ PR614
0_0402_5%
PR608
1M_0402_5%
+VCCSAP
+V1.05S_VCCP_PWRGOOD
<52>
PR603
0_0402_5%
@ PC606
.1U_0402_16V7K
H_VCCSA_VID0
PR604
1K_0402_5%
2
1
FB_VCCSA
<42>
LX
+VCCSA_PHASE
13
PVIN
PC609
22U_0805_6.3V6M
1
2
10
LX
PC607
22U_0805_6.3V6M
1
2
PC602
68P_0402_50V8J
2
1FB_VCCSA_IC
PVIN
1 2
JUMP_43X79
11
12
GND
2 +VCCSA_PWR_SRC
PC604
22U_0805_6.3V6M
1
2
PU601
2
PC601
22U_0805_6.3V6M
1
2
PC608
22U_0805_6.3V6M
1
2
PC603
22U_0805_6.3V6M
1
2
PJ602
+3VALW
<10>
C
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PR605
1K_0402_5%
2
1
H_VCCSA_VID1
<10>
PR606
100_0402_1%
2
1
+VCCSA_SENSE
<10>
PR607
0_0402_5%
PR612
82.5K_0402_1%
2
1
1
2
PC637
0.1U_0402_25V6
PR616
1M_0402_1%
DGPU_PWR_EN <18,25,42,53>
+0.95VGSP
PL605
1UH_PCMB063T-1R0MS_12A_20%
1
2
+0.95VGS
JUMP_43X118
1
A
1
2
PC622
22U_0805_6.3VAM
1
2
PC631
22U_0805_6.3VAM
+3VALW
PC633
47U_0805_6.3V6M
SY8208DQNC_QFN10_3X3
LDO
BYP
PG
ILMT_0.95V
ILMT
PC628
4.7U_0603_6.3V6K
PR617
100K_0402_5%
PGD_0.95V 2
PC630
4.7U_0603_6.3V6K
2
1
+0.95VGSP
PC629
47U_0805_6.3V6M
10
LX
PC632
0.1U_0603_25V7K
1
2
GND
PC635
220P_0402_50V7K
EN
FB
ILMT_0.95V3
+3VS
IN
BS
9
@
@ PR618
0_0402_5%
PR611
78.7K_0402_1%
10U_0805_25V6K
PC627
2
1
B+_0.95V
+3VS
PU604
PC636 @
0.1U_0402_25V6
2
1
PC621
2200P_0402_50V7K
2
1
B+
PJ606
2
@ PR610
@ PC634
4.7_1206_5%
680P_0603_50V7K
1
2SNB_0.95V 1
2
PL606
HCB2012KF-121T50_0805
1
2
PR615
A
133K_0402_1%
PR609
1M_0402_5%
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

+VCCSAP
Document Number
Rev
1.0
Gx00-CR
1
Sheet
51
of
60
PJ701
PR701
60.4K_0402_1%
1
2
LX_1.05VS_VCCP
11
DH_1.05VS_VCCP
10
DL_1.05VS_VCCP
DL
10_0402_1%
PC704
1000P_0402_50V7K
PR711
75K_0402_1%
2
1
0.01UF_0402_25V7K
1
2
PC708
1U_0603_10V6K
3
2
1
PGND
8
GND
7
TRIP
+5VALW
PR703
<9> VCCIO_SENSE
PC706
V5
COMP
VSNS
PQ702
S TR MDU1511RH 1N POWERDFN56-8
<9> VSSIO_SENSE_L
JUMP_43X118
PC715
0.1U_0402_25V6
2
1
PC713
4.7U_0805_25V6-K
2
1
B+
PL701
1UH_PCMB104T-1R0MH_18A_20%
2
1
DH
GSNS
PC709
PR714
1000P_0603_50V7K 4.7_1206_5%
REFIN
12
0_0402_5%
PC712
10U_0805_25V6K
2
1
PC711
2200P_0402_50V7K
2
1
13
SW
TPS51219RTER_QFN16_3X3
+V1.05S_VCCP
BST
EN
15
PC703
0.01UF_0402_25V7K
14
1
2
VREF
PC707
0.1U_0603_25V7K
1
2
12K_0402_1%
PR712
2
PQ701
S TR MDU1516URH 1N POW ERDFN56-8
PR713
2.2_0603_5%
1
2
BST_1.05VS_VCCP
MODE
PGOOD
16
17
PAD
PU701
10.7K_0402_1%~N
PR704
1
2
PR705
2
PC702
0.1U_0402_25V6
2
1
PL702
HCB2012KF-121T50_0805
2
1
1.05VS_B+
3
2
1
100K_0402_1%
@
PR710
100K_0402_1%
2
1
2
PC701
.1U_0402_16V7K
2
PR706
+1.05VS_VCCPP
<51> +V1.05S_VCCP_PW RGOOD
JUMP_43X118
PJ703
2
1
2
1
+3VS
PR702
@
@ 10K_0402_1%
<42,45,50> SUSP#
PC714
+1.05VS_VCCPP
1
+
330U_6.3V_M
2
B
+1.05VP
OCP min 20A
OVP min 1.24V
PR709
1
2
1
2
10_0402_1%
PC705
1000P_0402_50V7K
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
Title

+1.05VS_VCCP
Size
Document Number
Custom
Rev
1.0
Gx00-CR
Date:
Sheet
1
52
of
60
PC801 @
0.1U_0402_25V6
2
1
PQ801
CSD87351Q5D_SON8-7
2
PL802
0.22UH_PCME064T-R22MS_28A_20%
PR828
10K_0402_1%
1
ISEN2_VGA
+
2
1
+
2
VSUM-_VGA
VSUM+_VGA
PC837
2.2U_0402_6.3V6M
2
1
PC838
2.2U_0402_6.3V6M
2
1
PC856
0.1U_0402_10V7K
2
1
PC857
0.1U_0402_10V7K
2
1
PC839
2.2U_0402_6.3V6M
PC836
2.2U_0402_6.3V6M
2
1
PC830
2.2U_0402_6.3V6M
2
1
PC846
10U_0603_6.3V6M
PC835
2.2U_0402_6.3V6M
2
1
PC829
2.2U_0402_6.3V6M
2
1
PC845
10U_0603_6.3V6M
2
1
PC834
2.2U_0402_6.3V6M
2
1
PC828
2.2U_0402_6.3V6M
2
1
PC844
10U_0603_6.3V6M
2
1
PC833
2.2U_0402_6.3V6M
2
1
PC827
2.2U_0402_6.3V6M
2
1
PC843
10U_0603_6.3V6M
2
1
PC832
2.2U_0402_6.3V6M
2
1
PC826
2.2U_0402_6.3V6M
2
1
PC831
2.2U_0402_6.3V6M
2
1
PC825
2.2U_0402_6.3V6M
2
1
PC842
10U_0603_6.3V6M
2
1
PC855
0.1U_0402_10V7K
2
1
PC854
1U_0402_6.3V6K
2
1
PC853
1U_0402_6.3V6K
2
1
PC851
1U_0402_6.3V6K
2
1
BOOT1_1_VGA
PC858
0.22U_0603_10V7K
1
2
PQ802
CSD87351Q5D_SON8-7
PC881
10U_0805_25V6K
2
1
PC880
10U_0805_25V6K
PC878 @
0.1U_0402_25V6
2
1
UGATE1_VGA
PR852
2.2_0603_5%
2
1
PC879
2200P_0402_50V7K
2
1
<27,53>
PL803
0.22UH_PCME064T-R22MS_28A_20%
SW1_VGA
VSUM-_VGA
PR861
10_0402_1%
+VGA_CORE
V1N_VGA
1_0402_1%
1
PR858
2
PR838
10K_0402_1%
PR857
10K_0402_1%
ISEN2_VGA
VSUM-_VGA
Layout Note:
Place near Phase1 Choke
LGATE1_VGA
1
LF1_VGA
ISEN1_VGA
PR855 @
4.7_1206_5%
2
1
PR856
3.65K_0402_1%
2
1
7
6
5
PHASE1_VGA
PH802
10K_0402_1%_TSM0A103F34D1RZ
PR862
953_0402_1%
1
2
PC866
0.1U_0402_16V7K
+VGA_B+
VSSSENSE_VGA
PC861
0.033U_0603_25V7K
2
1
PC860
0.22U_0603_10V7K
2
1
VSUM_VGA_N001
1
<42>
VSUM+_VGA
ISEN1_VGA
PC865 @
680P_0402_50V7K
2
1 SNUB1_VGA
PR859
11K_0402_1%
2
1
0_0402_5%
PC864 @
0.01U_0402_25V7K
<27,53> VSSSENSE_VGA
PR860
PC862
1000P_0402_50V7K
PC863 @
330P_0402_50V7K
2
1
PC859
330P_0402_50V7K
PR854
0_0402_5%
<27> VCCSENSE_VGA
+5VS
PR853
2.61K_0402_1%
1NTC_VGA
2
1
PR850
10_0402_1%
PR851 @
82.5_0402_5%
PC841
10U_0603_6.3V6M
2
1
2
1
GPU_IMON
VSUM+_VGA
1
+VGA_CORE
PR826 @
4.7_1206_5%
2
1
PC811 @
680P_0402_50V7K
2
1
SNUB2_VGA
PC877
0.22U_0603_25V7K
PC876
1U_0603_10V6K
2
1
1
1
2
+5VS
V2N_VGA
+VGA_B+
@ 0_0402_5%
2
BOOT1_VGA
VSUM-_VGA
PR845
0_0402_5%
2
1
PR848
1_0402_5%
1
2
ISEN1_VGA
PR849
30K_0402_1%
1
1
+5VS
PC875
0.22U_0402_10V6K
PR846
221K_0402_1%
ISEN2_VGA
PC848
150P_0402_50V8J
PR844
VIN_VGA
PC850
0.22U_0402_10V6K
2FB2_VGA1
ISL62883CHRTZ-T_TQFN40_5X5
VSEN_VGA
For 15W one phase
PR863
0_0402_5%
1
2
PC824
2.2U_0402_6.3V6M
2
1
390P_0402_50V7K
PR843
1.69K_0402_1%
1
2
PC872
1U_0603_10V6K
PR864
0_0402_5%
1
2
@
+5VS
PC840
10U_0603_6.3V6M
2
1
PR842
499_0402_1%
PC874
2FB1_VGA1
2
AGND
+VGA_CORE
+VGA_CORE
41
30
29
28
27
26
25
24
23
22
21
0.047U_0402_16V7-K
1
2
PR847
11K_0402_1%
PC871
22P_0402_50V8J
1
2
COMP_VGA
FB_VGA
2ISEN3_VGA
PC873
1000P_0402_50V7K
PR840 @
249K_0402_1%
1
2
PR841
5.9K_0402_1%
1
VW_VGA
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
VDD_VGA
1
2
3
4
5
6
7
8
9
10
PC812
1U_0603_10V6K
1
2
PC849
2
1
PU801
40
39
38
37
36
35
34
33
32
31
PR836
147K_0402_1%
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PC847
33P_0402_50V8J
1
2
PR833
2.2K_0402_1%
2
11
12
13
14
15
16
17
18
19
20
<24,53> GPU_GPIO0
2
LGATE2_VGA
RTN_VGA
ISUM-_VGA
1 PR834 2
0_0402_5%
PR835
2
@ 1
2.2K_0402_1%
GPU_VID6
1.91K_0402_1%
+3VGS
9> DGPU_PWROK
CLK_ENABLE#_VGA
PR827
3.65K_0402_1%
2
1
LF2_VGA
PC809
330U_D2_2V_Y
PC808
330U_D2_2V_Y
SW2_VGA
PR829
1_0402_1%
2
1
7
6
5
PC807
330U_D2_2V_Y
UGATE2_VGA
PC810
330U_D2_2V_Y
PC806
0.22U_0603_10V7K
1
2
DPRSLPVR_VGA-1
RBIAS_VGA
PSI#_VGA
PR831
2
1
1.91K_0402_1%
PR832
0_0402_5%
2
1
B+
PR837
10K_0402_1%
BOOT2_2_VGA
2.2K_0402_1%
2
PR812
1
GPU_VID0
<24>
<24>
GPU_VID0
<24>
GPU_VID1
PR817
2.2_0603_5%
2
1
BOOT2_VGA
PHASE2_VGA
+3VGS
@ PR830
1
PL801
HCB4532KF-800T90_1812
1
2
PR811
1
GPU_VID1
+VGA_B+
PC804
10U_0805_25V6K
2
1
10K_0402_1%
2
PR810
1
GPU_VID2
(1 1 0 0 0 0)
PC803
10U_0805_25V6K
10K_0402_1%
2
PR809
1
GPU_VID3
Sun Pro = 0.9V
PC802
2200P_0402_50V7K
2
1
PR808 @ 10K_0402_1%
1
2
GPU_VID4
10K_0402_1%
2
PR807 @ 10K_0402_1%
1
2
GPU_VID5
10K_0402_1%
2
PR806 @ 10K_0402_1%
1
2
GPU_VID0
10K_0402_1%
2
PR805 @ 10K_0402_1%
1
2
GPU_VID1
PR804
1
GPU_VID2
PR803 @ 10K_0402_1%
1
2
GPU_VID3
(1 1 0 1 0 0)
PC852
1U_0402_6.3V6K
2
1
0_0402_5%
PR819
1
2
<24>
GPU_VID2
<24,53> GPU_GPIO0
100P_0402_25V8K
<24>
GPU_VID3
PR818 @
1
2
PC805 @
1
2
GPU_VID4
@
+3VGS
10K_0402_1%
2
PR814
0_0402_5%
PR816
2.2K_0402_1%
1
2
Mars XT = 0.85V
PR820
0_0402_5%
2
1
<42> EC_VGA_EN
GPU_VID5
DGPU_PWR_EN
PR802
1
GPU_VID4
@
PR813
147K_0402_1%
1
2VRON_VGA
<18,25,42,51>
GPU_VID5
PR801
1
10K_0402_1%
2
+3VGS
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
PWR-CPU_CORE
Size
C
Date:

Document Number
Rev
1.0
Gx00-CR
D
Sheet
53
of
60
PR955
1K_0402_1%
DROOP
+5VS
SW1A <55>
SW2 <55>
PC920
2
2.2U_0603_10V7K
PC922
2
0.22U_0603_25V7K
BST1_1
CSP2A
PR934 2
41.2K_0402_1%
+5VS
3P: 73.2K
2P: 41.2K
2Phase: @
1Phase: install
SW1 <55>
PR935
0_0402_5%
Option for
2 phase CPU
3Phase: @
2Phase: install
6132_PWM
CSP3
PC924
2
.1U_0402_16V7K
2
PC932
1000P_0402_50V7K
PC931
PR941
5.62K_0402_1%
2
SWN2 <55>
TSENSE
@
PR960
6.98K_0402_1%
PR917
2
CSREF
CSP2
PC927
0.047U_0402_16V7K
PR945
SWN1 <55>
5.62K_0402_1%
@
3P: 1500p0.047U_0402_16V7K
CSREF
2P: 1200p
PR961
6.98K_0402_1%
PR949
100K_0603_1%
1
2
2 PC936
220P_0402_50V7K
1 PR952 2NTC_PH201 1 PR953 2

75K_0402_1%
165K_0402_1%
PH903
2
SWN1
CSSUM
PC934
2
1000P_0402_50V7K
PR946 1
PUT COLSE
TO VCORE
Phase 1
Inductor
PR928
0_0402_5%
Option for
1 phase GFX
+5VS
HG1 <55>
1
PR931 2
0_0402_5%
LG1 <55>
BST1
CSREF <55>
CSREF
1000P_0402_50V7K
3P: 806
2P: 1K
1
1
LG2 <55>
2
1 PR930
6132P_VCCP
CSP1
3P: 3.65K
2P: 9.53K
PC937
1
2
PR916
2
BST2
3P: 21K
2P: 12.4K
3P: 2200p
2P: 3300p
3P: 23.7K
2P: 24.9K
PR921
PC918
2 BSTA1_1
1
2
2.2_0603_5%
0.22U_0603_25V7K
PC919
LG1A <55>
1
PR9242 BST2_1
1
2
0.22U_0603_25V7K
2.2_0603_5%
HG2 <55>
CSP1
CSP2
CSP3
806_0402_1%
.1U_0402_16V7K
3P: 348
2P: 1.21K
PC933
PR950
1
8.06K_0402_1%
PUT COLSE
TO V_GT
HOT SPOT
2.2_0603_5%
PR943
PC929
2
1COMP_CPU1 2
1
6.04K_0402_1%
1500P_0402_50V7K
3P: 6.04K
2P: 4.32K
PR948
0.033U_0402_16V7K
PR944
PC930
1
2FB_CPU3 1
2
10_0402_1%
0.033U_0402_16V7K
PR947
1
2
FB_CPU2
CSCOMP
HG1A <55>
22P_0402_50V8J
PR942
PC928
1
2FB_CPU1 1
2
49.9_0402_1%
680P_0402_50V7K
TRBST#
PC926
2
1
1 PR940 2
1K_0402_1%
3P: 330p
2P: 1000p
CSP2A
CSP1A
TSENSEA
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
BSTA1
PC923
1000P_0402_50V7K
VSP
3P: 22p
2P: 10p
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
PR938
0_0402_5%
2
1
<9> VCCSENSE
VSN
PC935
1
2
PR936
0_0402_5%
2
1
<16,42> VGATE
<9> VSSSENSE
VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT NCP6132AMNR2G_QFN60_7X7
SW2
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1
PH904
100K_0402_1%_TSM0B104F4251RZ
2P: 36K
1P: 26.1K
PR933
10K_0402_5%
<42,46,47,6> H_PROCHOT#
PR918
1
2
26.1K_0402_1%
6132_PWMA
24.9K_0402_1%
@
PR932
75_0402_1%
PC921
.1U_0402_16V7K
TSENSE
PR929 1K_0402_1%
+3VS
SWN1A <55>
PC914
2
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
+V1.05S_VCCP
CPU_B+
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PR927
60.4K_0402_1%
1
0_0402_5%
PR925
1
2
10K_0402_1%
1
2
PR926
0_0402_5%
1VR_SVID_DAT1
1
2
3
4
5
VR_SVID_DAT1
6
VR_SVID_ALRT#
VR_SVID_CLK7
8
VBOOT
9
ROSC_CPU
10
VRMP
11
H_PROCHOT#
12
VGATE
13
14
15
DIFF_CPU
2.2U_0603_10V7K
PR920
2
1VR_ON_CPU
<42> VR_ON
0.01U_0402_25V7K
<9> VR_SVID_DAT
<9> VR_SVID_ALRT#
<9> VR_SVID_CLK
PC917
.1U_0402_16V7K
PR923
1
2
54.9_0402_1%
PR922 2
130_0402_1%
PC916
.1U_0402_16V7K
PR913
5.6K_0402_1%
PU901
6132_VCC
TRBST#
FB_CPU
COMP_CPU
IMVP_IMON
IMON
IMON
1
2 ILIM_CPU
PR939 12.4K_0402_1%
DROOP
CSCOMP
1
PR919 2
2_0603_5%
PC915
1
2
+5VS
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
Switching Frequency = 450KHz
CSP1A
PC911
1000P_0402_50V7K
1PR914
2
15.8K_0402_1%
CSCOMPA
+V1.05S_VCCP
SWN1A
PC910
0.047U_0402_16V7K
CSREFA <55>
CSSUMA
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
PC912
1000P_0402_50V7K
PR954
0_0402_5%
2
1
<10> VSS_AXG_SENSE
PR912 2
63.4K_0603_1%
PR937
0_0402_5%
2
1
TSENSEA
CSREFA
2P: 21.5K
1P: 15.8K
CSREFA
1000P_0402_50V7K
2P: 1.65K
1P: 1K
6.04K_0402_1% 2200P_0402_50V7K
<10> VCC_AXG_SENSE
PC906
1
2
DROOPA
1_0402_5%
PR907
165K_0402_1%
PR910 10P_0402_50V8J PC909

2 COMPA11
2
1K_0402_1%
PR915
2
1K_0402_1%
CSCOMPA
PR906
220K_0402_5%_ERTJ0EV224J
NTC_PH203
PR909 2
1_0402_5%
680P_0402_50V7K
FBA2
24.9K_0402_1%
PC908
1
2
1
2
10_0402_1%
PC907
1
2
4700P_0402_25V7K
PR908
200K_0402_1%
2P: 24K
1P: 24.9K
10.7K_0402_1%
PC905
PUT COLSE
TO GT
Inductor
PH901
1.21K_0402_1%
SWN2
.1U_0402_16V7K
1 PR904 2
FBA1
PR902 2
200K_0402_1%
680P_0402_50V7K
PR903
PC903
1
2
10_0402_1%
TRBSTA#
PH902
100K_0402_1%_TSM0B104F4251RZ
PC902
2
2 PC901
PR905
1
2
75K_0402_1%
FBA3
PC904
1
2
PR901 2
1200P_0402_50V7K
1
D
470P_0402_50V7K
PR915,PR946=200K(setting 113 degreeC)

PR915,PR946=8.25K(setting 93 degreeC)
PR951
100K_0603_1%
PUT COLSE
TO VCORE
HOT SPOT
1
220K_0402_5%_ERTJ0EV224J
<42> IMVP_IMON
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PWR-CPU_CORE
Custom
Date:
Rev
1.0
Gx00-CR
Sheet
1
54
of
60
S TR MDU1516URH 1N POWERDFN56-8
PR958
PC944
0.1U_0402_25V6
2
1
3
CSREF <54>
<54> LG2
PQ904
SWN1 <54>
PC948
V2N_CPU 2 PR959 1
10_0402_1%
SNUB_CPU2
2
10_0402_1%
3
2
1
2
3
2
1
PQ903
PR957
4.7_1206_5%
V1N_CPU
1SNUB_CPU1
+VCC_CORE
PL903
S COIL 0.22UH +-20% PCMB104T-R22MS 35A
1
4
<54> SW2
PR956
4.7_1206_5%
<54> LG1
PC943
10U_0805_25V6K
2
1
PC942
10U_0805_25V6K
2
1
PQ902
<54> HG2
+ PC947
220U_25V_M
+VCC_CORE
<54> SW1
CPU_B+
PL902
3
2
1
PL901
HCB4532KF-800T90_1812
1
2
3
2
1
PQ901
CPU_B+
B+
PC941
2200P_0402_25V7K
2
1
PC940
0.1U_0402_25V6
2
1
<54> HG1
PC939
10U_0805_25V6K
2
1
PC938
10U_0805_25V6K
2
1
CPU_B+
PC946
2200P_0402_25V7K
2
1
CSREF
SWN2 <54>
1
680P_0603_50V7K
2
PC949
680P_0603_50V7K
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A
PC960
2200P_0402_25V7K
2
1
PC959
0.1U_0402_25V6
2
1
PC958
10U_0805_25V6K
2
1
PC957
10U_0805_25V6K
2
1
CPU_B+
<54> HG1A
+VCC_GFXCORE_AXG
<54> SW1A
PR967
4.7_1206_5%
3
2
1
PQ909
SNUB_GFX1
<54> LG1A
V1N_GFX
3
2
1
PL905
PQ907
PR971 1
CSREFA <54>
10_0402_1%
PC968
SWN1A <54>
680P_0603_50V7K
A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
PWR-CPU_CORE
Size
C
Date:

Document Number
Rev
1.0
Gx00-CR
1
Sheet
55
of
60
+VCC_CORE
1
+VCC_CORE
1
PC1
10U_0805_6.3VAM
1
PC2
10U_0805_6.3VAM
1
PC3
10U_0805_6.3VAM
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_GFXCORE_AXG
1
PC4
10U_0805_6.3VAM
PC5
10U_0805_6.3VAM
Socket Bottom
5 x 22 F (0805)
5 x (0805) no-stuff
sites
Socket Top
7 x 22 F (0805)
2 x (0805) no-stuff
sites
+VCC_GFXCORE_AXG
1
PC10
10U_0805_6.3VAM
+VCC_CORE
2
1
1
+
+
PC64
22U_0805_6.3V6M
1
+
PC67
330U_D2_2V_Y
1
PC63
22U_0805_6.3V6M
PC66
330U_D2_2V_Y
PC56
22U_0805_6.3V6M
PC48
22U_0805_6.3V6M
PC33
22U_0805_6.3V6M
PC53
22U_0805_6.3V6M
PC32
22U_0805_6.3V6M
1
PC62
22U_0805_6.3V6M
PC52
22U_0805_6.3V6M
2
1
PC31
22U_0805_6.3V6M
PC47
22U_0805_6.3V6M
PC61
22U_0805_6.3V6M
PC51
22U_0805_6.3V6M
PC30
22U_0805_6.3V6M
PC46
22U_0805_6.3V6M
PC50
22U_0805_6.3V6M
PC29
22U_0805_6.3V6M
+V1.05S_VCCP
PC28
22U_0805_6.3V6M
PC45
22U_0805_6.3V6M
+V1.05S_VCCP
PC43
22U_0805_6.3V6M
PC59
330U_D2_2V_Y
PC44
22U_0805_6.3V6M
PC42
22U_0805_6.3V6M
PC41
22U_0805_6.3V6M
PC58
330U_D2_2V_Y
1
PC24
22U_0805_6.3V6M
1
PC23
22U_0805_6.3V6M
PC40
22U_0805_6.3V6M
PC39
22U_0805_6.3V6M
1
PC22
22U_0805_6.3V6M
PC38
22U_0805_6.3V6M
1
PC21
22U_0805_6.3V6M
PC36
22U_0805_6.3V6M
1
PC20
22U_0805_6.3V6M
PC27
22U_0805_6.3V6M
PC19
22U_0805_6.3V6M
1
PC9
10U_0805_6.3VAM
PC18
22U_0805_6.3V6M
1
PC8
10U_0805_6.3VAM
PC17
22U_0805_6.3V6M
1
PC7
10U_0805_6.3VAM
PC15
22U_0805_6.3V6M
1
PC6
10U_0805_6.3VAM
PC13
22U_0805_6.3V6M
@
PC71
22U_0805_6.3V6M
@
PC72
22U_0805_6.3V6M
1
+
PC74
330U_D2_2V_Y
1
+
PC78
330U_D2_2V_Y
PC73
330U_D2_2V_Y
PC77
330U_D2_2V_Y
PC76
330U_D2_2V_Y
+VCC_CORE
2@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
Title

PWR - PROCESSOR DECOUPLING
Size
Document Number
Rev
1.0
LA-9631P
Date:
Sheet
1
56
of
60
VIWGP/R PWR PIR List
Item
Page
MODIFICATION LIST
PURPOSE
P.46
Add PR102,PC108,PC109
For ADP_ID pin detect
EVT TO DVT
P.47
Add PR225,PR227,PR228,PQ206,PQ207,PQ208
For protect adapter function
P.49
Add PR410,PC433
For 3VALWP/5VALWP sequence
P.49
Add PC434,PC435,PC436,PC437
For EMI solution
P.49
Add PC432 and change PL404 from 1.5uH to 3.3uH
For improve output voltage ripple
P.50
Change PR502 from 49.9k to 64.9k
For +0.75VSP sequence
P.51
Add PC637
For +0.95VGSP sequence
P.54
Change PC907,PR912,PR927,PC928
For CPU Transient
P.48
Add PR326 and PQ314
For battery health function
10
P.49
Add PR411,PC432
To delay +3VALW enable. PR411 change to 10K and PC432 change to 0.047uF
11
P.49
Change PC439 from 4700P to 10nF ,PC436 from 47nF to 6.8nF
Adjust +3VALW and +5VALW rising time.
12
P.51
Add PR614
For Celeron CPU SA_PGOOD
Compensation
PVT TO PVT2
13
14
15
16
17
18
19
20
21
B
22
23
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

HW-PIR1
Custom
Date:
Rev
1.0
LA-9631P
Sheet
1
57
of
60
COMPAL CONFIDENTIAL
3
3
10
B4
4
EC
PQ2
PCH_RSMRST#_R
B7
A4
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
PLT_RST#
12
16
CPU
SYSON
SYSON#
V
V
PU702
+V1.05S
PU602
+V1.05S_VCCP
SA_PGOOD
8a
(DIS)
U38
+5VS
8b
(DIS)
U39
+3VS
8a
DGPU
Q8
+1.5VS
PU701
+0.75VS
13
VR_ON
SVID
DGPU_PWR_EN
PU601
+VCC_SA
+1.5V
PU501
SUSP#,SUSP
13
DGPU_PWROK
ON/OFF
H_CPUPWRGD
VGATE
11
PM_DRAM_PWRGD
PBTN_OUT#
B6
PCH
14
15
SYS_PWROK
A5
EC_ON
51ON#
V V
B3
C
PCH_PWROK
+5VALW
B2
B+
B7
B1
A5
V V
+3VALW
PU401
B+
+3V_PCH
+5V_PCH
PU301
10
B5
VV
V V
A3
A2
BATT
MODE
BATT
VIN
A1
PCH_PWROK
AC
MODE
MODEL NAME: Power Sequence Block Diagram

LA-9631P
PCB NAME:
REVISION:
2011/07/13
DATE:
SVID
PU901
+VCC_CORE
14 VGATE
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

Power sequence
Custom
Rev
1.0
LA-9631P
Date:
Sheet
1
58
of
60
VIWGP/R HW PIR List
Item
Page
MODIFICATION LIST
PURPOSE
P.46
Change C726, C727 to 2.2nF
For Sequence
EVT TO DVT
P.36
Add R405
For Intel Combo Card
P.35
Delete RP19. Add RP26, RP27
Because ME modify MIC location
P.14
Add R406, R407, R408, R409
Reserve for improvement factory processes
P.42
Add EC_SPI_SO, EC_SPI_SI, EC_SPI_CLK, EC_SPI_CS# to EC
P.42
Add PCH_PWR_EN to EC Pin.107
P.42
Reserve R410
Reserve Pull-high for GPIO
P.5~32
Change footprint of JCPU1, U4, UV1, UV5, UV6, UV7, UV8, UV9, UV10, UV11, UV12
For Lenovo rule
P.25
Change RV41 to 240K. Change CV53 to 0.1uF
For VGA sequence
10
P.21
Add Q21, R40, C237, R225, C243
Reserve for power consumption
11
P.34
Add R411, R412, C411, C412
Reserve for EMI
12
P.25
Change CV36, CV37 to 8.2pF
For Crystal fine-tune
13
P.42
Add ADP_65 to EC Pin.21
For adapter protection
14
P.42
15
P.42
16
P.42
Change EC_FAN_PWM from EC Pin.34 to EC Pin.26
For common design
17
P.42
Change NOVO# from EC Pin.26 to EC Pin.34
For common design
18
P.42
Add ADP_ID to EC Pin.66
For adapter
19
P.42
Change PCH_ENBKL from EC Pin.73 to EC Pin.76
For common design
20
P.42
Change IMVP_IMON from EC Pin.76 to EC Pin.73
For common design
21
P.42
Add VGATE to EC Pin.74
Reserve for sequence
22
P.42
Add SYS_PWROK to EC Pin.86
Reserve for sequence
23
P.42
Change EC_TS_ON# from EC Pin.85 to EC Pin.97
For common design
24
P.42
Change DGPU_PWR_EN from EC Pin.107 to EC Pin.123
For common design
25
P.42
Change SUSCLK from EC Pin.123 to EC Pin.122
For common design
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

HW-PIR1
Custom
Date:
Rev
1.0
LA-9631P
Sheet
1
59
of
60
VIWGP/R HW PIR List
Item
Page
MODIFICATION LIST
PURPOSE
P.40
Delete R416, Add J9
No need Zero ODD Function
P.36
Reserve R508
For leakage current issue of Atheros WLAN
P.33
Add R509
protect BKOFF# damage
P.42
Reserve R416
Reserve +3VLP power rail to EC
P.42
Change EC_RST# power rail to +3V_EC
Using power rail which the same with EC.
P.42
Change EC_SMB_CK1 & EC_SMB_DA1 power rail to +3V_EC
Using power rail which the same with EC.
P.14
Change U5 from 4MB to 8MB ROM
Follow common design
P.14
Delete R266, R221, U6
It is for 2MB ROM, we don't need it
P.41
Reserve resistance to +3VLP and +3VALW.
For Speaker Noise in S5
P.42
Reserve resistance in EC for share ROM.
Follow common design
P.51
Reserve +V1.05S_VCCP_PWRGOOD of +V.05S_VCCP to connect to SA_PGOOD
For Celeron CPU
DVT TO PVT
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

HW-PIR2
Custom
Date:
Rev
1.0
LA-9631P
Sheet
1
60
of
60
www.s-manuals.com

Compal La-9631p r1.0 Schematics

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Compal La-9631p r1.0 Schematics

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A

Gx00/Gx00 DIS M/B Schematics Document

Compal Electronics, Inc.

Compal Secret Data

Wednesday, February 27, 2013

AMD MARS XT M2 128 bits

USB30 Port 0,1

USB20 Port 11 page 28

PCIe Mini Card

Int. MIC Conn.

Int. Speaker Conn.

Audio Combo Jacks

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

S5 S4/ Battery only

S5 S4/AC & Battery

Board ID / SKU ID Table for AD channel

USB Port Table

PCH SM Bus address

AMD-GPU SM Bus address

1010 000x A0h

Internal thermal sensor 0100 0001 41h

1010 010x A4h

BOM Structure Table

USB 2.0 Port

USB Port (Right Side USB-BD)

SMBUS Control Table

Compal Electronics, Inc.

Compal Secret Data

UV5, UV6, UV7, UV8

"Mars" has the following requirements with regards to power-supply

Sun PRO VRAM STRAP

Global ASIC Reset

Compal Electronics, Inc.

Compal Secret Data

VGA Notes List

Wednesday, February 27, 2013

PEG_ICOMPI and RCOMPO signals should be

eDP_COMPIO and ICOMPO signals

PCI EXPRESS* - GRAPHICS

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane #

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

DDR3 Compensation Signals

JTAG & BPM

Buffered reset to CPU

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

Compal Secret Data

Eiffel used 0.01u

Compal Electronics, Inc.

Wednesday, February 27, 2013

CFG Straps for Processor

Interl request AH26 short GND

1 : Disabled; No Physical Display Port

1: Normal Operation; Lane #