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entity fifo_ctrl is

Port ( rd : in STD_LOGIC; wr : in STD_LOGIC; clk : in STD_LOGIC; rst : in


STD_LOGIC;
wrinc : out STD_LOGIC; rdinc : out STD_LOGIC; empty : out
STD_LOGIC; full : out STD_LOGIC);
end fifo_ctrl;
architecture Behavioral of fifo_ctrl is
begin
generare_rdinc : process(rd,wr)
variable c: integer range 0 to 8;
begin
if(rst = '1')then rdinc <= '0'; wrinc <= '0'; c:= 0; empty<= '1'; full<= '0';
else
if(rd= '1')then rdinc <= '1';
if(c>0)then c:= c-1;
if(c=0)then empty<='1';
else empty<='0';
end if;
end if;
else rdinc <= '0';
end if;
if(wr= '1')then wrinc <= '1';
if(c<8)then c:= c+1;
if(c=8)then full<='1';
else full<='0';
end if;
else wrinc <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
entity filtr is
Port ( d_in : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q_out :
out STD_LOGIC);
end filtr;
architecture Behavioral of filtr is
signal Q1, Q2, Q3 : std_logic;
begin
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then Q1 <= '0'; Q2 <= '0'; Q3 <= '0';
else Q1 <= D_IN; Q2 <= Q1; Q3 <= Q2;
end if;
end if;
end process;
Q_OUT <= Q1 and Q2 and (not Q3);
end Behavioral;
entity fifo8x8 is
Port ( rd : in STD_LOGIC; wr : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR
(7 downto 0);

wrinc : in STD_LOGIC; rdinc : in STD_LOGIC; rst : in STD_LOGIC; clk : in


STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end fifo8x8;
architecture Behavioral of fifo8x8 is
signal wrptr : STD_LOGIC_VECTOR(2 downto 0);
signal rdptr : STD_LOGIC_VECTOR(2 downto 0);
signal write_loc : STD_LOGIC_VECTOR(7 downto 0);
type fifo_type is array ( 0 to 7) of STD_LOGIC_VECTOR(7 downto 0);
signal fifo : fifo_type;
signal out_mux : STD_LOGIC_VECTOR(7 downto 0);
begin
p_citire : process(clk)
begin
if(clk'event and clk='1') then
if(rst='1') then rdptr<="000";
else
if(rdinc='0') then rdptr <=rdptr + 1;
end if;
end if;
end if;
end process;
p_scriere : process(clk)
begin
if(clk'event and clk='1') then
if(rst='1') then rdptr<="000";
else
if(rdinc='0') then wrptr <=wrptr + 1;
end if;
end if;
end if;
end process;
decodificator : process(wrptr)
begin
case wrptr is
when "000"=>write_loc <= "00000001";
when "001"=>write_loc <= "00000010";
when "010"=>write_loc <= "00000100";
when "011"=>write_loc <= "00001000";
when "100"=>write_loc <= "00010000";
when "101"=>write_loc <= "00100000";
when "110"=>write_loc <= "01000000";
when others =>write_loc <= "10000000";
end case;
end process;
registre : process(clk)
begin
if(clk'event and clk='1') then
if(rst='1') then for i in 0 to 7 loop
fifo(i)<="00000000";
end loop;
if(wr='1') then for i in 0 to 7 loop
if(write_loc(i)='1') then fifo(i) <= data_in;
end if;

end loop;
end if;
end if;
end if;
end process;
multiplexor : process(rdptr,fifo)
begin
case rdptr is
when "000"=>out_mux <= fifo(0);
when "001"=>out_mux <= fifo(1);
when "010"=>out_mux <= fifo(2);
when "011"=>out_mux <= fifo(3);
when "100"=>out_mux <= fifo(4);
when "101"=>out_mux <= fifo(5);
when "110"=>out_mux <= fifo(6);
when others =>out_mux <= fifo(7);
end case;
end process ;
buff : process (rd,out_mux)
begin
if( rd = '1') then data_out <= out_mux;
else data_out <= "ZZZZZZZZ";
end if;
end process;
end Behavioral;
entity main is
Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0); btn_rd : in STD_LOGIC;
btn_wr : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC;
SF_D : out STD_LOGIC_VECTOR (3 downto 0); SF_CE0 : out STD_LOGIC;
LCD_E : out STD_LOGIC; LCD_RS : out STD_LOGIC; LCD_RW : out
STD_LOGIC;
empty : out STD_LOGIC; full : out STD_LOGIC);
end main;
architecture Behavioral of main is
component fifo8x8 is
Port ( ... );end component fifo8x8;
component fifo_ctrl is
Port ( ... );end component fifo_ctrl;
component filtr is
Port ( ... );end component filtr;
component lcd_ctrl is
Port ( ... );end component lcd_ctrl;
function hex2ascii (hex : STD_LOGIC_VECTOR (3 downto 0)) return
STD_LOGIC_VECTOR is
variable ascii : STD_LOGIC_VECTOR (7 downto 0);
begin
if(hex > x"9") then ascii := x"0" & hex + x"37";
else ascii := x"0" & hex + x"30";
end if;
return ascii;
end function hex2ascii;
signal rd: std_logic;
signal wr:std_logic;

signal rdinc:std_logic;
signal wrinc:std_logic;
signal data_ins,data_outs:std_logic_vector(15 downto 0);
signal data_out:std_logic_vector(7 downto 0);
signal lcd: std_logic_vector(63 downto 0);
begin
data_ins<="00000000"&data_in;
data_outs<="00000000"&data_out;
filter_rd: filtr Port map(d_in => btn_rd, clk => clk, rst => rst, q_out => rd);
filter_wr: filtr Port map(d_in => btn_wr, clk => clk, rst => rst, q_out => wr);
fifo_control:fifo_ctrl Port map(rd=>rd, wr=>wr, clk=>clk, rst=>rst, rdinc=>rdinc,
wrinc=>wrinc, empty=>empty, full=>full);
fifo_8x8: fifo8x8 Port map(data_in=>data_in, data_out=>data_out, rd=>rd,
wr=>wr, wrinc=>wrinc,
rdinc=>rdinc, rst=>rst, clk=>clk);
lcd_control:lcd_ctrl Port map(clk =>clk, rst =>rst, lcd =>lcd, SF_D =>SF_D,
SF_CE0=>SF_CE0,
LCD_E=>LCD_E, LCD_RS=>LCD_RS, LCD_RW=>LCD_RW);
lcd(63 downto 48)<= hex2ascii(data_in(7 downto 4)) & hex2ascii(data_in(3
downto 0));
lcd(47 downto 32)<=x"2020";
lcd(31 downto 16)<= hex2ascii(data_in(7 downto 4)) & hex2ascii(data_in(3
downto 0));
lcd(15 downto 0)<=x"2020";
end Behavioral;