A

Compal confidential

JBK00 LA-4092P Schematics Document

Mobile AMD S1G2 CPU with ATI
RX781 & SB700 core logic with M82-S
3

2008-02-20
REV:0.4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

Consumer AMD UMA/DISCRETE 17"

Compal
confidential

Thermal Sensor
ADM1032ARMZ

VRAM
256MB

DDR2 667MHz 1.8V

DDR2 800MHz 1.8V

AMD S1G2 CPU

72QFN

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3

638-PIN uFCPGA 638

P6

Clock Generator
SLG8SP626

P8, 9

P22

Dual Channel
P4, 5, 6, 7

page 19, 20

Fan conn

P4

Hyper Transport Link

16X16

Discrete
ATI M82-S

PCI-E Lane*16

P15,16,17,18,21

LVDS Panel
Interface

ATI RX781M

Finger Print

P24

USB Camera
with Digital MIC

P10, 11, 12, 13, 14

CRT

P39

P39

P23
USB2.0 X12

A-Link Express II

USB conn x4

P39

4X PCI-E

HDMI

P25

BT Conn
PCI-E BUS*5

ATI SB700
RTL8111C
10/100/1000

SATA Master-1
SATA Master-2

P39

SATA Slave

P33

WLAN & TV Tunner

Touch Screen

SATA Slave

Express Card

Mini-Card*2
P32

LED

P39

Azalia

P26, 27, 28, 29, 30

Dock

P33

P43

P42

RJ45 Conn.

Audio CKT

LPC BUS

RTC CKT.

AMP & Audio Jack

Codec_92HD71B7

P32

TPA6020A2 P37

P36

P26

ENE
KB926

SPI

JMB380

Power OK CKT.

SPI ROM
P34

MDC V1.5

SUBAMP

P42

TPA3007D1

P38

P41

P40

SATA HDD Connector

P31

CardReader
Docking CKT.

P34

1394 Conn.

P34

P38

P41

P42

SATA ODD Connector

CIR

P43

Subwoofer

Int.KBD

Touch Pad CONN.

P31

P37

SATA 2nd HDD Option Connector

P31

DC/DC Interface CKT.

P44

e-SATA Connector
P39

ACCELEROMETER.
LIS302DLTR

Compal Secret Data

Security Classification

P35

2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

Voltage Rails
Symbol Note :
+5VS
+3VS

power
plane

: means Digital Ground

+2.5VS
+1.8VS
+1.5VS
+B
+3VL
+5VL

+5VALW
+3VALW
+1.2VALW
+3V_LAN

: means Analog Ground

+1.1VS

+1.8V

+VGA_CORE

+0.9V

@ : means just reserve , no build

DEBUG@ : means just reserve for debug.

+1.2V_HT
+CPU_CORE_NB

State

+CPU_CORE_0

Layout Notes

+CPU_CORE_1

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

O MEANS ON

X MEANS OFF

I2C / SMBUS ADDRESSING

SMBUS Control Table

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

ACCELEROMETER

3A

00111010

SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK

KB926
KB926
RS780M

I2C_DATA
DDC_CLK0
DDC_DATA0

EC SM Bus1 address
Device

HEX

Address

Smart Battery

16H

0001 011X b

A0H

1010 000X b

98H

1001 100X b

24C16
CPU SIC interface

EC SM Bus2 address

DDC_CLK1
DDC_DATA1

HEX

Address

SCL0

ADI1032-2 CPU

9AH

1001 101X b

SDA0

ADI1032-1 VGA

98H

1001 100X b

Device

RS780M
SB700

SCL1

SB700

SDA1
SCL2

SB700

SDA2
4

RS780M

SCL3

SB700

SDA3

X
X
X
X
X
X
X
X
X

BATT

V
X
X
X
X
X
X
X
X

SERIAL
EEPROM

THERMAL
SENSOR
CPU &
ADM1032

X
V
X
X
X
X
X
X
X

V
X
X
X
X
X
X
X
X

SODIMM
I / II

X
X
X
X
X
V
X
X
X

2007/08/02

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

CLK CHIP

X
X
X
X
X
V
X
X
X

Compal Secret Data

Security Classification
Issued Date

INVERTER

Title

MINI CARD
Slot 2

X
X
X
X
X
X
V
X
X

LCD

HDMI

X
X
V
X
X
X
X
X
X

X
X
X
V
X
X
X
X
X

G-Sensor
3

X
X
X
X
X
V
X
X
X

Compal Electronics, Inc.

Notes List

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

VLDT CAP.

+1.2V_HT

250 mil
1
H_CADIP[0..15]

10 H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

10 H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15]
H_CADON[0..15]

10

C1
4.7U_0805_10V4Z

10

C2
4.7U_0805_10V4Z

C3
0.22U_0603_16V4Z

C4
0.22U_0603_16V4Z

C5
180P_0402_50V8J

C6
180P_0402_50V8J

Near CPU Socket

+1.2V_HT
JP1A

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT LINK

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

10
10
10
10

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

10
10
10
10

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AE2 +VLDT_B 1
C7
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

2
4.7U_0805_10V4Z

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

PWM Fan Control circuit

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

10
10
10
10

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

10
10
10
10

+5VS

JP2

VLDT=500mA

1
D1
CH751H-40PT_SOD323-2

C8
4.7U_0805_10V4Z

C9
@ 0.1U_0402_16V4Z

1
2

1
2

3
4

GND
GND

ACES_88231-02001
+VCC_FAN

6090022100G_B
1

1
2
5
6

CONN@
D Q1

@ D2

G
S

SI3456BDV-T1-E3_TSOP6

RLZ5.1B_LL34

FAN_PWM

41

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

JP1C

9 DDR_B_D[63..0]

MEM:DATA

DDR_A_CLK0
+1.8V

R1
1K_0402_1%

DDR_A_CLK#0

C10
1.5P_0402_50V9C

DDR_A_CLK1
1

R2
1K_0402_1%
1

C13
1000P_0402_25V8J

C12
0.1U_0402_16V4Z

+MCH_REF
1

DDR_A_CLK#1

C11
1.5P_0402_50V9C

DDR_B_CLK0
1

DDR_B_CLK#0

C14
1.5P_0402_50V9C

DDR_B_CLK1
1

DDR_B_CLK#1

C15
1.5P_0402_50V9C

+0.9V

+0.9V
JP1B

Place them close to CPU within 1"

+1.8V

R4
1
1
R3

39.2_0402_1%
2
2
39.2_0402_1%
T2

8
8

DDR_A_ODT0
DDR_A_ODT1

8 DDR_CS0_DIMMA#
8 DDR_CS1_DIMMA#

8 DDR_CKE0_DIMMA
8 DDR_CKE1_DIMMA

8 DDR_A_CLK0
8 DDR_A_CLK#0
8 DDR_A_CLK1
8 DDR_A_CLK#1
3

8 DDR_A_MA[15..0]

8 DDR_A_BS#0
8 DDR_A_BS#1
8 DDR_A_BS#2
8 DDR_A_RAS#
8 DDR_A_CAS#
8 DDR_A_WE#

PAD

DDR_A_ODT0
DDR_A_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

D10
C10
B10
AD10

VTT1
VTT2
VTT3
VTT4

AF10
AE10

MEMZP
MEMZN

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

H16

RSVD_M1

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22
J20

MA_CKE0
MA_CKE1

W10
AC10
AB10
AA10
A10

VTT_SENSE

Y10

MEMVREF

W17

VTT_SENSE

RSVD_M2

B18

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

DDR_B_ODT0
DDR_B_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

MB_CKE0
MB_CKE1

J25
H26

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

N19
N20
E16
F16
Y16
AA16
P19
P20

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

P22
R22
A17
A18
AF18
AF17
R26
R25

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

PAD

T1

PAD

T3

+MCH_REF

DDR_B_ODT0 9
DDR_B_ODT1 9
DDR_CS0_DIMMB# 9
DDR_CS1_DIMMB# 9
DDR_CKE0_DIMMB 9
DDR_CKE1_DIMMB 9

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

9
9
9
9
9 DDR_B_DM[7..0]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA[15..0] 9

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

DDR_B_BS#0 9
DDR_B_BS#1 9
DDR_B_BS#2 9
DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

DDR_A_D[63..0]

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

8
1

DDR_A_DM[7..0]

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

6090022100G_B

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

+2.5VDDA
VDDA=300mA
L1
3300P_0402_50V7K
1
2
1 FBM_L11_201209_300L_0805
1
1
1
+
4.7U_0805_10V4Z
C17
C18
C19
0.22U_0603_16V4Z
2
2
2
2

+2.5VS

+1.8V

R10
1
R5

2
10K_0402_5%
2
300_0402_5%
B

C16
@ 100U_D2_10VM

C20

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

LDT_RST#
H_PWRGD
LDT_STOP#
CPU_LDT_REQ#

R8
169_0402_1%
22 CLK_CPU_BCLK#

C21

2
3900P_0402_50V7K

Address:100_1100

+1.8VS

Place close to CPU wihtin 1.5"

2

R13
R14

+1.2V_HT

R15
300_0402_5%

26

+CPU_CORE_0
R487 10_0402_5%
1
2CPU_VDD0_FB_H
1
2CPU_VDD0_FB_L
R486 10_0402_5%

LDT_RST#

LDT_RST#
1

CPU_SIC
CPU_SID

C22
0.01U_0402_25V4Z
@

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

1
1

2
1
26

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

AF4
AF5
AE6

SIC
SID
ALERT_L

R6
P6

HT_REF0
HT_REF1

THERMTRIP_L
PROCHOT_L
MEMHOT_L

W7
W8

51 CPU_VDD1_FB_H
51 CPU_VDD1_FB_L

CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

+1.8VS

R25

2 0_0402_5%

DBRDY
TMS
TCK
TRST_L
TDI

AD7

TEST23

H10
G9

TEST18
TEST19

E9
E8
AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

R30
@ 300_0402_5%

+1.8VS

R36
300_0402_5%

11,26 LDT_STOP#
1

LDT_STOP#

PV:unmount R30 per AMD 4.1 change

CPU_LDT_REQ#

R6

R7

2
@ 0_0402_5%
2
0_0402_5%

ENTRIP2

47

H_THERMTRIP# 27,41

2
300_0402_5%
R11
1
2
@ 0_0402_5%

CPU_PROCHOT#_1.8

+1.8V

H_PROCHOT# 26

PV:change PROCHOT# & delete Q2

PAD
PAD

+CPU_CORE_NB

T22
T21

VDD_NB_FB_H
VDD_NB_FB_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

Close to CPU

J7
H8

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

R484 10_0402_5%
1
2
1
2
R485 10_0402_5%

VDD_NB_FB_H
VDD_NB_FB_L

VDD_NB_FB_H 51
VDD_NB_FB_L 51

PAD
PAD
PAD
PAD
PAD
PAD

T5
T6

route as differential
as short as possible
testpoint under package

T7
T8
T10
T12

+1.8V

0718 AMD --> 1K ohm

CPU_SVC
CPU_SVD

R22
R23

CPU_TEST27_SINGLECHAIN
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

PAD
PAD

T13
T14

H18
H19
AA7
D5
C5

6090022100G_B

1
1

2
1K_0402_5%
2
1K_0402_5%

1
R24

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST23_TSTUPD

CPU_LDT_REQ# 11,26

C24
0.01U_0402_25V4Z
@

1
R9

+1.8V

THERMDC_CPU
THERMDA_CPU

DBREQ_L

TEST28_H
TEST28_L

TEST25_H
TEST25_L

C2
AA6

+1.8V sense no support

W9
Y9

G10
AA9
AC9
AD9
AF9

CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
2
1
R48
300_0402_5%

AF6
AC7
AA8

THERMDC
THERMDA

Q3
1

CPU_SVC 51
CPU_SVD 51

C23
@ 0.1U_0402_16V4Z

B7
A7
F10
C6

CPU_SVC
CPU_SVD

A6
A4

VDDIO_FB_H
VDDIO_FB_L

CPU_TEST23_TSTUPD

H_PWRGD

H_PWRGD

SVC
SVD

VDD0_FB_H
VDD0_FB_L

CPU_TEST19_PLLTEST0
+1.8V
CPU_TEST18_PLLTEST1
R493@ 510_0402_5%
1
2 CPU_TEST25_H_BYPASSCLK_H
1
2 CPU_TEST25_L_BYPASSCLK_L
R492@ 510_0402_5%
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

R488 10_0402_5%

KEY1
KEY2

F6
E6

R21
300_0402_5%

CLKIN_H
CLKIN_L

51 CPU_VDD0_FB_H
51 CPU_VDD0_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

+CPU_CORE_1
R489 10_0402_5%
1
2CPU_VDD1_FB_H
1
2CPU_VDD1_FB_L

VDDA1
VDDA2

A9
A8

MMBT3904_NL_SOT23-3

M11
W18

CPU_VDD0_FB_H
CPU_VDD0_FB_L

Close to CPU
+1.8VS

F8
F9

CPU_THERMTRIP#_R

22 CLK_CPU_BCLK

JP1D

SI2: remove 100uF

2
300_0402_5%

1
R26 2
R27 2
R28 2
R29 2
R31 2
R32 2
R33 2
R34 2
R35 2
R49

2
1
1
1
1
1
1
1
1
1

300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%
300_0402_5%

PV:AMD 4.1 recommend

C25
0.01U_0402_25V4Z
@
1

@ C939 0.1U_0402_16V4Z
R175

R814
1

2.09V for Gate

+1.8V

1
D

PV:change to 2.2K

Q127

@ FDV301N_NL_SOT23-3

R19

EC is PU to 5VALW
G

CPU_SIC

2
1
2.2K_0402_5%

+1.8V

+3VS

0.1U_0402_16V4Z
C27
1

2200p change to
1000p for ADT7421

Q129

C26

FDV301N, the Vgs is:

min = 0.65V
Typ = 0.85V
Max = 1.5V

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

SMB_EC_CK1 40,41,42,45

SMB_EC_DA1 40,41,42,45

@ FDV301N_NL_SOT23-3

HDT Connector
JP3
1
3
5
7
9
11
13
15
17
19
21
23

2
U2
1
THERMDA_CPU 2

THERMDC_CPU 3
2
2200P_0402_50V7K
4

VDD

SCLK

SMB_EC_CK2
SMB_EC_DA2

D+

SDATA

D-

ALERT#

GND

THERM#

+3VS

U1
HDT_RST#

CONN@ SAMTEC_ASP-68200-07

LDT_RST#
SB_PWRGD 27,41,51 4

@ NC7SZ08P5X_NL_SC70-5

SMB_EC_DA2 21,41

Compal Secret Data

Security Classification
2007/08/02

Issued Date

ADM1032ARMZ-2REEL_MSOP8

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Address:100_1101

NOTE: HDT TERMINATION IS REQUIRED

FOR REV. Ax SILICON ONLY.

SMB_EC_CK2 21,41

2
4
6
8
10
12
14
16
18
20
22
24
26

CPU_SID

2
1
2.2K_0402_5%

+1.8V

@ 34.8K_0402_1%~N

@ 20K_0402_5%
R18

2
1
@ 220_0402_5% R37
2
1
@ 220_0402_5% R38
2
1
@ 220_0402_5% R39
2
1
@ 220_0402_5% R40
2
1
300_0402_5% R41

+3VS

Title

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

JP1F

VDD(+CPU_CORE) decoupling.
+CPU_CORE_0

+CPU_CORE_1

C30
330U_X_2VM_R6M

C28
330U_X_2VM_R6M

C31
330U_X_2VM_R6M

C29
330U_X_2VM_R6M

Near CPU Socket

+CPU_CORE_0

+CPU_CORE_1
+CPU_CORE_NB

C32
22U_0805_6.3V6M

C33
22U_0805_6.3V6M

C34
22U_0805_6.3V6M

C35
22U_0805_6.3V6M

C36
22U_0805_6.3V6M

C37
22U_0805_6.3V6M

+CPU_CORE_0

C38
22U_0805_6.3V6M

C39
22U_0805_6.3V6M

+1.8V

+CPU_CORE_1

C40
0.22U_0603_16V4Z

C41
0.01U_0402_25V4Z

JP1E

+CPU_CORE_0

C42
180P_0402_50V8J

C43
0.22U_0603_16V4Z

C44
0.01U_0402_25V4Z

C45
180P_0402_50V8J

Under CPU Socket

2

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE_1

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

6090022100G_B
Athlon 64 S1
Processor Socket

VDDIO decoupling.
+CPU_CORE_NB

decoupling.

+1.8V
+CPU_CORE_NB
1

C46
22U_0805_6.3V6M

C47
22U_0805_6.3V6M

C48

0.22U_0603_16V4Z
2

C49

0.22U_0603_16V4Z
2

C50

C51

180P_0402_50V8J 180P_0402_50V8J
2
2

C52
22U_0805_6.3V6M

C53
22U_0805_6.3V6M

C54
@ 22U_0805_6.3V6M

SI2: reserve 22u

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

6090022100G_B

Under CPU Socket

Athlon 64 S1
Processor Socket

Between CPU Socket and DIMM

+1.8V

+0.9V

C55
0.22U_0603_16V4Z

C56
0.22U_0603_16V4Z

C57
0.22U_0603_16V4Z

+1.8V

C60
0.01U_0402_25V4Z

C61
0.01U_0402_25V4Z

C58
0.22U_0603_16V4Z

C62
180P_0402_50V8J

C63
180P_0402_50V8J

C64
180P_0402_50V8J

+0.9V

C65
1
180P_0402_50V8J C66
4.7U_0805_10V4Z

A: Add C165 and C176

to follow AMD Layout
review recommand for
EMI

+1.8V

C: Change to NBO CAP

180PF Qt'y follow the distance between

CPU socket and DIMM0. <2.5inch>

Near Power Supply

1

+ C59
220U_Y_4VM

+1.8V

VTT decoupling.

C67
4.7U_0805_10V4Z

C68
0.22U_0603_16V4Z

C69
0.22U_0603_16V4Z

C70
1000P_0402_25V8J

C71
1000P_0402_25V8J

C72
180P_0402_50V8J

C73
180P_0402_50V8J

Near CPU Socket Right side.

+0.9V

1
1

1
C74
4.7U_0805_10V4Z

1
C75
4.7U_0805_10V4Z

1
C76
4.7U_0805_10V4Z

C77
4.7U_0805_10V4Z

C: Change to NBO CAP

+ C78
220U_Y_4VM
2 @

C79
4.7U_0805_10V4Z

C80
4.7U_0805_10V4Z

C81
0.22U_0603_16V4Z

C82
0.22U_0603_16V4Z

C83
1000P_0402_25V8J

C84
1000P_0402_25V8J

C85
180P_0402_50V8J

C86
180P_0402_50V8J

Near CPU Socket Left side.

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

+V_DDR_MCH_REF
+1.8V

DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
1

DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_D4
DDR_A_D5

DDR_A_D[0..63]
DDR_A_DM[0..7]

DDR_A_DM0
DDR_A_DQS[0..7]
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_MA[0..15] 5

DDR_A_DQS#[0..7]

DDR_A_DQS#[0..7]

+1.8V

DDR_A_MA0
DDR_A_BS#1
DDR_A_MA2
DDR_A_MA4

DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
2

DDR_CKE0_DIMMA

5 DDR_CKE0_DIMMA

DDR_A_BS#2

5 DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

5 DDR_A_BS#0
5 DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

5 DDR_A_CAS#
5 DDR_CS1_DIMMA#

DDR_A_ODT1

5 DDR_A_ODT1

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
3

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
9,22,27,35 SMB_CK_DAT0
9,22,27,35 SMB_CK_CLK0
+3VS
4

1
C103
0.1U_0402_16V4Z

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

R43
1K_0402_1%
+V_DDR_MCH_REF

DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

+V_DDR_MCH_REF 9

R44
1K_0402_1%

DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA 5

DDR_A_ODT0
DDR_A_MA13

C90
C89

C91
C92

47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4

C93
C94

1
1

1
1

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_WE#
DDR_A_CAS#

47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4

1
C100
1
C99

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#
DDR_CS0_DIMMA#

47_0804_8P4R_5%
RP7
1
8
2
7
3
6
4
5

1
C102
1
C101

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

C98
C97

1
1

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5
DDR_A_ODT0 5

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1 5
DDR_A_CLK#1 5
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

P-TWO_A5692B-A0G16-P
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

C88

DDR_A_BS#0
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

C87

47_0804_8P4R_5%
RP3
1
8
2
7
3
6
4
5

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_D20
DDR_A_D21

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_A_D18
DDR_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

C96
0.1U_0402_16V4Z

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

8
7
6
5

47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA15
DDR_CKE1_DIMMA

DDR_A_CLK0 5
DDR_A_CLK#0 5

C95
1000P_0402_25V8J

DDR_A_D16
DDR_A_D17

1
2
3
4

DDR_A_DM1

DDR_A_D14
DDR_A_D15

+1.8V

+0.9V
RP1
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14

DDR_A_D10
DDR_A_D11

+1.8V

JP4

Title

Compal Electronics, Inc.

DDRII SO-DIMM 0

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

+1.8V
+1.8V

JP5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

8 +V_DDR_MCH_REF

C104
1000P_0402_25V8J

DDR_B_D0
DDR_B_D1
1

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

5 DDR_CKE0_DIMMB
5 DDR_B_BS#2

DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

5 DDR_B_BS#0
5 DDR_B_WE#
5 DDR_B_CAS#
5 DDR_CS1_DIMMB#
5 DDR_B_ODT1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
8,22,27,35 SMB_CK_DAT0
8,22,27,35 SMB_CK_CLK0
+3VS
4

C119
0.1U_0402_16V4Z

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_DM0
DDR_B_D6
DDR_B_D7

DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]

DDR_B_D12
DDR_B_D13

DDR_B_D[0..63]

RP8

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_BS#1
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6

1
2
3
4

8
7
6
5

2
C105
1
C106

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C108
1
C107

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C109
1
C110

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C111
1
C112

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C114
1
C113

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C116
1
C115

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C118
1
C117

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
1

RP9

DDR_B_DM1

DDR_B_MA4
DDR_B_MA14
DDR_B_MA7
DDR_B_MA11

1
2
3
4

DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
DDR_B_MA15

8
7
6
5

8
7
6
5

47_0804_8P4R_5%

DDR_B_CLK0 5
DDR_B_CLK#0 5

RP10

DDR_B_D14
DDR_B_D15

1
2
3
4

47_0804_8P4R_5%
DDR_B_D20
DDR_B_D21

RP11
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_DM2
DDR_B_D22
DDR_B_D23

8
7
6
5

1
2
3
4

47_0804_8P4R_5%

DDR_B_D28
DDR_B_D29

RP12
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA3
DDR_B_MA1

DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
2

RP13
DDR_CKE1_DIMMB

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_CKE1_DIMMB 5

DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_ODT0
DDR_B_MA13

1
2
3
4

RP14

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

8
7
6
5

47_0804_8P4R_5%
DDR_B_MA13
DDR_B_ODT0
DDR_B_RAS#
DDR_CS0_DIMMB#

1
2
3
4

8
7
6
5

47_0804_8P4R_5%

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5
DDR_B_ODT0 5

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
3

DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1 5
DDR_B_CLK#1 5
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS

PTI_A5652D-A0G16-P
2

CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+1.8V

+0.9V
DDR_B_D[0..63]
DDR_B_D4
DDR_B_D5

Title

Compal Electronics, Inc.

DDRII SO-DIMM 1

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

of

53

15 PCIE_GTX_C_MRX_P[0..15]
15 PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] 15
PCIE_MTX_C_GRX_N[0..15] 15

U3B

33
33
34
34
33
33
32
32

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3

33 PCIE_PTX_C_IRX_P5
33 PCIE_PTX_C_IRX_N5
26
26
26
26
26
26
26
26

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

C152
C153
C154
C155
C156
C157
C158
C159

PCIE_ITX_PRX_P5
PCIE_ITX_PRX_N5

C160 1
C161
1

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R55
R56

C121 1
C123 1

C125 1

C127 1

C129 1

C131 1

C133 1

C135 1

C137 1

C139 1

C141 1

C143 1

C145 1

C147 1

C149 1

C151 1

C162
C163
C164
C165
C166
C168
C169
C167

1
1
1
1
1
1
1
1

1
1

2
2

C120 1
0.1U_0402_16V7K
C122 1
0.1U_0402_16V7K
C124 1
0.1U_0402_16V7K
C126 1
0.1U_0402_16V7K
C128 1
0.1U_0402_16V7K
C130 1
0.1U_0402_16V7K
C132 1
0.1U_0402_16V7K
C134 1
0.1U_0402_16V7K
C136 1
0.1U_0402_16V7K
C138 1
0.1U_0402_16V7K
C140 1
0.1U_0402_16V7K
C142 1
0.1U_0402_16V7K
C144 1
0.1U_0402_16V7K
C146 1
0.1U_0402_16V7K
C148 1
0.1U_0402_16V7K
C150 1
0.1U_0402_16V7K

2
1

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2

1
1

PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3

2
1

1
1
1
1

2
2
2
2
2
2
2
2

1.27K_0402_1%
2K_0402_1%

Polarity inversion

Polarity inversion

Polarity inversion

New Card

33
33
34
34
33
33
32
32

Cardreader

GLAN

PCIE_ITX_C_PRX_P5 33
PCIE_ITX_C_PRX_N5 33
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

TV Tuner

4 H_CADON[0..15]

26
26
26
26
26
26
26
26

H_CADOP[0..15]

H_CADIP[0..15]

H_CADON[0..15]

H_CADIN[0..15]

H_CADIP[0..15]

H_CADIN[0..15]

U3A

+1.1VS

RS780M_FCBGA528
RS780M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
3

WLAN

4 H_CADOP[0..15]

0.1U_0402_16V7K
2 0.1U_0402_16V7K

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

GFX_TX4,TX5,TX6 and TX7

DP1
AUX1 and HPD1

4
4
4
4

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

4
4
4
4

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1 R57

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

M22
M23
R21
R20

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

2 301_0402_1% C23
A24

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GFX

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

RS780M_FCBGA528

0718 Place within 1"

layout 1:2

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

4
4
4
4

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

4
4
4
4

1 R58

2 301_0402_1%

0718 Place within 1"

layout 1:2

NEED CHECK R68 & R69 WITH AMD

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780-HT/PCIE

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

10

of

53

PV: follow check list connect to GND

U3C

RX781GND

F12
E12
F14
G15
H15
H14

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

E17
F17
F15

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

G18
G17
E18
F18
E19
F19

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

A11
B11
F8
E8

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

PV: follow check list connect to GND

+1.8VS

+VDDA18HTPLL
L10
1
2
BLM18PG121SN1D_0603
1

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

+VDDA18HTPLL

H17

VDDA18HTPLL

+VDDA18PCIEPLL

D7
E7

VDDA18PCIEPLL1
VDDA18PCIEPLL2

D8
A10
C10
C12

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

C25
C24

HT_REFCLKP
HT_REFCLKN

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

RX781GND
+1.8VS

+VDDA18PCIEPLL

L11
1
2
BLM18PG121SN1D_0603
C180
2.2U_0603_6.3V4Z

1
14,15,26,32,33,34,40,41

R67
1

0_0402_5%
2
27 NB_PWRGD
6,26 LDT_STOP#
6,26 CPU_LDT_REQ#

PLT_RST#

+1.8VS
2 NB_PWRGD
300_0402_5%

1
R371

22
22

NB_RESET#
NB_PWRGD

CLK_NBHT
CLK_NBHT#

22 NB_OSC_14.318M

For SB700 A12 use

+1.1VS

1
2
R71
4.7K_0402_5%

1
2
R72
4.7K_0402_5%

22 NBGFX_CLK
22 NBGFX_CLK#

22 CLK_SBLINK_BCLK
22 CLK_SBLINK_BCLK#

+3VS
R88
14

1
10K_0402_5%

AUX_CAL

Strap pin

T2
T1

GFX_REFCLKP
GFX_REFCLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

RX781GND

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

RX781GND

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

TMDS_HPD(NC)
HPD(NC)

D9
D10

PLL PWR
LVTM

A12
2
1
R251 0_0402_5% D14
B12

A22
B22
A21
B21
B20
A20
A19
B19

PM

C179
2.2U_0603_6.3V4Z

14 UMA_HSYNC
14 UMA_VSYNC

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

CRT/TVOUT

1RX781GND
0_0402_5%

2
R250

1
0_0402_5%

CLOCKs

2
R249
RX781GND

MIS.

SUS_STAT#(PWM_GPIO5)

D12

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

D13

AUX_CAL(NC)

PV: follow check list connect to GND

1
R77

2
0_0402_5%

SUS_STAT# 27
SUS_STAT_R# 14

Strap pin

1
2
R80
1.8K_0402_5%

RS780M_FCBGA528

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

11

of

53

U3D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

SBD_MEM/DVO_I/F

PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

MEM_COMPP(NC)
MEM_COMPN(NC)

+1.8VS
+1.1VS

RS780M_FCBGA528

Compal Secret Data

Security Classification
Issued Date

2007/08/02

Deciphered Date

2008/08/02

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Compal Electronics, Inc.

RS780 SIDE PORT

Size Document Number

Custom
LA-4092P
Date:

Thursday, February 21, 2008

Rev
0.4
Sheet

12

of

53

U3F

+VDDHT

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L22
1
0_0805_5%

2A

+VDDA18PCIE

1
C235
4.7U_0805_10V4Z

1
C246

1
C236

1
C237

1
C238

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

1
C239

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

F9
G9
AE11
AD11

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

+1.8VS

C251
1U_0402_6.3V4Z

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)

+1.1VS

+NB_VDDC

PAD-OPEN 4x4m

VDD_CORE=10A

1
+
2

330U_D2E_2.5VM

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

C234

+1.8VS

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

C245

C233

10U_0805_10V4Z

C225
C226
C227
C228
C229
@ FBMA-L11-201209-221LMA30T_0805
2
2
2
2
2
L43

C232

PJP3

10U_0805_10V4Z

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C244

1
+1.35VS

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

2
2
2
2
1
1

0.1U_0402_16V4Z

+VDDHTTX

2A

1
0_0805_5%

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

1
1
1
1
2
2

C231

0.1U_0402_16V4Z

L19
2

+1.2V_HT

H18
G19
F20
E21
D22
B23
A23

C220
C219
C222
C221
C224
C223

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

10U_0805_10V4Z

C212

C230

C218

10U_0805_10V4Z

C211

0.1U_0402_16V4Z

C217

2
2
0.1U_0402_16V4Z

+1.1VS

+VDDA11PCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

C243

C216
2

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

0.1U_0402_16V4Z

C214

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

C242

C215

10U_0805_10V4Z

J17
K16
L16
M16
P16
R16
T16

0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHTRX
2
1 2A
0_0805_5%
1
1
1
1
L18

PV:Change C215 from 4.7u to 10u

L17
1
2
FBMA-L11-201209-221LMA30T_0805

VDDA_12=2.5A

U3E

C241

0.1U_0402_16V4Z

1
C210

C240

1
C208

0.1U_0402_16V4Z

1
C207

C247

1
C206

0.1U_0402_16V4Z

1
C209

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

PART 6/6

GROUND

2A
1

0.1U_0402_16V4Z

L16
2
0_0805_5%

+1.1VS

POWER

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M_FCBGA528

AE10
AA11
Y11
AD10
AB10
AC10
H11
H12

+3VS

RS780M_FCBGA528
R252
0_0402_5%

2
3

PV: follow check list connect to GND

+1.8VS

U67

C903
@ 10U_0805_10V4Z

VCNTL

GND

NC

R599
1K_0402_1%

VREF

NC

VOUT

NC

TP

VIN

+3VS

C489
@ 1U_0603_10V6K

@ G2992F1U_SO8
+VREF1.35V
+1.35VS

Q56
@ 2N7002_SOT23-3
4

1
R601

2
@ 0_0402_5%

2
G
2

R600
@ 3K_0402_5% 2

C703
@ 0.1U_0402_16V7K

1
C702

VLDT_EN#

44

C905
2 @ 10U_0805_10V4Z

@ 0.1U_0402_16V7K

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 PWR/GND

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

13

of

53

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

RS780 DFT_GPIO5 mux at CRT_VSYNC pull high to 3K

SI2: Change to 3K pull high
2
R101
2
R102

11 UMA_VSYNC

1
3K_0402_5%
1
@ 3K_0402_5%

Enables the Test Debug Bus using GPIO.

1 : Enable (RX780, RS780)
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

+3VS

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These
000 :
001 :
010 :
011 :
100 :
101 :
111 :

RS780 use register to control PCI-E configure

pin straps are used to configure PCI-E GPP mode.

00001
00010
01011
00100
01010
01100
01011

DFT_GPIO1: LOAD_EEPROM_STRAPS
1
@R104
@
R104

11 AUX_CAL

RS780 DFT_GPIO1

D4
2

11 SUS_STAT_R#

2
150_0402_1%
@ CH751H-40PT_SOD323-2
1

PLT_RST#

Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
11,15,26,32,33,34,40,41 default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RS780 use HSYNC to enable SIDE PORT (internal pull high)

11 UMA_HSYNC

2
R107

1
@ 3K_0402_5%

2
R125

1
3K_0402_5%

RX780: Enables the Test Debug Bus using PCIE bus

1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780)
0 : Enable (RS780)

+3VS

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

RS780 STRAPS

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

14

of

53

PCIE_GTX_C_MRX_P[0..15]

10 PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

10 PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

10 PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

10 PCIE_MTX_C_GRX_N[0..15]

U5A
PART 1 OF 6

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

AC30
AC31

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AA28
AA27

PEG_M_RXP15
PEG_M_RXN15

C284 1
C285 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

AC29
AB29

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AA25
AA24

PEG_M_RXP14
PEG_M_RXN14

C282 1
C283 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

AB31
AB30

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

Y28
Y27

PEG_M_RXP13
PEG_M_RXN13

C280 1
C281 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

AA31
AA30

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

Y25
Y24

PEG_M_RXP12
PEG_M_RXN12

C278 1
C279 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

W30
W31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

V28
V27

PEG_M_RXP11
PEG_M_RXN11

C276 1
C277 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

W29
V29

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

V25
V24

PEG_M_RXP10
PEG_M_RXN10

C274 1
C275 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

V31
V30

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

T28
T27

PEG_M_RXP9
PEG_M_RXN9

C272 1
C273 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

U31
U30

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

T25
T24

PEG_M_RXP8
PEG_M_RXN8

C270 1
C271 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

P30
P31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

P28
P27

PEG_M_RXP7
PEG_M_RXN7

C268 1
C269 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

P29
N29

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

P25
P24

PEG_M_RXP6
PEG_M_RXN6

C266 1
C267 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

N31
N30

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

M28
M27

PEG_M_RXP5
PEG_M_RXN5

C264 1
C265 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

M31
M30

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

M25
M24

PEG_M_RXP4
PEG_M_RXN4

C262 1
C263 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

K30
K31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

L28
L27

PEG_M_RXP3
PEG_M_RXN3

C260 1
C261 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

K29
J29

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

L25
L24

PEG_M_RXP2
PEG_M_RXN2

C258 1
C259 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

J31
J30

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

J28
J27

PEG_M_RXP1
PEG_M_RXN1

C256 1
C257 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

H31
H30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

G28
G27

PEG_M_RXP0
PEG_M_RXN0

C254 1
C255 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0

PCIE LANE REVERSAL

P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E

PCIE LANE REVERSAL

Clock
AD29
AD30

22 CLK_PCIE_VGA
22 CLK_PCIE_VGA#

11,14,26,32,33,34,40,41

PLT_RST#

PCIE_REFCLKP
PCIE_REFCLKN
SM BUS

AC28
AC27

NC_SMBCLK
NC_SMBDATA

AG25

PERSTB

Calibration
PCIE_CALRN

AF25

R108 1

2K_0402_1%

PCIE_CALRP

AE25

R109 1

1.27K_0402_1%

NC
NC

AE23
AH30

+1.1VS

216-0707001-00/M82-S_BGA632

Compal Secret Data

Security Classification
2006/09/25

Issued Date

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S PCIE interface

Size

Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

15

of

53

BLM18PG121SN1D_0603
2
1
L23

1U_0402_6.3V4Z

+VGA_CORE

+MPVDD
1

C294

2
0.1U_0402_16V4Z

AL5
AK5

AK8
AL8

BLM18PG121SN1D_0603
L26
0.1U_0402_16V4Z +DPLL_PVDD
2
1
1
1
1
+1.8VS
C291
1U_0402_6.3V4Z
C290
C299
2
2
2
10U_0603_6.3V6M

21

PSYNC

10U_0603_6.3V6M

BLM18PG121SN1D_0603
R115
0.1U_0402_16V4Z +DPLL_VDDC
2
1
+1.1VS
1
1
1
C310
C311
C312
1U_0402_6.3V4Z
2
2
2
10U_0603_6.3V6M

21
21
21
21

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

TX0M_DPB1P
TX0P_DPB1N

TX1M_DPA2P
TX1P_DPA2N

TX1M_DPB2P
TX1P_DPB2N

TX2M_DPA3P
TX2P_DPA3N

TX2M_DPB3P
TX2P_DPB3N

41

+VGA_VREF

1
10K_0402_5%

SI2:unmount R188

C325
0.1U_0402_16V4Z

R188

+3.3V_DELAY

R136
249_0402_1%

21
21
21

ENBKL

1
@ 10K_0402_5%

52 VGA_PWRSEL
22 27M_SSC
21 THM_ALERT#

1
R625

21
21
21
21
21
21

SOUT_GPIO8
SIN_GPIO9
SCLK
GPIO11
GPIO12
GPIO13
27M_SSC_R

2
0_0402_5%

VGA_CTF

2
1
@ 10K_0402_5% R127
B

21 SCS#_GPIO22
+3.3V_DELAY

1VGA_CLKREQ#
1 10K_0402_5%
1K_0402_5%
T35
T36
T37
T38

2
R130 2
R131

SI: Per EMI request add SSC chip

TMDS_SSCOUT
TMDS_CLKIN

Spread spectrum
U4
27M_OUT

REFOUT

VSS

DVPCNTL_MVP_0
DVPCNTL_MVP_1

DPA_VDDR
DPA_VDDR

AJ12
AJ13

V2
V1
W3

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2

DPB_VDDR
DPB_VDDR

AK13
AL13

W1

DVPCLK

R630
0_0402_5%

27M_CLK

22

XOUT MODOUT

XIN

VDD

2 27M_SSC_R
@ 33_0402_5%

1
R178

120mA

@ 0.1U_0402_16V4Z

C463
1U_0402_6.3V4Z
@

40mA
230mA
300mA

75_0402_1%
27M_OUT
1
2
R177

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11 EXT TMDS
DVPDATA_12 DVO
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

AL12
AK12
AJ11
AH9
AH11

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

AJ8
AF7
AG7
AJ7
AH7

DP_CALR
HPD1

Y6
OUT

IN

GND

XTALOUT

R142
1K_0402_5%
1

27MHz_16PF_6P27000126

@
CV2
2 22P_0402_50V8J

@
GND

PCIE_PVDD

A9
B9

MPVDD
MPVSS

AE12

DPLL_VDDC

AJ31

XTALIN

AJ30

XTALOUT

R189
100_0402_5%

XTALOUT

AH31

AH26

TESTEN

AD12

PLLTEST

G
GB

GREEN
BLUE

RSET

AJ28

AVDD

AL29

AVSSQ

AH28

VDD1DI

AJ27

VSS1DI

AJ26

R2
R2B

AL17
AK17

G2
G2B

AL15
AK15

GREEN

23

BLUE

AF23
AF21
AL18
AJ22
AJ25
AK18
AK23
AK25
AJ21
AL23
AL25

LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR

+1.8VS

C599

40mA
2
1
+1.1VS
L27
BLM18PG121SN1D_0603

C302

AG18
AH18

LPVDD
LPVSS

C292

200mA

1
2

C293
2

+1.1VS

L28
BLM18PG121SN1D_0603

C303

C304
2
1U_0402_6.3V4Z

2
10U_0603_6.3V6M

23

GREEN
BLUE

CRT_HSYNC 21,23
CRT_VSYNC 23
1
2
R119 499_0402_1%

100mA

+VDD1DI

1
C316

1U_0402_6.3V4Z
2

1
C317

C318
10U_0603_6.3V6M

1U_0402_6.3V4Z
2

1
L31
BLM18PG121SN1D_0603

U70
TMDS_CLKIN R182 1

CLKIN

VDD

8
7

R627 1

2 @ 0_0402_5%

SR1

ModOUT

VSS

SSON#

1
2
C500 @ 0.1U_0402_16V4Z
R629 1
2 @ 0_0402_5%
R183 1

2 @ 33_0402_5% TMDS_SSCOUT

SI: Per EMI request add SSC chip @ P2040CF-08TR_TSSOP8

COMP

AJ14

V2SYNC
H2SYNC

AE16
AF16

A2VDD

AH14

+A2VDD

A2VDDQ

AH16

+A2VDDQ

A2VSSQ

AG16

Pin 5 have internal pull low

135mA
2mA
1

1
C322

1
C323

2
2
10U_0603_6.3V6M

AF18

L33
2

0_0603_5%
1
+1.8VS

C319

L32
2

C320

2
2
0.1U_0402_16V4Z

C324
2

10U_0603_6.3V6M
1
1

0_0603_5%
1
+3.3V_DELAY

C321
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
1
R135

2
715_0402_1%

SI: Per AMD request cahnge to +3.3V_DELAY

LCD_DDC_CLK
LCD_DDC_DAT

LCD_DDC_CLK 24
LCD_DDC_DAT 24

+3.3V_DELAY

LCD

AJ29
AH29

LCD_DDC_CLK

1
R241
1
R242
1
R243
1
R244
1
R245
1
R246

LCD_DDC_DAT

AC5
AC4

DDC3DATA_DP3_AUXN
DDC3CLK_DP3_AUXP

AF4
AH4

VGA_DDC_DAT
VGA_DDC_CLK

DDC4DATA_DP4_AUXN
DDC4CLK_DP4_AUXP

AF9
AG9

HDMIDAT_VGA
HDMICLK_VGA

VGA_DDC_DAT

D+
D-

21
21

VGA_DDC_DAT 23
VGA_DDC_CLK 23

CRT

HDMIDAT_VGA 25
HDMICLK_VGA 25

HDMI

VGA_DDC_CLK
HDMIDAT_VGA
HDMICLK_VGA

2
4.7K_0402_5%
2
4.7K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

SI2: change from 4.7K to 10K

thermal
Compal Secret Data

Security Classification
Issued Date

2006/09/25

2006/09/25

Deciphered Date

Title

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C314

+3VS

2 @ 33_0402_5% 1

AJ15

AE5
AE4

2
1
+1.8VS
L30
BLM18PG121SN1D_0603
C315
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
1

2
2
0.1U_0402_16V4Z

AJ17

DPLUS
DMINUS

2
1
+1.8VS
L29
BLM18PG121SN1D_0603

2
0.1U_0402_16V4Z

C313

+1.8VS

AE14

+LPVDD
1

100mA

+AVDD

TS_FDO

LVDS_ACLK+ 24
LVDS_ACLK- 24
LVDS_A0+ 24
LVDS_A0- 24
LVDS_A1+ 24
LVDS_A1- 24
LVDS_A2+ 24
LVDS_A2- 24

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

SR0

DDC1CLK

AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22

1
R116
1
R117
1
R118

MRA

AA5
AA4

TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

C306

AE18

LVDS_BCLK+ 24
LVDS_BCLK- 24
LVDS_B0+ 24
LVDS_B0- 24
LVDS_B1+ 24
LVDS_B1- 24
LVDS_B2+ 24
LVDS_B2- 24

C305

2 @ 0_0402_5%

AG14

TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23

10U_0603_6.3V6M
1

R626 1

R2SET

VGA_ENVDD 24

LVDS channel

VSS2DI

T44 PAD

AA7
AC6

216-0707001-00/M82-S_BGA632

2
10U_0603_6.3V6M

RED

DDC2DATA
DDC2CLK

THERMAL

23

LVDDC
LVDDC

AL14
AK14

SERIAL
BUSES DDC1DATA

TEST

RED

2
0.1U_0402_16V4Z

200mA

1U_0402_6.3V4Z
1
1

AJ18
AH20

2 10U_0603_6.3V6M

C301
2

0.1U_0402_16V4Z

25

+LVDDC
C288

L41
2
1
1 BLM18PG121SN1D_0603

C597

VARY_BL
Control
DIGON

B2
B2B

SCL
SDA

216-0707001-00/M82-S_BGA632
@
CV1
22P_0402_50V8J

+DPB_VDDR

RED

AK29
AK30

C300
2

AL27
AK27

VDD2DI

PLL &
XTAL

0.1U_0402_16V4Z

AL28
AK28

AL26
AK26

C298
+DPB_PVDD 1U_0402_6.3V4Z
2 10U_0603_6.3V6M
1
1

LVDDR
LVDDR

80mA

SI2: Add C598,C597,C599,L41 for AMD request

C289

HPD

PART 6 OF 6

AF20
AG20

C296

10U_0603_6.3V6M
2
L25
2
1
+1.8VS
1 BLM18PG121SN1D_0603

2
2
0.1U_0402_16V4Z

150_0402_1%
2

2
0.1U_0402_16V4Z

C295

1U_0402_6.3V4Z
+DPA_VDDR
1
1

R112
1

U5F

320mA
C391

1U_0402_6.3V4Z
1

1
2
L24
1
BLM18PG121SN1D_0603

C598

R
RB

VREFG
DPLL_PVDD
DPLL_PVSS

C297

AA8

B
BB

DAC2 (TV/CRT2)

1U_0402_6.3V4Z
1
1

2
2
0.1U_0402_16V4Z

AG11

HSYNC
VSYNC

DAC1 / CRT

GEN_A
GEN_B
GEN_C
GEN_D_HPD4
GEN_E

AH12
AG12

+MPVDD
+DPLL_VDDC

GPIO_0
GPIO_1
GPIO_2
GENERAL
GPIO_3
PURPOSE
GPIO_4
I/O
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_24_JMODE
GPIO_25_TDI
GPIO_26_TCK
GPIO_27_TMS
GPIO_28_TDO

27MCLK

+PCIE_PVDD

27MCLK
2

VGA input level is 1.8V

+DPLL_PVDD

+3VS

C462

ASM3P2872A

Y8
Y7
V8
AH6
AG6

+VGA_VREF AC11

PAD
PAD
PAD
PAD

HDMI_TX2-_VGA 25
HDMI_TX2+_VGA 25

40mA

+DPB_PVDD

Y4
V3
V4
V5
U3
U2
T4
T5
T7
T8
R1
R2
R3
P1
P3
N1
N2
P4
P7
P8
P5
V7
N3
Y5
M4
M5
M7
M8
L8

GPIO4
GPIO5
GPIO6

AL11
AK11

AE11
AF11

PSYNC_NEW

R120

HDMI_TX1-_VGA 25
HDMI_TX1+_VGA 25

DPB_PVDD
DPB_PVSS

DVALID

AE7

GPIO0
GPIO1

AL10
AK10

21
21

+1.8VS

+LVDDR
1

C389

2
10U_0603_6.3V6M

HDMI_TX0-_VGA 25
HDMI_TX0+_VGA 25

DPA_PVDD
DPA_PVSS

+1.8VS

R132
499_0402_1%

AJ9
AJ10

+DPA_PVDD

Y1
Y2
Y3
AA2
AA3
AB1
AB2
AB3
AC1
AC3
AD1
AD2
AD3
AF3
AG3
AH3
AG1
AH2
AH1
AJ3
AJ1
AJ2
AK2
AK3

TX0M_DPA1P
TX0P_DPA1N

C390

HDMI_CLK-_VGA 25
HDMI_CLK+_VGA 25

AL7
AK7

AK4
AL3

0.1U_0402_16V4Z +PCIE_PVDD
1
1
1
C307
C309
1U_0402_6.3V4Z
C308

R110

TXCM_DPB0P
INTEGRATED
TMDS/DP PORT TXCP_DPB0N

AD9

BLM18PG121SN1D_0603
+1.8VS

TXCM_DPA0P
TXCP_DPA0N

AK9
AL9

1U_0402_6.3V4Z
1

1
2
L40
1
BLM18PG121SN1D_0603

PART 2 OF 6

AL6
AK6

+1.8VS

U5B
AJ4
AJ5

C287

C286
2
2
10U_0603_6.3V6M

polarity swap for ATI commond

Size

Compal Electronics, Inc.

M82-S CRT/LVDS/TV-OUT
Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

16

of

53

U5C
Part 3 of 6

19

MDA[31..0]

MDA[63..32]

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[31..0]

+1.8VS

R143
100_0402_1%

E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19
C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5
F5
G4
F4
B3
B2
C2
C1
E3
F3
F2
F1
G2
G1
H3
H2
K2
L3
L2
L1

R144
100_0402_1%

F30
F31

C328
0.1U_0402_16V4Z

L5
L7
J7
R145

B14
A14
B13
E14
B17
A17
C15
G16
E16
C14
A12
B12
C12
D14
B15
G14

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
BA0
BA1
MAA12
BA2

DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7

D30
G25
C26
C21
C5
D6
D2
K3

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QS_0
QS_1
QS_2
QS_3
QS_4
QS_5
QS_6
QS_7

C30
D23
B26
B21
B6
E7
E2
J2

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
QS_7B

C31
E23
A26
A21
A6
D7
E1
J1

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

ODT0
ODT1

E20
C11

ODTA0
ODTA1

CLK0
CLK1

A18
A11

CLKA0
CLKA1

CLK0B
CLK1B

B18
B11

CLKA0#
CLKA1#

RAS0B
RAS1B

G20
D12

RASA#0
RASA#1

CAS0B
CAS1B

D20
E12

CASA#0
CASA#1

CS0B_0
CS0B_1

E18
G18

CSA0#

CS1B_0
CS1B_1

G11
E11

CSA1#

CKE0
CKE1

D18
G12

CKEA0
CKEA1

WE0B
WE1B

D16
C10

WEA#0
WEA#1

MEMORY
INTERFACE

MVREFD
MVREFS
TEST_MCLK
TEST_YCLK
MEMTEST

DRAM_RST

4.7K_0402_5%

MAA[12..0] 19,20
BA[2..0]

19,20

DQMA#[3..0] 19

DQMA#[7..4] 20

QSA[3..0] 19

QSA[7..4] 20

QSA#[3..0] 19

QSA#[7..4] 20

ODTA0
ODTA1

19
20

CLKA0
CLKA1

19
20

CLKA0#
CLKA1#

19
20

RASA#0
RASA#1

19
20

CASA#0
CASA#1

19
20

CSA0#

19

CSA1#

20

CKEA0
CKEA1

19
20

WEA#0
WEA#1

19
20

R147
R146
4.7K_0402_5%

4.7K_0402_5%

BA[2..0]

J5

216-0707001-00/M82-S_BGA632

+1.8VS

MAA[12..0]

MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8
MA_9
MA_10
MA_11
MA_BA0
MA_BA1
MA_A12
MA_BA2

R149
240_0402_1%

R148
100_0402_1%

+VDD_MEM18_REFD
+VDD_MEM18_REFS

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63

MDA[63..32]

write strobe read strobe

20

R150
100_0402_1%

C329
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2006/09/25

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S MEM

Size

Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

17

of

53

U5E

U5D

Part 5 of 6

PART 4 OF 6

C336

C340

10U_0603_6.3V6M

1U_0402_6.3V4Z
1

1U_0402_6.3V4Z
1

C333

C334
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
C347
2

BLM18PG121SN1D_0603
2
1
L36
1

1
C349

C350

1U_0402_6.3V4Z
+1.8VS

1U_0402_6.3V4Z
1

C348

C335

1U_0402_6.3V4Z

C332

10U_0603_6.3V6M

C331

1U_0402_6.3V4Z

VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDD_CT

AC18
AC16
AC14
AC12

VDDR3
VDDR3
VDDR3
VDDR3

2
1
1U_0402_6.3V4Z 0.1U_0402_16V4Z

AF1
AF2

VDDR4
VDDR4

AE1
AE2

VDDR5
VDDR5

C356

C357
2

AA9
Y9
V9
T9
J11
J20
J21
L9

110mA

+VDD_CT

10U_0603_6.3V6M

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

C358

150mA

50mA
1

1U_0402_6.3V4Z
1
C364

10U_0603_6.3V6M

C365

1U_0402_6.3V4Z
1

C366
2

C367
M2
M3
L4
AD11

1U_0402_6.3V4Z

+VDD_MEM_CLK0
+VDD_MEM_CLK1

10U_0603_6.3V6M

+1.8VS
1

1
C378

C379

2
1U_0402_6.3V4Z
+3.3V_DELAY

1
C380

1U_0402_6.3V4Z

1
C381

C382
0.1U_0402_16V4Z

Back Bias Disable

S
2
G

SI2301BDS_SOT23

+3VS

VDDRH
VDDRH

B10
B19

VSSRH
VSSRH

V11
U11

BBN
BBN

R11
P11

1
C387

R151
100K_0402_5%

A10
A19

120mA

+VGA_CORE

NC
NC
NC
NC

P
O
W
E
R

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

VDDCI
VDDCI
VDDCI
VDDCI

J12
J14
J16
J18

1U_0402_6.3V4Z

Q8

PCI-Express

C330

A15
A22
A28
A4
A8
B8
C9
D1
H1
H11
H12
H14
H16
H18
H20
H21
B31
M1

Core

1.1A

10U_0603_6.3V6M
1

I/O Internal

10U_0603_6.3V6M
1

BBP
BBP

C388

2 1U_0402_6.3V4Z

Back Bias

+VGA_PCIE_VDDR

1
C337

10U_0603_6.3V6M

2
10U_0603_6.3V6M

1U_0402_6.3V4Z
1
C383

C375

1U_0402_6.3V4Z
1
C384
C385

220U_B2_2.5VM

C363

C372

2
1U_0402_6.3V4Z

C376

2
1U_0402_6.3V4Z

C371
2

1
+VGA_CORE
<BOM Structure>
+
C478

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1

C355

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1

2
1U_0402_6.3V4Z

C370

C374

15A
1

C362

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1

2
10U_0603_6.3V6M

+VDDCI

C361

C346

2 1U_0402_6.3V4Z

C354
2

1U_0402_6.3V4Z
1

C369

C373

1U_0402_6.3V4Z
1

PCIE_VDDC 1.1V @2A)

C345

2
1U_0402_6.3V4Z

C353

1U_0402_6.3V4Z
1
C368

2
10U_0603_6.3V6M

C344
2

C360

BLM18PG121SN1D_0603
1
2
+1.1VS
L35
1

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1
C359

C343

C352
2

+1.8VS

2 0.1U_0402_16V4Z

2
1U_0402_6.3V4Z

C351

1U_0402_6.3V4Z
1

2
10U_0603_6.3V6M

BLM18PG121SN1D_0603
1
2
L34
C339
0.5A

0.1U_0402_16V4Z

C342

2
2
10U_0603_6.3V6M

C338

2
1U_0402_6.3V4Z

1U_0402_6.3V4Z
+VGA_PCIE_VDDC
1
1
C341

C377

2
1U_0402_6.3V4Z

BLM18PG121SN1D_0603
2
1
L37
C386

2
1U_0402_6.3V4Z

2
10U_0603_6.3V6M

216-0707001-00/M82-S_BGA632

1U_0402_6.3V4Z
1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

Memory
I/O
Clock

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PCI-Express GND

A13
A2
C18
A24
A30
AA1
AA11
AA14
AA17
AA20
AA6
AC2
AC7
AE3
AL4
AD14
AF12
AF14
AD16
AD18
AE6
AG2
AE9
AH25
AK1
AK31
AJ6
AL2
AL30
B1
C13

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

+1.8VS

Memory I/O

AA26
AA29
AC26
AD31
AE29
AE30
AE31
F28
G26
G29
G30
G31
H29
J25
J26
L26
L29
L30
L31
M26
M29
P26
R29
R30
R31
T26
U29
V26
Y26
Y29
Y30
Y31

CORE GND
B

49

R185
2
1
@ 330K_0402_5%
1
2
R42
0_0402_5%

SUSP

1.1VS_POK
+3VS

1
R403

2
4.7K_0402_5%

D
Q9

2
G
3

44,50

216-0707001-00/M82-S_BGA632

0.01U_0402_25V7K

2N7002_SOT23-3

C883

+1.8VS

+VDD_MEM_CLK0
2

1
L38
BLM18PG121SN1D_0603
C392

2
1

2
1U_0402_6.3V4Z

10U_0603_6.3V6M

1.1A

C394

C393

0.1U_0402_16V4Z

+VDD_MEM_CLK1
2
1
L39
BLM18PG121SN1D_0603
C395

1
C396

10U_0603_6.3V6M

1.1A

Compal Secret Data

Security Classification

1
0.1U_0402_16V4Z

1U_0402_6.3V4Z

2
C397

Issued Date

2006/09/25

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.

M82-S POWER

Size

Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

18

of

53

L8

CS

WEA#0

K3

WE

RASA#0

K7

RAS

CASA#0

L7

CAS

DQMA#2
DQMA#0

F3
B3

LDM
UDM

K9

ODT

QSA2
QSA#2

F7
E8

LDQS
LDQS

R155
4.99K_0402_1%

QSA0
QSA#0

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

R157
4.99K_0402_1%

C402
BA2
0.1U_0402_16V4Z

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

+1.8VS

0.1U_0402_16V4Z
1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

K8
J8

CK
CK

CKEA0

K2

CKE

CSA0#

L8

CS

WEA#0

K3

WE

RASA#0

K7

RAS

CASA#0

L7

CAS

DQMA#1
DQMA#3

F3
B3

LDM
UDM

ODTA0

K9

ODT

QSA1
QSA#1

F7
E8

LDQS
LDQS

QSA3
QSA#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

C399
2 1U_0402_6.3V4Z
+1.8VS

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA0#
CLKA0

+1.8VS
1

+VRAM_REF1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

C398

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

BA0
BA1

R156
4.99K_0402_1%

+VRAM_REF2

R158
4.99K_0402_1%

C403
BA2
0.1U_0402_16V4Z

SI2:Add BA2 for 64M*16 VRAM

MDA29
MDA27
MDA31
MDA24
MDA26
MDA28
MDA25
MDA30
MDA14
MDA9
MDA12
MDA8
MDA10
MDA15
MDA11
MDA13

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

QSA#[7..0]

17,20 QSA#[7..0]

DQMA#[7..0]

17,20 DQMA#[7..0]
17,20

MAA[12..0]

MAA[12..0]

MDA[63..0]

17,20 MDA[63..0]

17

ODTA0

17

CKEA0

17

RASA#0

17

CASA#0

17

WEA#0

17

CSA0#

ODTA0
CKEA0
RASA#0

+1.8VS

0.1U_0402_16V4Z
1

CASA#0
WEA#0
CSA0#

+1.8VS
1
C401

2
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

QSA[7..0]

17,20 QSA[7..0]

C400

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

BA[2..0]

17,20 BA[2..0]

2 1U_0402_6.3V4Z

17

CLKA0

17

CLKA0#

CLKA0
CLKA0#
1

CKE

CSA0#

ODTA0
+1.8VS

CK
CK

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

K2

L2
L3

R159
56_0402_5%

R160
56_0402_5%
2

K8
J8

CKEA0

BA0
BA1

CLKA0#
CLKA0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

MDA1
MDA6
MDA3
MDA4
MDA5
MDA0
MDA7
MDA2
MDA19
MDA21
MDA16
MDA22
MDA23
MDA17
MDA20
MDA18

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

U7

BA0
BA1

L2
L3

U6
BA0
BA1

SI2:Add BA2 for 64M*16 VRAM

HY5PS561621F-25
@

HY5PS561621F-25
@

C404
470P_0402_50V7K

+1.8VS
+1.8VS
10U_0603_6.3V6M
1
B

C405

1
C406

0.1U_0402_16V4Z
1

C407
2

1
C408

0.1U_0402_16V4Z
1

C409
2

1
C410

1
C411

0.01U_0402_16V7K
1
1
+
C490
220U_6.3VM_R15
C412

10U_0603_6.3V6M
1
C413

C414
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C415
2

1
C416

0.1U_0402_16V4Z
1

C417
2

0.01U_0402_16V7K

C418
2

C419
2

C420
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2006/09/25

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S VRAM

Size

Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

19

of

53

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

K2

CSA1#

L8

CKE

CS

WEA#1

K3

WE

RASA#1

K7

RAS

CASA#1

L7

CAS

F3
B3

LDM
UDM

DQMA#5
DQMA#4
ODTA1

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

K9

ODT

QSA5
QSA#5

F7
E8

LDQS
LDQS

QSA4
QSA#4

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

MDA36
MDA35
MDA39
MDA32
MDA33
MDA38
MDA34
MDA37
MDA45
MDA43
MDA46
MDA40
MDA41
MDA44
MDA42
MDA47

+1.8VS

SI2:Add BA2 for 64M*16 VRAM

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKA1#
CLKA1

K8
J8

CK
CK

K2

L8

WE

RASA#1

K7

RAS

CASA#1

L7

CAS

F3
B3

LDM
UDM

K9

ODT

QSA6
QSA#6

F7
E8

LDQS
LDQS

QSA7
QSA#7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+1.8VS
1

ODTA1

2 1U_0402_6.3V4Z

+1.8VS

R162
4.99K_0402_1%

+VRAM_REF4

R164
4.99K_0402_1%

BA2
C426
0.1U_0402_16V4Z

SI2:Add BA2 for 64M*16 VRAM

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

MDA58
MDA59
MDA61
MDA56
MDA63
MDA62
MDA57
MDA60
MDA50
MDA53
MDA48
MDA55
MDA52
MDA49
MDA54
MDA51

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

BA[2..0]

17,19 BA[2..0]

DQMA#[7..0]

17,19 DQMA#[7..0]

MAA[12..0]

17,19 MAA[12..0]

QSA#[7..0]

17,19 QSA#[7..0]

QSA[7..0]

17,19 QSA[7..0]

MDA[63..0]

17,19 MDA[63..0]

+1.8VS

0.1U_0402_16V4Z
1

17

ODTA1

17

CKEA1

17

RASA#1

17

CASA#1

17

WEA#1

17

CSA1#

ODTA1
CKEA1
RASA#1
CASA#1
WEA#1
CSA1#

+1.8VS
1
C424
2 1U_0402_6.3V4Z

17

CLKA1

17

CLKA1#

CLKA1
CLKA1#
R165
56_0402_5%

HY5PS561621F-25
@

R166
56_0402_5%
2

HY5PS561621F-25
@

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

C421

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

C423

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

CS

K3

DQMA#6
DQMA#7
0.1U_0402_16V4Z
1

CKE

WEA#1

BA2

C425
0.1U_0402_16V4Z

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

CSA1#

+VRAM_REF3
1

R163
4.99K_0402_1%

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

C422

R161
4.99K_0402_1%

L2
L3

CKEA1

+1.8VS

BA0
BA1

MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

CKEA1

U9
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BA0
BA1

L2
L3

U8
BA0
BA1

2
+1.8VS

+1.8VS
10U_0603_6.3V6M
1

C427
470P_0402_50V7K

C428

1
C429

0.1U_0402_16V4Z
1

C430

1
C431

0.1U_0402_16V4Z
1

C432
2

1
C433

0.01U_0402_16V7K
1

C434
2

10U_0603_6.3V6M

1
C435

1
C436

10U_0603_6.3V6M

1
C437

0.1U_0402_16V4Z
1

C438
2

1
C439

0.1U_0402_16V4Z
1

C440
2

0.01U_0402_16V7K

C441
2

C442
2

C443
2

10U_0603_6.3V6M
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2006/09/25

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S VRAM

Size

Document Number

Rev
0.4

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

20

of

53

+3.3V_DELAY

10K_0402_5%2

@
1 R193
@
1 R184

10K_0402_5%2

@
1 R187

10K_0402_5%2

@
1 R194

10K_0402_5%2

@
1 R291

10K_0402_5%2

1 R190

SOUT_GPIO8 16

10K_0402_5%2

@
1 R219

SIN_GPIO9 16

10K_0402_5%2

GPIO0

16

GPIO1

16

STRAPS

GPIO4

16

TX_PWRS_ENB

GPIO0

GPIO5

16

TX_DEEMPH_EN

GPIO1

GPIO6

16

BIF_DEBUG_ACCESS

GPIO4

DEBUG SIGNALS MUXED OUT

BIF_GEN2_EN_A

GPIO5

PCI-E 5.0GT/s or 2.5 GT/s select

DEBUG_ I2C_ENABLE

GPIO6

Internal use only

GPIO9 = 0 (BIOS_ROM_EN = 0)

10K_0402_5%2

@
1 R234
@
1 R287
@
1 R289

10K_0402_5%2

@
1 R240

10K_0402_5%1

@
2 R196

10K_0402_5%2
10K_0402_5%2

10K_0402_5%2

GPIO[13:11]

GPIO11 16

0
0
0
1

GPIO12 16
GPIO13 16

SCS#_GPIO22

0
0
1
0

MEMORY SIZE
256MB

CRT_HSYNC

GPIO8

ROMIDCFG[3:0]

GPIO
[9,13,12,11]

BIOS_ROM EN

GPIO_22_ROMCSB

BIF_VGA_DIS
BIF_HDMI_EN

ENABLE HD AUDIO(M8X)
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

0 1 0 1

DISABLE EXTERNAL BIOS ROM

PSYNC

VGA ENABLED===0 is enable

HSYNC

HDMI ENABLE

64MB
512MB

PSYNC 16

1 R197

PCIE FULL TX OUTPUT SWING

PCIE TRANSMITTER DE-EMPHASIS ENABLES

BIF_AUDIO_EN

128MB

0
1
0
0

RECOMMENDED
M8X

DESCRIPTION OF RECOMMENDED SETTING

PIN

VRAM_ID 3 ,2 ,1 ,0

16,23

@ 10K_0402_5%
2
1
R213

+1.8VS

DVPDATA
(23,22,21,20)

VRAM_ID[3:0]

VRAM_ID0 16
1
2
R202
@ 10K_0402_5%
@ 10K_0402_5%
2
1
+1.8VS
R215
VRAM_ID1 16

Samsung

64Mx16 1.8V

0 0 0 0

Samsung

32Mx16 1.8V

0 0 0 1

Hynix

64Mx16 1.8V

0 0 1 0

Hynix

32Mx16 1.8V

0 0 1 1

Qimonda

32Mx16 1.8V

0 1 0 0

Qimonda

64Mx16 1.8V

0 1 0 1

1
2
R204
@ 10K_0402_5%
@ 10K_0402_5%
2
1
+1.8VS
R216
VRAM_ID2 16
1
2
R206
@ 10K_0402_5%
@ 10K_0402_5%
2
1
+1.8VS
R212

ATI RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESE

VRAM_ID3 16
1
R208

2
@ 10K_0402_5%
GPIO2

GPIO3

GPIO5

GPIO6

DVALID

H2SYNC

V2SYNC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
GENERICC

GPIO21_BB_EN

GPIO_28_TDO

FLASH ROM

VGA Thermal Sensor ADM1032ARMZ

Closed to U80

+3VS

U11
16

C466
0.1U_0402_16V4Z

16
16

16

D+

2200P_0402_50V7K

D-

VDD

SCS#_GPIO22

SCLK

SMB_EC_CK2 6,41

D+

SDATA

SMB_EC_DA2 6,41

D-

ALERT#

THERM#

GND

@ RV96 10K_0402_5%

+3.3V_DELAY

1
R330

HOLD

VCC

VSS

SOUT_GPIO8 16

M25P10-AVMN6T_SO8~D

ADM1032ARMZ REEL_MSOP8

THM_ALERT#

@
RV99
10K_0402_5%

16

8
1

C467
1
2

SCLK

SCLK

+3.3V_DELAY

U12

16

SIN_GPIO9

2
4.7K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2006/09/25

2006/09/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

M82-S Filters / Strap

Size

Document Number

Rev
0.3

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

21

of

53

+VDDCLK_IO

+1.2V_HT

R168
1
2
0_0805_5%

0.1U_0402_16V4Z
1
C452

22U_0805_6.3V6M

+3VS_CLK
R167
1
2
0_0805_5%
1

+3VS
1

C453
2

0.1U_0402_16V4Z
1

C454

C455

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C456

C457

2
0.1U_0402_16V4Z

1
C444
22U_0805_6.3V6M

C445
0.1U_0402_16V4Z

C446
0.1U_0402_16V4Z

C447
0.1U_0402_16V4Z

C448
0.1U_0402_16V4Z

C449
0.1U_0402_16V4Z

C450
0.1U_0402_16V4Z

C451
1U_0402_6.3V4Z

+3VS_CLK
1

C458
0.1U_0402_16V4Z

C459
0.1U_0402_16V4Z

C460
0.1U_0402_16V4Z

C461
0.1U_0402_16V4Z

CLK_XTAL_OUT
CLK_XTAL_IN

SI2:follow AMD request modify resistor value

Y2

Routing the trace at least 10mil

GND
8,9,27,35 SMB_CK_CLK0
8,9,27,35 SMB_CK_DAT0
16
16

PA_RS7X0A1

R226
R228

27M_CLK
27M_SSC

+3VS_CLK
1
2
1
2

33_0402_5%
33_0402_5%

11 CLK_SBLINK_BCLK#
11 CLK_SBLINK_BCLK

SB LINK

+VDDCLK_IO

MiniCard_1
MiniCard_2

33 CLK_PCIE_MCARD1#
33 CLK_PCIE_MCARD1
33 CLK_PCIE_MCARD2#
33 CLK_PCIE_MCARD2

R220

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

+3VS_CLK

1
2
R174 10K_0402_5%

33_0402_5%

R179
@ 8.2K_0402_5%

OSC_14M_NB
RS780

1.1V 158R/90.0R

CLK_14M_SIO 40
CLK_NBHT 11
CLK_NBHT# 11 NB

+3VS_CLK

1
R946
1
R945

CLK_CPU_BCLK 6
2

R186
@ 261_0402_1%

2
0_0402_5%
2
0_0402_5%

CPU
CLK_CPU_BCLK# 6

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO

VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC

+3VS_CLK
+VDDCLK_IO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#

U10

73

NB_OSC_14.318M 11
2 R380
90.9_0402_1%

22P_0402_50V8J

CLK_48M_USB 27

2
158_0402_1%

22P_0402_50V8J
2

R171/R183 (value may change)

33_0402_5%

R379

+3VS_CLK

14.31818MHZ_20P_6X1430004201
1
C465

NB_OSC_14.318M_R

CLK_XTAL_OUT
CLK_XTAL_IN

C464

SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK

R170

CLKREQ_NCARD#
CLKREQ_MCARD2#

VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

CLKREQ_MCARD1#

+3VS_CLK
+VDDCLK_IO

CLKREQ_LAN

CLKREQ_NCARD#
CLKREQ_MCARD2#

CLKREQ_NCARD# 33
CLKREQ_MCARD2# 33

+3VS_CLK

CLK_SBSRC_BCLK 26
CLK_SBSRC_BCLK# 26
+3VS_CLK
1
R372

CLKREQ_MCARD1#

2
10K_0402_5%

SB SRC

1
R324
1
R325
1
R326
1
R390

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

+3VS_CLK

PA_RS7X0A1

CLKREQ_MCARD1# 33

+3VS_CLK

+3VS_CLK
+VDDCLK_IO
3

SLG8SP626VTR_QFN72_10x10

SI2: Use new version CLK gen

R181
8.2K_0402_5%

R180
8.2K_0402_5%

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

SEL_SATA

27M_SEL

NBGFX_CLK 11
NBGFX_CLK# 11

NB GFX

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15

VGA chip(Dis)

NB CLOCK INPUT TABLE

NB CLOCKS

HT_REFCLKN
1

CLKREQ_LAN

configure as SATA output

1 *

SEL_SATA
0 * configure as normal SRC(SRC_6) output
* default

configure as 27M and 27M_SS output

27M_SEL
configure as SRC_7 output
0
* default

CLK_PCIE_MCARD0 34
CLK_PCIE_MCARD0# 34
CLKREQ_LAN 32
CLK_PCIE_LAN 32
CLK_PCIE_LAN# 32
CLK_PCIE_NCARD 33
CLK_PCIE_NCARD# 33

GLAN

configure as single-ended 66MHz output

0*
configure as differential 100MHz output
* default

2007/08/02

Issued Date

New Card

REFCLK_N

14M SE (1.8V)
NC

14M SE (1.1V)
vref

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

100M DIFF

NC or 100M DIFF OUTPUT

GPPSB_REFCLK

100M DIFF

100M DIFF

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

100M DIFF
100M DIFF

GFX_REFCLK

Compal Secret Data

Security Classification
1

RS780

100M DIFF
100M DIFF

REFCLK_P

Card reader

Use voltage divider resistor R379 & R380 to pull low

NB_OSC_14.318M

RX780

HT_REFCLKP

Title

Compal Electronics, Inc.

Clock generator

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

22

of

53

CRT CONNECTOR
1

+5VS

+R_CRT_VCC

D35

D37

D34

+CRT_VCC
F2

D36
1

2
1

RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z

+3VS

DAN217_SC59DAN217_SC59
@
@

DAN217_SC59
@

JP6

C471
2

1
C859
2

1
C469
2

1
C858
2

HSYNC
BLUE_L
+CRT_VCC
1
C476
2

1
C472
2

VSYNC

6P_0402_50V8K

R217

2
1
150_0402_1%

R211

2
1
150_0402_1%

R214

D_DDCDATA
GREEN_L

6P_0402_50V8K

BLUE

BLUE
2
1
150_0402_1%

16

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED_L

6P_0402_50V8K

GREEN

6P_0402_50V8K

16

GREEN

6P_0402_50V8K

RED

RED

6P_0402_50V8K

16

L47
1
2
BLM15AG121SN1D_0402
L48
1
2
BLM15AG121SN1D_0402
L49
1
2
BLM15AG121SN1D_0402

D_DDCCLK

RED_L

16 GND
17 GND

43

GREEN_L 43
SUYIN_070546FR015S265ZR
BLUE_L 43

SI:change
CRT Conn.
CONN@

SI2:change pull high from 6.8K to 2K ohm

+3VS

+CRT_VCC

5
1
A

Y
U14

D_DDCDATA 43

Q10B
2N7002DW-7-F_SOT363-6

D_HSYNC

SN74AHCT1G125GW_SOT353-5

1
L84

2
10_0402_5%

HSYNC

1
L83

2
10_0402_5%

VSYNC

+CRT_VCC

+3VS

RS780 DAC_SCL & SDA is 5V tolerance

Q10A
2N7002DW-7-F_SOT363-6 C857
@
470P_0402_50V8J

D_DDCCLK 43

C856
@
2 470P_0402_50V8J

16

5
1
2

CRT_VSYNC

P
OE#

D_DDCCLK

D_VSYNC

U13
SN74AHCT1G125GW_SOT353-5

M82-S DDC3 & DDC4 is 5V tolerance

16 VGA_DDC_CLK

C474

1
2
C477
0.1U_0402_16V4Z

D_HSYNC

1
C470
@

10P_0402_50V8J

D_DDCDATA

10P_0402_50V8J

1
3

16,21 CRT_HSYNC
4

16 VGA_DDC_DAT

P
OE#

R218
2K_0402_5%

R100
2K_0402_5%

1
2
C473
0.1U_0402_16V4Z

+CRT_VCC
+3VS
R238
4.7K_0402_5%
@

R237
4.7K_0402_5%
@

43

D_VSYNC 43

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

CRT Connector

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

23

of

53

+LCDVDD
1

+5VALW
2

R225
470_0805_5%

R224
1M_0402_5%

3 2

+3VS

R222
1
2
100K_0402_5%

Q43
SI2301BDS-T1-E3_SOT23-3

Q144B
2N7002DW-7-F_SOT363-6

80mil

2
R276
2.2K_0402_5%

2
C863
1000P_0402_50V7K
Q144A
1
2N7002DW-7-F_SOT363-6

16 VGA_ENVDD

80mil
+LCDVDD
1

C487
4.7U_0805_10V4Z

C491
0.1U_0402_16V4Z

INVPWR_B+

IO2 GND

USB20_P5

@ PRTR5V0U2X_SOT143-4

27
27

LVDS_BCLK+
LVDS_BCLK-

16 LVDS_BCLK+
16 LVDS_BCLK-

LVDS_BCLK+
2
1
680P_0402_50V7K C870 @
LVDS_BCLK2
1
680P_0402_50V7K C871 @

USB20_P5
USB20_N5

USB20_P5
USB20_N5

16
16
16
16
16
16

SI: Add +5VS jumper

LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

DMIC_DAT
DMIC_CLK

PJP7
PAD-OPEN 2x2m

VIN

GND

VOUT

BP

R891

2
3

EN

RT9193-39GB_SOT23-5

1
@ 0_0402_5%

1
@C923
@
C923
1
@C924
@
C924

2
220P_0402_50V7K
2
220P_0402_50V7K

SI2: Add 220P for EMI

+5VS

SI: Change R491 to 0805 size

INV_PWM 41
BKOFF# 41
DAC_BRIG 41

LCD_DDC_CLK 1
4.7K_0402_5% @

2
R274

LCD_DDC_DAT 1 @
4.7K_0402_5%

2
R275

2
C719
10U_0805_10V4Z
1
R892
100K_0402_1%
@

C511
0.1U_0402_16V4Z

2
2
R17

1
2
R16
0_0402_5%

2
R483

DMIC_CLK

PV: mount for EMI

@ 215K_0402_1%
U54

28 CAM_SHDN#

BKOFF#
1
@ 4.7K_0402_5%

+USB_CAM

SI:Change to Richtek parts

DMIC_DAT

+USB_CAM
LCD_DDC_CLK 16
LCD_DDC_DAT 16

LCD_DDC_CLK
LCD_DDC_DAT

+3VS

DMIC_DAT 36
DMIC_CLK 36
1
2
100_0805_5%
R491

INVT_PWM
BKOFF#
DAC_BRIG

+5VALW +5VS

C720
10U_0805_10V4Z

LVDS_A2- 16
LVDS_A2+ 16
LVDS_A1- 16
LVDS_A1+ 16
LVDS_A0- 16
LVDS_A0+ 16
LVDS_ACLK- 16
LVDS_ACLK+ 16

LVDS_ACLKLVDS_ACLK+

ACES_88242-4001
CONN@

PJP4
PAD-OPEN 2x2m

1
2
@ C868 680P_0402_50V7K
1
2
@ C869 680P_0402_50V7K

LVDS_ACLK+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

C628
470P_0402_50V7K

LVDS_ACLK-

JP7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

C483
470P_0402_50V7K

IO1

VIN

USB20_N5

680P_0402_50V7K

D22
+5VALW

LVDS CONN

C482
470P_0402_50V7K

C481

INVPWR_B+
L44
2
1
FBMA-L11-201209-221LMA30T_0805
<BOM Structure>

C867
680P_0402_50V7K
2
1

680P_0402_50V7K

+3VS

C480

680P_0402_50V7K

B+
C479

C866
680P_0402_50V7K
2
1

+LCDVDD

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

LCD CONN.

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

24

of

53

SI2:change pull high from 6.8K to 2K ohm

+3VS

+HDMI_5V_OUT

R176
@ 4.7K_0402_5%

HPD

U39
SN74AHCT1G125GW_SOT353-5

16

R210
2K_0402_5%

R236
2K_0402_5%

16 HDMIDAT_VGA

2 C850
0.1U_0402_16V4Z

R628
100K_0402_5%

+3VS
R209
@ 4.7K_0402_5%

HDMI_SDATA

P
OE#

+3VS

2.2K_0402_5%

1
R615

2
5
1

C851
0.1U_0402_16V4Z

HDMI_HPD
1

+HDMI_5V_OUT

Q139B
2N7002DW-7-F_SOT363-6

+3VS

16 HDMICLK_VGA

HDMI_SCLK

6
Q139A
2N7002DW-7-F_SOT363-6

C:Chg. PN to SB770020010.

MP:Update D10 to meet HDMI.

SI:Add R6161~R624 for EMI requset
D10
HDMI_CLK-

R616

HDMI_R_CK-

+5VS

0_0402_5%

+HDMI_5V_OUT

RB491D_SOT23
L85
1
4
@

1
4

HDMI_TX0-

HDMI_CLK+
HDMI_CLK-

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX0+
HDMI_TX0-

C804 1
C827 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX1+
HDMI_TX1-

16 HDMI_TX2+_VGA
16 HDMI_TX2-_VGA

C852 1
C853 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX2+
HDMI_TX2-

R618

HDMI Connector
HDMI_R_CKHDMI_R_D0+

HDMI_R_D1HDMI_R_D1+
HDMI_R_D0-

HDMI_TX1-

R620

HDMI_R_D1HDMI_R_D0+

0_0402_5%

L87
1
4
@

HDMI_R_D2+

1
4

HDMI_R_D2-

1
R307
1
R315
1
R297
1
R173
1
R304
1
R172
1
R141
1
R139

2
2
2
2
2
2
2
2

499_0402_1%

499_0402_1%
499_0402_1%
499_0402_1%

R623

HDMI_R_D1+
+5VS

HDMI_R_D2-

4
@
4

HDMI_TX2+

WCM-2012-900T_0805
1
2
R624
0_0402_5%

CKCK+
D0D0+
D1D1+
D2D2+

GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND

2
5
8
11
20
21
22
23
17

SI:Update
CONN@HDMI footprint

HDMI_R_D2+

Compal Secret Data

2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

12
10
9
7
6
4
3
1

13
14

0_0402_5%

Security Classification

HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

CEC
Reserved

Q136
2N7002_SOT23-3

2
G

R490
100K_0402_5%

L88
1

+5V
SDA
SCL
HP_DET

499_0402_1%

1
1

18
16
15
19

499_0402_1%
499_0402_1%

JP8

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

HDMI_TX2-

+HDMI_5V_OUT

499_0402_1%

SUYIN_100042MR019S153ZL

WCM-2012-900T_0805
1
2
R621
0_0402_5%

HDMI_TX1+

0.1U_0402_16V4Z

HDMI_R_D00_0402_5%

WCM-2012-900T_0805
1
2
R619
0_0402_5%

HDMI_TX0+

C468

HDMI_R_CK+

HDMI_R_CK+
4
@

16 HDMI_TX1+_VGA
16 HDMI_TX1-_VGA

L86
1

C655 1
C675 1

16 HDMI_TX0+_VGA
16 HDMI_TX0-_VGA

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C507 1
C508 1

WCM-2012-900T_0805
1
2
R617
0_0402_5%

HDMI_CLK+

16 HDMI_CLK+_VGA
16 HDMI_CLK-_VGA

Title

Compal Electronics, Inc.

HDMI

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

25

of

53

Check AMD need pull low or not

1
R300

2 NB_RST#_R
@ 8.2K_0402_5%
U15A

10
10
10
10
10
10
10
10

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

C492
C493
C494
C495
C496
C497
C498
C499

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

R305
R306
+PCIE_VDDR
L53
1
2
+1.2V_HT
BLM18PG121SN1D_0603
1
+3VALW

C506

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

T25
T24

PCIE_CALRP
PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

+SB_PCIEVDD
1

C505
1U_0402_6.3V4Z

A_RST#

Part 1 of 5

NB_RST#_R

U16

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

PLT_RST# 11,14,15,32,33,34,40,41

@ NC7SZ08P5X_NL_SC70-5

@ R314 20M_0402_5%
@R314
1
2
C643

Y3

R389
20M_0603_5%
C652
1

OUT

NC

IN

NC

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

K23
K22

NB_DISP_CLKP
NB_DISP_CLKN

M24
M25

NB_HT_CLKP
NB_HT_CLKN

P17
M18

CPU_HT_CLKP
CPU_HT_CLKN

M23
M22

SLT_GFX_CLKP
SLT_GFX_CLKN

J19
J18

GPP_CLK0P
GPP_CLK0N

L20
L19

GPP_CLK1P
GPP_CLK1N

M19
M20

GPP_CLK2P
GPP_CLK2N

N22
P22

GPP_CLK3P
GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

32.768KHZ_12.5P_1TJS125BJ4A421P

SB_32KHI

2
1

18P_0402_50V8J

N25
N24

PCI INTERFACE

22 CLK_SBSRC_BCLK
22 CLK_SBSRC_BCLK#

1
33_0402_5%

CLOCK GENERATOR

2
R312

SB_32KHO

J20

25M_X2

N1

AD3
AC4
AE2
AE3

PCIRST#

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

Close to SB
PLT_RST#

P4
P3
P1
P2
T4
T3

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

@ 0.1U_0402_16V4Z
2

C504
10U_0805_10V4Z

V23
V22
V24
V25
U25
U24
T23
T22

1 562_0402_1%
1 2.05K_0402_1%

2
2

SB700

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

SB_32KHO

B3

X2

H_PROCHOT#
1
10K_0402_5%
CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

RTCCLK
INTRUDER_ALERT#
VBAT

PAD T15

PAD T16
PAD T17

CLK_PCI_EC
CLK_PCI_SIO

PCI_PIRQH#

R967

1 0_0402_5%

C3
C2
B2

C501 1
2
@ 100_0402_5%
C503 1
2
@ 100_0402_5%

1
R303
1
R369

2@ 100P_0402_25V8K
3

2@ 100P_0402_25V8K

ACCEL_INT 35

08/29 new add

R308
1
R309
1
R310
1
LPC_AD0 40,41
LPC_AD1 40,41
LPC_AD2 40,41
LPC_AD3 40,41
LPC_FRAME# 40,41

CLK_PCI_EC
CLK_PCI_SIO

2 22_0402_5%
2 22_0402_5%
2@ 22_0402_5%

CLK_PCI_EC 30,41
CLK_PCI_SIO 30,40
CLK_PCI_SIO2 40

LPC_DRQ1# 40
SIRQ

40,41

RTC_CLK 30

STRAP PIN
+3VL

+SB_VBAT

+SB_VBAT

RTC

6,11 CPU_LDT_REQ#
6 H_PROCHOT#
6 H_PWRGD
6,11 LDT_STOP#
6
LDT_RST#

LPC

X1

CPU

2
R319

A3

RTC XTAL

+3VS

SB_32KHI

PCI_SERR# 41

18P_0402_50V8J

Close to SB

30
30
30
30

30
30
30
30
30
30

+RTCVCC
R316
120_0402_5%
1
2

218S7EALA11FG_BGA528_SB700

1
C509

W=20mils

C510

2
1U_0402_6.3V4Z

+RTCBATT
D42
2

1
DAN202U_SC70

R876
3
1
2
W=20mils
1K_0402_5%

JBATT1
W=20mils

J1
@ JUMP_43X39

1
2
3
4

1
2
GND
GND

ACES_85205-02001
1

R317
120_0402_5%
1
2

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PCI CLKS

10
10
10
10
10
10
10
10

N2

PCI EXPRESS INTERFACE

NB_RST#_R

Compal Secret Data

Security Classification
2007/08/02

Issued Date

0.1U_0402_16V4Z

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700-PCIE/PCI/ACPI/LPC/RTC

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

26

of

53

+3VALW

R561
10K_0402_5%

PCIE_WAKE#

32,33 LAN_PCIE_WAKE#

U15D

32,33 MINI_PCIE_WAKE#

SB_TEST0
PCIE_WAKE#
6,41 H_THERMTRIP#
11 NB_PWRGD

2
R327

1 EC_RSMRST#
100K_0402_5%

H_THERMTRIP#

PV:delete R381 & R386

SI2: change from 2.2K to 100K ohm

EC_RSMRST#

41 EC_RSMRST#

36
SB_SPKR
8,9,22,35 SMB_CK_CLK0
8,9,22,35 SMB_CK_DAT0
33 SMB_CK_CLK1
33 SMB_CK_DAT1

+3VS

R328

2 2.2K_0402_5%

SMB_CK_CLK0

R329

2 2.2K_0402_5%

SMB_CK_DAT0

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

PAD T47

+3VALW

R331

2 2.2K_0402_5%

SMB_CK_CLK1

R332

2 2.2K_0402_5%

SMB_CK_DAT1

36
42
42
36
36
42

HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDIN0
HDA_SDIN1

42 HDA_SYNC_MDC
36 HDA_SYNC_CODEC
36 HDA_RST#_CODEC
42 HDA_RST#_MDC

STRAP PIN 30,41

41 EC_LID_OUT#
33 EXP_CPPE#
34 CR_CPPE#
32 LAN_DSM#

R333
R334
R335
R336

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

R337
R338

33_0402_5%
33_0402_5%

R339
R340

33_0402_5%
33_0402_5%

1
1
1
1

1
1
1
1

2
2
2
2

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1

2
2

HDA_SYNC

2
2

HDARST#

D3

AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5

E6
E7

USB_FSD12P
USB_FSD12N

F7
E8

USB10_P12
USB10_N12

USB_HSD11P
USB_HSD11N

H11
J10

USB20_P11
USB20_N11

USB_HSD10P
USB_HSD10N

E11
F11

USB20_P10
USB20_N10

USB_HSD9P
USB_HSD9N

A11
B11

USB_HSD8P
USB_HSD8N

C10
D10

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

G11
H12

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

E12
E14

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

C12
D12

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B12
A12

USB20_P4
USB20_N4

USB_HSD3P
USB_HSD3N

G12
G14

USB20_P3
USB20_N3

USB_HSD2P
USB_HSD2N

H14
H15

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

A13
B13

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

B14
A14

USB20_P0
USB20_N0

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

G20
G21
D25
D24
C25
C24
B25
C23

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

USB MISC

USB_FSD13P
USB_FSD13N

USB 1.1

SB_TEST1

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

G8

RSMRST#

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

B9
B8
A8
A9
E5
F8
E4

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

M1
M2
J7
J8
L8
M3
L6
M4
L5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

PAD T41

HDARST#

H19
H20
H21
F25

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3

D22
E24
E25
D23

IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

USB 2.0

41
41
41
41

SB_TEST2

USB_RCOMP

GPIO

2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%
2
@ 2.2K_0402_5%

C8

ACPI / WAKE UP EVENTS

1
R320
1
R321
1
R322

+3VALW

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0

2@ 100P_0402_25V8K
1

USBCLK/14M_25M_48M_OSC

INTEGRATED uC

SUS_STAT#

2
4.7K_0402_5%

SB700 has internal PD

INTEGRATED uC

1
R388

+3VS

41
SLP_S3#
41
SLP_S5#
41 PWRBTN_OUT#
6,41,51 SB_PWRGD
11 SUS_STAT#

C617 1
2
@ 100_0402_5%

1
R311

Part 4 of 5

SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

USB OC

demo circuit LID use RI#

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14

HD AUDIO

CLK_48M_USB 22
USB_RCOMP 1
11.8K_0402_1%

2
R323

USB10_P12 39
USB10_N12 39

Touch Screen

USB20_P11 33
USB20_N11 33

USB-11 New Card

USB20_P10 33
USB20_N10 33

USB-10 MiniCard(TV tuner)

USB-9 Card Reader(delete)

USB20_P8 33
USB20_N8 33

USB-8 WLAN

USB20_P7 39
USB20_N7 39

USB-7 Fingerprint

USB20_P6 39
USB20_N6 39

USB-6 Bluetooth

USB20_P5 24
USB20_N5 24

USB-5 USB Camera

USB20_P4 39
USB20_N4 39

USB-4 Left side

USB20_P3 43
USB20_N3 43

USB-3 Dock

USB20_P2 39
USB20_N2 39

USB-2 Left Side

USB20_P1 39
USB20_N1 39

USB-1 Right side

USB20_P0 39
USB20_N0 39

USB-0 Right side

GPIO16 30
GPIO17 30

STRAP PIN
STRAP PIN
3

218S7EALA11FG_BGA528_SB700

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 USB/AC97

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

27

of

53

U15B
1

SATA_RX0N
SATA_RX0P

C514
C515

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

AE10
AD10

SATA_TX1P
SATA_TX1N

AD11
AE11

SATA_RX1N
SATA_RX1P

AB12
AC12

SATA_TX2P
SATA_TX2N

AE12
AD12

SATA_RX2N
SATA_RX2P

AD13
AE13

SATA_TX3P
SATA_TX3N

AB14
AC14

SATA_RX3N
SATA_RX3P

T24 PAD
T25 PAD

AE14
AD14

SATA_TX4P
SATA_TX4N

T26 PAD
T27 PAD

AD15
AE15

SATA_RX4N
SATA_RX4P

T18 PAD
T19 PAD

AB16
AC16

SATA_TX5P
SATA_TX5N

SATA_STX_DRX_P1
SATA_STX_DRX_N1

31 SATA_RXN1_C
31 SATA_RXP1_C
C520
C521

39 SATA_TXP5
39 SATA_TXN5

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SATA_STX_DRX_P5
SATA_STX_DRX_N5

39 SATA_RXN5_C
39 SATA_RXP5_C
C518
C519

31 SATA_TXP4
31 SATA_TXN4

SATA_STX_DRX_P4
SATA_STX_DRX_N4

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

31 SATA_RXN4_C
31 SATA_RXP4_C

T20 PAD
T23 PAD
2
R342

+3VS R343 1
42 SATA_LED#

+1.2V_HT

AE16
AD16
V12

SATA_CAL

Y12

SATA_X1

SATA_X2

AA12

SATA_X2

10K_0402_5%

W11

SATA_ACT#/GPIO67

+PLLVDD_SATA
2

C523
1U_0402_6.3V4Z

+3VS
L55
2
1
BLM18PG121SN1D_0603
C524
1U_0402_6.3V4Z
3

+XTLVDD_SATA
2

PLLVDD_SATA

W12

XTLVDD_SATA

HW MONITOR

C522
1U_0402_6.3V4Z

AA11

SATA PWR

L54
2
1
BLM18PG121SN1D_0603

C625
@ 0.1U_0402_16V4Z

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
2

SATA_RX5N
SATA_RX5P

SATA_CAL
1
1K_0402_1%
SATA_X1

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

Part 2 of 5

ATA 66/100/133

SATA_TX0P
SATA_TX0N

AB10
AC10

31 SATA_RXN0_C
31 SATA_RXP0_C
31 SATA_TXP1
31 SATA_TXN1

SB700

AD9
AE9

SPI ROM

31 SATA_TXP0
31 SATA_TXN0

SATA_STX_DRX_P0
SATA_STX_DRX_N0

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

1
1

SERIAL ATA

C512
C513

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32

G6
D2
D1
F4
F3

LAN_RST#/GPIO13
ROM_RST#/GPIO14

U15
J1

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

M8
M5
M7

CR_WAKE# 34

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

P5
P8
R8

LAN_ISOLATE# 32
GSENSOR_LED# 42
SB_INT_FLASH_SEL 40

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

C6
B6
A6
A5
B5

XMIT_OFF# 33
BT_COMBO_EN# 33

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

A4
B4
C4
D4
D5
D6
A7
B7

EC_THERM# 41

1 C517

AVDD

F6

AVSS

G7

+SB_AVDD
1
1

2
C525
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

10M_0402_5%
2

10P_0402_50V8J 2

AC_IN

41,46

+3VALW

R341
2

Y4
25MHZ_20P

2
150K_0402_5%

+3VALW

SATA_X1

1 C516

1
D41

1
R562

PV:Add D41 and R562

PV:Reserve for EMI

10P_0402_50V8J 2

CH751H-40PT_SOD323-2
2

BT_OFF
39
CAM_SHDN# 24

L56
2
1
BLM18PG121SN1D_0603
C526
2.2U_0603_6.3V4Z

SATA_X2

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 SATA/IDE/SPI

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

28

of

53

U15C

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

Y20
AA21
AA22
AE25

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

Part 3 of 5

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

1
R592
1
R593

L15 +1.2V_HT_R
M12
M14
N13
P12
P14
R11
R15
T16

@ 22U_0805_6.3V6M
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z
2 @ 1U_0402_6.3V4Z

+PCIE_VDDR
L61
2
0_0805_5%

+1.2V_HT

C552
C553
C555
C554
C558
C557
C560

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

AA14
AB18
AA15
AA17
AC18
AD17
AE17

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

4.7U_0805_10V6K
2@ 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
+1.2V_SATA
1
0_0805_5%
1
22U_0805_6.3V6M
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

SATA I/O

2
C566
C567 1
C568 1
C571 1
C572 1

L60
1
0_0603_5%

C546
C545
C548
C551
C550

1
1
2
2
1

+1.2V_HT

1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z

2
2
1
1
2

+3VALW

L63
2

+1.2V_HT

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

POWER
P18
P19
P20
P21
R22
R24
R25

1
1
1
1
1
1

+1.2V_CKVDD

L21
L22
L24
L25

2
2
2
2
2
2

SB700

3.3V_S5 I/O

1
1
1

CLKGEN I/O

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

CORE S5

A-LINK I/O

C543
C544
C547
C549

IDE/FLSH I/O

No IDE device unmount CAP

+3VS

10U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

U15E

2
+1.2VALW
@ 0_0805_5%
2
+1.2V_HT
0_0805_5%
2
C529
C532
1
C534
1
C538
1
C537
1
C527
1
C540
1

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

A17
A24
B17
J4
J5
L1
L2

+S5_3V

S5_1.2V_1
S5_1.2V_2

G2
G4

+S5_1.2V

1
2
R564
0_0805_5%
1
2
22U_0805_6.3V6M
C556
1U_0402_6.3V4Z 2
C559
1
1U_0402_6.3V4Z 2
C561
1
1U_0402_6.3V4Z 2
C562
1
0.1U_0402_16V4Z 2
C563
1
0.1U_0402_16V4Z 2
C564
1
0.1U_0402_16V4Z 2
C565
1

+1.2VALW
+1.2_USB

USB_PHY_1.2V_1
USB_PHY_1.2V_2

+1.2VALW
L64

A10
B10

L65

0_0603_5%

1U_0402_6.3V4Z
1U_0402_6.3V4Z

0_0603_5%

1
10U_0805_10V4Z
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2

2
2

1
1

C569
C570

C573
C574
C575

1
1

C576
C577
C580
C581
C583
C582
C584
3

1
1
1
1
1
1
1

L66
1
0_0805_5%
2
2
2
2
2
2
2

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

PLL

+3VALW

USB I/O

+AVDD_USB
V5_VREF

AE7

+V5_VREF

AVDDCK_3.3V

J16

+AVDDCK_3.3V

AVDDCK_1.2V
AVDDC

1K_0402_5% 2

K17

C578
+AVDDCK_1.2V 0.1U_0402_16V4Z

E9

+AVDDC

C579
1U_0603_10V4Z
1

L67
1
0_0603_5%

2.2U_0603_6.3V4Z
0.1U_0402_16V4Z

218S7EALA11FG_BGA528_SB700

+AVDDCK_1.2V

+AVDDCK_3.3V

C585

C586

L68
1
0_0603_5%

0.1U_0402_16V4Z

+3VS

H18
J17
J22
K25
M16
M17
M21
P16
F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17

218S7EALA11FG_BGA528_SB700

+1.2V_HT

C587

C588

L69
1
0_0603_5%

2.2U_0603_6.3V4Z

+5VS

+3VALW
1

0.1U_0402_16V4Z

1 R346

CH751H-40PT_SOD323-2

2.2U_0603_6.3V4Z

D14

GROUND

CORE S0

C528
C531
C530
C533
C536
C535
C539
C541
C542

PCI/GPIO I/O

+3VS

SB700

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

+3VS

1 C589

1 C590

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

29

of

53

REQUIRED STRAPS
PULL
HIGH

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2

PCI_CLK3

PCI_CLK4

PCI_CLK5

LPC_CLK0

LPC_CLK1

RTC_CLK AZ_RST_CD#

BOOTFAIL
TIMER
ENABLED

USE
DEBUG
STRAPS

RESERVED

RESERVED

ENABLE PCI
MEM BOOT

CLKGEN
ENABLED

INTERNAL
RTC

EC
ENABLED

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

DEFAULT

DEFAULT

L,L = FWH ROM

R355
10K_0402_5%
2
1

+3VALW

R354
10K_0402_5%
2
1

+3VALW

R353
10K_0402_5%
2
1

+3VALW

R352
10K_0402_5%
2
1

+3VALW

L,H = LPC ROM (Default)

DEFAULT

R351
10K_0402_5%
2
1

+3VALW

EC
DISABLED

R350
10K_0402_5%
2
1

+3VS

H,L = SPI ROM

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

R349
10K_0402_5%
2
1

+3VS

H,H = Reserved

R348
10K_0402_5%
2
1

+3VS

DEFAULT

GP16

Internal pull up

R347
10K_0402_5%
2
1

+3VS

CLKGEN
DISABLED

GP17

DEFAULT

PULL
LOW

+3VALW

R356
2.2K_0402_5%
2
1

26
PCI_CLK2
26
PCI_CLK3
26
PCI_CLK4
26
PCI_CLK5
26,41 CLK_PCI_EC
26,40 CLK_PCI_SIO
26
RTC_CLK
27,41 HDARST#
27
GPIO17
27
GPIO16

R366
2.2K_0402_5%
2
1

R365
2.2K_0402_5%
2
1

R364
10K_0402_5%
2
1

R363
2.2K_0402_5%
2
1

R362
10K_0402_5%
2
1

R360
10K_0402_5%
2
1

R361
10K_0402_5%
2
1

R359
10K_0402_5%
2
1

R358
10K_0402_5%
2
1

R357
10K_0402_5%
2
1

SI2: mount 2.2K ohm

DEBUG STRAPS

PULL
LOW

PCI_AD24

PCI_AD23

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

R378
2.2K_0402_5%
2
1

R377
2.2K_0402_5%
2
1

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R373
2.2K_0402_5%
2
1

26
26
26
26
26
26

PCI_AD25

USE ACPI
BCLK

R376
2.2K_0402_5%
2
1

PCI_AD26

USE PCI
PLL

R375
2.2K_0402_5%
2
1

PCI_AD28
PULL
HIGH

PCI_AD27

USE
LONG
RESET

R374
2.2K_0402_5%
2
1

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

SB700 STRAPS

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

30

of

53

HDD Connector
JP9

1
C594

1
C591

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C595
0.1U_0402_16V4Z

C593
10U_0805_10V4Z

+5VS

2
2
0.1U_0402_16V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

Pleace near HD CONN (JP23)

1
2
3
4
5
6
7

SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K

SATA_TXP0 28
SATA_TXN0 28

1 C592 SATA_RXN0_C
1 C596 SATA_RXP0_C

SATA_RXN0_C 28
SATA_RXP0_C 28

Near CONN side.

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

SUYIN_127072FR022G210ZR_RV
CONN@

2nd HDD Connector-option

2

JP10

1
C602

1
C603

2
0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

C604
0.1U_0402_16V4Z

C601
10U_0805_10V4Z

+5VS

2
2
0.1U_0402_16V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

Pleace near HD CONN (JP23)

1
2
3
4
5
6
7

SATA_TXP1
SATA_TXN1
0.01U_0402_16V7K
SATA_RXN1
2
SATA_RXP1
2
0.01U_0402_16V7K

SATA_TXP1 28
SATA_TXN1 28

1 C605 SATA_RXN1_C
1 C606 SATA_RXP1_C

SATA_RXN1_C 28
SATA_RXP1_C 28

Near CONN side.

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

SUYIN_127072FR022G210ZR_RV
CONN@
3

CD-ROM Connector
JP11

+5VS

Placea caps. near ODD CONN.

1
C615

10U_0805_10V4Z

1U_0603_10V4Z

1
C614

C613

0.1U_0402_16V4Z

C616
10U_0805_10V4Z

15
14

GND
GND

GND
A+
AGND
BB+
GND

1
2
3
4
5
6
7

DP
V5
V5
MD
GND
GND

8
9
10
11
12
13

SATA_TXP4
SATA_TXN4
0.01U_0402_16V7K
SATA_RXN4
2
SATA_RXP4
2
0.01U_0402_16V7K

SATA_TXP4 28
SATA_TXN4 28

1 C612 SATA_RXN4_C
1 C611 SATA_RXP4_C

SATA_RXN4_C 28
SATA_RXP4_C 28

Near CONN side.

+5VS

SUYIN_127382FR013G509ZR
CONN@

SI: Update ODD footprint to fix pin reverse issue

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

HDD/CDROM

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

31

of

53

Place Close to Chip

U18
10 PCIE_PTX_C_IRX_P3
10 PCIE_PTX_C_IRX_N3

C485

C488

0.1U_0402_16V7K
PCIE_PTX_IRX_P3
1
PCIE_PTX_IRX_N3
1
0.1U_0402_16V7K

10 PCIE_ITX_C_PRX_P3

30

HSON

23

HSIP
HSIN

33

CLKREQB

22 CLK_PCIE_LAN

26

REFCLK_P

22 CLK_PCIE_LAN#

27

REFCLK_N

20

PERSTB

11,14,15,26,33,34,40,41

PLT_RST#
+CTRL_18

+3V_LAN
R408 1

2 2.49K_0402_1%

27,33 LAN_PCIE_WAKE#
ISOLATE#

SROUT12

FB12

62

ENSR

64

RSET

19

LANWAKEB

36

ISOLATEB

LAN_X1

60

CKTAL1

LAN_X2

61

CKTAL2

R384
@ 1K_0402_1%

65

R398
2

28 LAN_ISOLATE#

25

ISOLATE#

31

3
4
6
7
9
10
12
13
21
32
38
43
49
52

EVDD12
EVDD12

22
28

VDD33
VDD33
VDD33
VDD33

16
37
46
53

VDDSR

63

AVDD33
AVDD33

2
59

AVDD12
AVDD12
AVDD12
AVDD12

8
11
14
58

IGPIO
OGPIO

50
51

EGND
EGND

15
17
18
34
35
39
40
41
42

NC
NC
NC
NC
NC
NC
NC
NC
NC

4
3
2
1

DO
DI
SK
CS

GND
NC
NC
VCC

5
6
7
8

C618
+3V_LAN

1
0.1U_0402_16V4Z

C620
0.1U_0402_16V4Z

C621
0.1U_0402_16V4Z

C622
0.1U_0402_16V4Z

C623
0.1U_0402_16V4Z

AT93C46-10SI-2.7_SO8
LAN_LINK#
LAN_ACTIVITY#

+LAN_VDD12

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

4.7UH_1008HC-472EJFS-A_5%_1008
L71
1
2

+CTRL_18

+LAN_EVDD12
1

L72
0_0603_5%

C627
1

+LAN_VDD12

Close to Pin1

C632
0.1U_0402_16V4Z

C633
0.1U_0402_16V4Z
+LAN_VDD12

+LAN_EVDD12

C636
0.1U_0402_16V4Z

C637
0.1U_0402_16V4Z

C638
0.1U_0402_16V4Z

C639
0.1U_0402_16V4Z

C640
0.1U_0402_16V4Z

C641
0.1U_0402_16V4Z

+3V_LAN

L75
0_0603_5%

+3V_LAN

EXPOSE_PAD

C635
2
+AVDD33

0.1U_0402_16V4Z
1

C634

1K_0402_1%
R401
15K_0402_5%

U17
LAN_DO
LAN_DI
LAN_SK
LAN_CS

C626
22U_0805_6.3V6M

DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12

+3VS

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

+3V_LAN

Close to Pin16,37,46,53

+3V_LAN

0.1U_0402_16V4Z

+LAN_VDD12

LED3
LED2
LED1
LED0

54
55
56
57

2
3.6K_0402_5%

C
1
1
1
8
r
o
f
A
dm
a
0
e
B0
3

22 CLKREQ_LAN

LAN_DO
LAN_DI
LAN_SK
LAN_CS

45
47
48
44

EEDO
EEDI/AUX
EESK
EECS

e
k
o
h
c
H
u
7
.
4

HSOP

24

10 PCIE_ITX_C_PRX_N3

1
R382

29

C644
0.1U_0402_16V4Z

C645
0.1U_0402_16V4Z

C646
0.1U_0402_16V4Z

C647
0.1U_0402_16V4Z

C648
0.1U_0402_16V4Z

10U_0805_10V4Z

+LAN_VDD12

+3V_LAN
L74
+AVDD33
C650

PAD T30
DSM#
2
0_0402_5%

1
R399

0.1U_0402_16V4Z

LAN_DSM# 27

0_0603_5%
C651

0.1U_0402_16V4Z

RTL8111C-GR_QFN64_9X9

Close to Pin2 & pin59

Y1
LAN_X1 2

1LAN_X2
25MHZ_20P

C182
27P_0402_50V8J

C181
27P_0402_50V8J
PJP6
1

+3VALW

2
PAD-OPEN 4x4m

40 mils
1

+3V_LAN

C707
1

1
41

1
R715

LANPWR

R713
@ 100K_0402_5%

2
10K_0402_5%

Q61
SI2301BDS-T1-E3_SOT23-3

0.1U_0402_16V4Z

LAN Conn.
JP12
13

Yellow LED+

1 300_0402_5%

14

Yellow LED-

RJ45_MIDI3-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

+3V_LAN
LAN_ACTIVITY#
U19

7
8
9

LAN_MDI1LAN_MDI1+

10
11
12

24
23
22

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

C607 0.01U_0603_100V4Z
2
1

R393
1

75_0402_1%
2

C610 0.01U_0603_100V4Z
2
1

R394
1

75_0402_1%
2

C619 0.01U_0603_100V4Z
2
1

R396
1

RJ45_MIDI3RJ45_MIDI3+
RJ45_MIDI2RJ45_MIDI2+

RJ45_MIDI3- 43
RJ45_MIDI3+ 43

C659
0.01U_0402_16V7K
4

RJ45_MIDI2- 43
RJ45_MIDI2+ 43

C656
@68P_0402_50V8K

75_0402_1%
2

RJ45_MIDI0RJ45_MIDI0+

RJ45_MIDI1- 43
RJ45_MIDI1+ 43

D39
PSOT24C_SOT23-3
@

RJ45_MIDI0- 43
RJ45_MIDI0+ 43

PR3-

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

PR1+

C657
@68P_0402_50V8K +3V_LAN
1 R395
2
1 300_0402_5%

11

LAN_LINK#

12

C663
0.01U_0402_16V7K

10

SHLD1

15

Green LEDLANGND

C658
1000P_1808_3KV7K

C664
0.01U_0402_16V7K

Compal Secret Data

Security Classification

Place these components

colsed to LAN chip

Issued Date

2007/08/02

Deciphered Date

2008/08/02

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

DETCET PIN2
Green LED+

FOX_JM36113-P1122-7F

DETECT PIN1

RJ45_MIDI2LAN_LINK#

RJ45_MIDI1RJ45_MIDI1+

16

SHLD1
PR4-

RJ45_MIDI2+

LAN_ACTIVITY#

NS892402
C660
0.01U_0402_16V7K

PV:Add ESD diode for EMI request

LAN_MDI0LAN_MDI0+

MCT1
MX1+
MX1-

75_0402_1%
RJ45_GND
2

4
5
6

LAN_MDI2LAN_MDI2+

TCT1
TD1+
TD1-

R392
1

1
2
3

LAN_MDI3LAN_MDI3+

C600 0.01U_0603_100V4Z
2
1

R391

Title

C661
0.1U_0402_16V4Z

C662
4.7U_0805_10V4Z

Compal Electronics, Inc.

RTL8111C/8102E 10/100/1000 LAN

Size
C
Date:

Document Number

Rev
0.4

LA-4092P
Thursday, February 21, 2008
E

Sheet

32

of

53

Mini Card---TV tuner

SI2: chagne power plan from +3VALW to +3VS_TV
+1.5VS_TV
+3VS_TV

+3VS_TV
0.01U_0402_16V7K

4.7U_0805_10V4Z

C665

2
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C666

C667

C668

C669

C670

0.1U_0402_16V4Z
1

New Card
+1.5VS

+3VS
C679
2
1 0.1U_0402_16V4Z
2
C680

+3VALW
11,14,15,26,32,34,40,41

1 0.1U_0402_16V4Z
PLT_RST#

36,41,44,46,49,52 SUSP#
+3VALW

1.5Vin
1.5Vin

2
4

3.3Vin
3.3Vin

41,44,48 SYSON

27

12
14

17

PLT_RST#

2
R412

EXP_CPPE#

1@ 100K_0402_5%
EXP_CPPE#

Power Switch internal pull high

22 CLKREQ_MCARD1#

U21

C681
2
1 0.1U_0402_16V4Z

AUX_IN

1.5Vout
1.5Vout

11
13

+1.5VS_PEC

3.3Vout
3.3Vout

3
5

+3VS_PEC

SYSRST#

PERST#

STBY#

NC

18

CPPE#

22 CLK_PCIE_MCARD1#
22 CLK_PCIE_MCARD1

10 PCIE_PTX_C_IRX_N5
10 PCIE_PTX_C_IRX_P5

+3V_PEC

19

OC#

SHDN#

15

AUX_OUT

20

10

CONN@
JP14

SI: Exchange TV & WLAN

minicard location

10 PCIE_ITX_C_PRX_N5
10 PCIE_ITX_C_PRX_P5

PERST#

8
16

+3VS_TV

GND

CPUSB#
THERMAL_PAD
RCLKEN

21

R5538D001-TR-F_QFN20_4X4~D

USE TI TPS2231MRGPR

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

53

GND1GND2

54

+3VS_TV
+1.5VS_TV

SI2: chagne power plan from +3VALW to +3VS_TV

PLT_RST#
+3VS_TV
+1.5VS_TV

SMB_CK_CLK1
SMB_CK_DAT1

USB20_N10 27
USB20_P10 27

+1.5VS_TV
+3VS_TV

MOLEX 67910-0002 52P

+1.5VS

R406 1

2 0_1206_5%

+1.5VS_TV

+3VS

R407 1

2 0_1206_5%

+3VS_TV

Mini-Express Card---WLAN
+3VS_WLAN
0.01U_0402_16V7K

Near to Express Card slot.

USB20_N11
USB20_P11

27 SMB_CK_CLK1
27 SMB_CK_DAT1
+1.5VS_PEC
+1.5VS_PEC
27,32 MINI_PCIE_WAKE#
+3V_PEC

EXP_CPPE#

MINI_PCIE_WAKE#
PERST#

+3VS_PEC
22 CLKREQ_NCARD#
22 CLK_PCIE_NCARD#
22 CLK_PCIE_NCARD
10 PCIE_PTX_C_IRX_N0
10 PCIE_PTX_C_IRX_P0
10 PCIE_ITX_C_PRX_N0
10 PCIE_ITX_C_PRX_P0

EXP_CPPE#

27
28

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND1
GND2

SHIELD
SHIELD

C677

C678
2

28 BT_COMBO_EN#

2
0.1U_0402_16V4Z

2 CH_CLK
0_0402_5%

1
R547

4.7U_0805_10V4Z
1
1

R556
1

0_0402_5%
2

CH_DATA
CH_CLK
CH_CLK
22 CLKREQ_MCARD2#
22 CLK_PCIE_MCARD2#
22 CLK_PCIE_MCARD2

10 PCIE_PTX_C_IRX_N2
10 PCIE_PTX_C_IRX_P2

4.7U_0805_10V4Z
1
C684

C685
2

SANTA_131851-A_LT

10 PCIE_ITX_C_PRX_N2
10 PCIE_ITX_C_PRX_P2

+3VS_WLAN

2
0.1U_0402_16V4Z

CONN@
4

2007/08/02

GND1GND2

54

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

+3VS_WLAN

L78

2 0_1206_5%

L79

2 0_1206_5%

+1.5VS

PLT_RST#
+3VAUX

XMIT_OFF# 28
R634 1
R635 1

2 @ 0_0603_5%
0_0603_5%
2

+3VALW
+3VS

SMB_CK_CLK1
SMB_CK_DAT1
USB20_N8 27
USB20_P8 27
WL_LED# 42

SI: Exchange TV & WLAN

minicard location

Compal Secret Data

Security Classification

C784
0.1U_0402_16V4Z

+3VS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

MOLEX 67910-0002 52P

CONN@
JP26
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

Issued Date

C783

+1.5VS_WLAN

MINI_PCIE_WAKE#
39
39

+3V_PEC

0.1U_0402_16V4Z

0.1U_0402_16V4Z

29
30

C781 C782

C682
2

R553
4.7K_0402_5%

+1.5VS_PEC

C683

C787

+3VALW

4.7U_0805_10V4Z

27
27

+1.5VS_WLAN
0.01U_0402_16V7K

0.1U_0402_16V4Z

C786

4.7U_0805_10V4Z

JP16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

C785

+3VS_PEC

4.7U_0805_10V4Z

Title

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Express Card

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

33

of

53

SI:Per ME request change

JP21 to new one

Card Reader Connector

JP21
3

+VCC_4IN1
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

+VCC_4IN1

SDCMD_MSBS_XDWE# 34
XDWP#_SDWP#
33
XD_ALE
35
XD_CD#
40
XD_RB#
39
XD_RE#
38
XDCE#
37
XD_CLE
36

R45
2 XDWP#_SDWP#
XD_RB#
2

XDCE#

C901
R411
100P_0402_25V8K @ 100_0402_5% @

+3VS

41
42

SD-WP-SW

XDWP#_SDWP#

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

7IN1 GND
7IN1 GND

SDCLK

MSCLK

7IN1 GND
7IN1 GND

1
C892

C688

1
D

2 2
G
3

22 CLK_PCIE_MCARD0#
22 CLK_PCIE_MCARD0

CPPE#

10 PCIE_ITX_C_PRX_N1
10 PCIE_ITX_C_PRX_P1

2N7002_SOT23-3
10 PCIE_PTX_C_IRX_N1
10 PCIE_PTX_C_IRX_P1
XDCD0#_SDCD#

C693 1
C697 1

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

2
8.2K_0402_5%

XIN
XOUT

+3VS
1
2
C695 0.1U_0402_16V4Z

SI:Use build in Regulator

Chip mount R383,C689,C694

+5VS

C687

R370
470_0402_5%
2 2

C694
0.1U_0402_16V4Z

PLT_RST#

9
8

APRXN
APRXP

11
12

APTXN
APTXP

APVDD
APV18
DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDWP#
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

TPA1P
TPBIAS_1
TREXT

34
35
36

TPA+
TPBIAS
TREXT

APREXT

38
39

TXIN
TXOUT

30

TAV33

1
2

XRSTN
XTEST

JMB380

CPPE#

13
14

SEEDAT
SEECLK

XDCD1#_MSCD#
XDCD0#_SDCD#

15
16

CR1_CD1N
CR1_CD0N

D5
HT-F196BP5_WHITE

17

+VCC_OUT
1

C689
10U_0805_10V4Z

11,14,15,26,32,33,40,41

APCLKN
APCLKP

0_0603_5%

@ 0_0603_5%

C893
2

SI:Use build in Regulator

Chip unmount R387

2
0.1U_0402_16V4Z

+3VS

4.7K_0402_5% R111
1
2 XDCD1#_MSCD#

CR_LED#
Q53
CR_LED#
2
G
2N7002_SOT23-3
R113
4.7K_0402_5%

21

TCPS
TPB1N
TPB1P
TPA1N

24
31
32
33

GND

49

CR1_PCTLN
CR1_LEDN

C692

2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

+1.8VS_OUT
1

C686
2

C690
0.1U_0402_16V4Z

0.1U_0402_16V4Z

SDCLK_MSCLK_XDCE#

2
22_0402_5% 2
22_0402_5% 2
22_0402_5%

D40
1
R124

2
12K_0402_1%

TPBTPB+
TPA-

SI2: Use B version chip

C899

R140

R133
56_0402_5%
2

2
3
4

@ 0.1U_0402_16V4Z

2
2

1
5

22P_0402_50V8J

R200
56_0402_5%

TPBIAS

1
2
3
4

TPBTPB+ GND
TPA- GND
TPA+

5
6

@ SUYIN_020115FR004S550ZL_4P-T
R290
56_0402_5%

R134

2
XOUT

1
C177
0.33U_0603_10V7K

2
4

1M_0402_5%

GND

@ G5250C2T1U_SOT23-5

C896
2

@ 1U_0603_10V4Z

@
150K_0402_5%
R123

Compal Secret Data

Security Classification
2007/08/02

Issued Date

reserved power circuit

C696
270P_0402_50V7K

OUT
OUT

C895

IN
EN

TPBTPB+
TPATPA+

XIN

X2
24.576MHz_16P_3XG-24576-43E1
C898

U22

XD_CD#

JP19
4.99K_0402_1%

+3VS

R199
56_0402_5%

C897

40mil

SI:Change 1394 connector

1

22P_0402_50V8J

+VCC_4IN1

XDCD0#_SDCD#

JMB380-QGAZ0A_QFN48_7X7

+VCC_OUT

XDCD1#_MSCD#

Close to Chip

220P_0402_50V7K 2

SI:Use new chip ,change to

High active control
SI:Use build in Regulator
Chip unmount U22 and relation parts

SDCLK
MSCLK
XDCE#

1
1 R457
1 R456
R455

DAN202U_SC70

4.7K_0402_5% R121
1
2XDCD0#_SDCD#

APGND

C691

5
10

+VCC_4IN1
R383
1

1000P_0402_50V7K
1
1

+3VS
1

3
4

1
R114

SI:Per Jmicro request change

R114 from 10K to 8.2K

+VCC_OUT

Power Circuit
U23

0_0402_5%
1
2
R397

CR_WAKE#

2 1

+1.8VS

0.1U_0402_16V4Z
1

10K_0402_5%

28

R410
C900
@ 100_0402_5% @ 100P_0402_25V8K

2
2
10U_0805_10V4Z

Q54
1

R387

SI2:Support D3E function

R126
2

+1.8VS_OUT

CONN@

CR_CPPE#

R413
C902
@ 100_0402_5% @ 100P_0402_25V8K

TAITW_R015-B10-LM

+3VS

27

XD_RE#

XD_ALE

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

+VCC_4IN1

1
R86

11
31

SI:Per Jmicro request change

R405 & R122 from 200K to 10K

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

XD_CLE

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

200K_0402_5%

1
R405
1
R122

21
28

10K_0402_5%

7 IN 1 CONN

10K_0402_5%

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

2
R106

SD-VCC
MS-VCC

XD-VCC

10K_0402_5%
1
10K_0402_5%
1

32
10
9
8
7
6
5
4

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

Compal Electronics, Inc.

JMB380/385 card reader/1394

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

34

of

53

ACCELEROMETER

U66
+3VS

C1031

Vdd_IO

GND

SDA / SDI / SDO

13

SDO

12

Reserved

GND

Reserved
GND

11
10

GND

INT 2

Vdd

INT 1

SMB_CK_DAT0 8,9,22,27

Pin12(internal pull high ) pull up I2C address :0011101b

pull low I2C address:0011100b

ACCEL_INT 26

CS

10U_0805_6.3V6M

C1030

0.1U_0402_16V4Z

+3VS

SCL / SPC

14

SMB_CK_CLK0 8,9,22,27

+3VS

2
R964

LIS302DLTR_LGA14_3x5

1
10K_0402_5%

I2C address:0111000Xb
+3VS
U68

SCK

INT

SDI

SDO

reserved

GND

GND

11

GND

12

10
1

reserved

1
C830

2
@ 0.1U_0402_16V4Z
+3VS

ACCEL_INT 26

C829

VDD

10U_0805_6.3V6M

8,9,22,27 SMB_CK_DAT0
B

CSB

C828

8,9,22,27 SMB_CK_CLK0

VDDIO
5

0.1U_0402_16V4Z

+3VS

@ BMA150_LGA12

SI: Reserve Bosch solution

Compal Secret Data

Security Classification
Issued Date

2006/08/04

Deciphered Date

2006/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

R5C833_1394

Size Document Number

Custom LA-4092P
Date:

Rev
0.4

Thursday, February 21, 2008

1

Sheet

35

of

53

CODEC POWER

0212_Change to +5VALW.
+5VALW

W=40Mil
C728

+VDDA_CODEC

U32

2
0.1U_0402_16V4Z

IN

GND

33,41,44,46,49,52 SUSP#

SHDN

OUT

BYP

G9191-475T1U_SOT23-5 1

C729

C731
1U_0603_10V4Z

C730
0.1U_0402_16V4Z

C904
0.1U_0402_16V4Z

C733
0.1U_0402_16V4Z

+VDDA_CODEC

2.2U_0805_16V4Z

C734
1U_0603_10V4Z

+3VS

+3VDD_CODEC
R885
1
2
BLM18BD601SN1D_0603
1

C732

(4.75V)
300mA
1

0.1U_0402_16V4Z

U27
DVDD_CORE*

DVDD_CORE

25

AVDD1*

38

AVDD2**

32
HDA_BITCLK_CODEC

27 HDA_BITCLK_CODEC

27 HDA_SDOUT_CODEC
R522 1

27 HDA_SDIN0

PV: add bead for EMI

24

DMIC_CLK

41

EC_BEEP

27

SB_SPKR

R537
R524

R523

2
L58
1
2
47K_0402_5%
1
2
47K_0402_5%

1
1
2
FBMA-L10-160808-301LMT_0603 R230
22_0402_5%
2
1
C913 1U_0603_10V4Z
MONO_INR
1
2
C955 0.1U_0402_16V4Z

31
43

MONO_OUT

GPIO 6

44

SPDIF OUT1 / GPIO 7

45

SPDIF OUT0

48

SI2: change to SPDIF to pin 45

VREFOUT-B

28

+VREFOUT_B 37

VREFOUT-C

29

BITCLK

SDI_CODEC

27 HDA_RST#_CODEC

SYNC

43

R584 1
R916 1

SENSEB#

C979

HDA_BITCLK_CODEC
10U_0805_10V4Z
C744 1
+VC_REFA
2

SENSE_A

13

DMIC_CLK

33

CAP2

PORTA_R

41

HP_OUTR

12

PCBEEP

PORTA_L

39

HP_OUTL

5.1K_0402_1% 2
20K_0402_1% 2
39.2K_0402_1% 2
@ 10K_0402_1% 2
0.1U_0402_16V4Z 2
HP_OUTR 37

PORTB_R

22

MIC_EXT_R

PORTB_L

21

MIC_EXT_L

C907 1

34

SENSE_B / NC

37

NC

PORTC_R

24

MIC_IN_R

18

NC

PORTC_L

23

MIC_IN_L

19

NC
PORTD_R

36

LINE_OUT_R

20

NC
PORTD_L

35

LINE_OUT_L

HP Jack & Dock

MIC_EXTR 37
MIC_EXTL 37

27

VREFFILT

PORTE_R

15

DOCK_MICR

26

AVSS1*

PORTE_L

14

DOCK_MICL

42

AVSS2**

DVSS**

MIC_IN_R 37

Internal MIC

MIC_IN_L 37
LINE_OUT_R 37,38

Internal SPKR.

LINE_OUT_L 37,38
C972
1
C973
1

1U_0603_10V6K
2

PORTF_R

17

PORTF_L

16

1
R943
1
R944

1U_0603_10V6K

2
R910

2
10K_0402_5%
2
10K_0402_5%

DOCK_MIC_R 43

DOCK MIC

DOCK_MIC_L 43

R911
3

1.21K_0402_1%

1.21K_0402_1%

C745
@ 33P_0402_50V8K

Jack MIC

1U_0603_10V4Z

+VDDA_CODEC
EXTMIC_DET# 37
JACK_DET# 37,43
INTMIC_DET# 37

HP_OUTL 37
1U_0603_10V4Z
C908 1
2

NC / OTP

R548
1
R569
1
R571
1
R570
1
1 C951

R525
@ 47_0402_5%

SPDIF_OUT 43

46

0.1U_0402_16V4Z

SPDIF_OUT

SENSEA#

40

2 5.1K_0402_1%
2 39.2K_0402_1%

SUB_ENABLE 38

RESET#

2 0.1U_0402_16V4Z
+VDDA_CODEC
SENSE_B#

30

GPIO 5

SDO

11

DVDD_IO

8
10

DMIC_DAT 24

VOL_DN/DMIC_1/GPIO 2

VREFOUT-E / GPIO 4

27 HDA_SYNC_CODEC

2 10K_0402_5%

C956

2 33_0402_5%

EAPD_CODEC 41

GPIO 3

+3VDD_CODEC

47

VOL_UP/DMIC_0/GPIO 1

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

+VDDA_CODEC

+3VDD_CODEC

92HD71B7X5NLGXA1X8_QFN48_7X7

1/10*Vin
need close to Codec

SI2: Use new version Codec

C746
1
2
@ 1000P_0402_25V8J

SENSE A

SENSE B

Port

Resistor

Port

Resistor

39.2K

39.2K

20K

20K

10K

10K

C747
1
2
@ 1000P_0402_25V8J
C748
1
2
@ 1000P_0402_25V8J
C749
1
2
@ 1000P_0402_25V8J
R195 1

HP_DET#

MIC_DET

0(LOW)

0(LOW)

NC

5.11K

R198
1
2
@ 0_0805_5%

NC

0(LOW)

2 0_1206_5%

0(LOW)

NC
GNDA

NC

GNDA

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

PORT-A
<Earphone OUT>

MIC

EQ

OFF

ON

ON

Disable

OFF

ON

OFF

Disable

ON

OFF

ON

Enable

ON

OFF

OFF

Enable

37,38,43

5.11K
GND

LINEOUT

Title

Compal Electronics, Inc.

Audio Codec-IDT9271B7

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

36

of

53

PV:change cap form 100uF

7
SPKR+

36

RIN+

ROUT+

17

RIN-

ROUT-

SPKR-

R703 2
1
7.5K_0402_1%
R704 2
1
7.5K_0402_1%

12

LIN+

LOUT+

SPKL+

13

LIN-

LOUT-

SPKL-

15

RBYPASS

11

LBYPASS

Keep 10 mil width

SI2:change from 0.047u to 0.1u

LVDD

C765
2

C767

NC

20

NC

18

GND

NC

10

GND

NC

1U_0603_10V4Z
1U_0603_10V4Z

THERMAL_PAD

SI2:change from 10u to 1u for

PA PA sound issue

1
2
3
4
5
6
7
8
9
10
11
12
13
14

HP_OUT_R
HP_OUT_L

2 HP_OUT_L
150U_D_6.3VM

EXTMIC_DET#
HP_DET#

36 EXTMIC_DET#

HP OUT For M/B

41,43

CIR_IN

CIR_IN
+5VL

36 +VREFOUT_B

1
C818

C766

1
C941

HP_OUTL

R907
4.7K_0402_5%

21

TPA6020A2RGWR_QFN20_5x5

36

MIC_EXTR

36

MIC_EXTL

1
2
3
4
5
6
7
8
9
10
11
12
13
14

ACES_87213-1400G

R909 0_0402_5%
1
1

0.1U_0402_16V7K

LS/D

16

0.1U_0402_16V7K
36,38 LINE_OUT_L

1
C776
1
C817

9
R701 2
1
7.5K_0402_1%
R702 2
1
7.5K_0402_1%

MIC_EXTR
MIC_EXTL

HP_OUT_R
2
150U_D_6.3VM

0.1U_0402_16V7K

1
C940

HP_OUTR

0.1U_0402_16V7K
36,38 LINE_OUT_R

1
C770
1
C775

RVDD

JP17
36

2
0_1206_5%

10U_0805_10V4Z

RS/D

19

10U_0805_10V4Z

38,41 EC_MUTE#

R594
1

14

U28
EC_MUTE#

to 150uF

+5VS

+5VAMP

SI2:change from 12.7K to 7.5K

2
CONN@

C742
1U_0603_10V4Z
R908
4.7K_0402_5%

MIC_EXTR
MIC_EXTL

+3VALW
2

JACK_DET# 36,43

R46
10K_0402_5%

B+

R871

5
Q20B
2

330K_0402_5%

2N7002DW-7-F_SOT363-6
+3VALW

PV:change cap form 100uF

1
C854
2
<BOM Structure>
5

Q20A

36

HP_OUTR

2N7002DW-7-F_SOT363-6
2

DOCK_R 1

Q22B
2N7002DW-7-F_SOT363-6

C945
HP_DET#

36

JP20

@ 2N7002_SOT23-3

GND1
GND2
ACES_88231-04001
CONN@

INTMIC_DET#
D
@ 2N7002_SOT23-3

Q28
2
G

R957
@ 100K_0402_5%

DOCK_LOUT_L 43

SPEAKER
JP15
1
2
3
4

5
6
1

1
2
3
4
GND1
GND2
ACES_88231-04001
CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

44.2_0603_1%
2

36

Q27
2
G

SPKL+
SPKLSPKR+
SPKRC763
220P_0402_50V7K

5
6

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

1
2
3
4

C762
220P_0402_50V7K

1
2
3
4

C761
220P_0402_50V7K

@ 1U_0603_10V6K
MICIN_L
1
2
MICIN_R
1
2
C971
@ 1U_0603_10V6K
2
1
+3VS
R956
@
10K_0402_5%
41 ANA_MIC_DET
C970

MIC_IN_L
MIC_IN_R

R607
1

SI: change 2n7002 to dual package

C760
220P_0402_50V7K

1
2

C743 @ 1U_0603_10V4Z
R905
@ 4.7K_0402_5%

HP OUT For Docking

R555
@ 10K_0402_5%

150U_D_6.3VM

1
2

44.2_0603_1%
2
DOCK_LOUT_R 43

R906 @ 0_0402_5%
1

R904
@ 4.7K_0402_5%

36
36

Q22A
2N7002DW-7-F_SOT363-6

+3VS

Analog MIC
2

HP_OUTL

DOCK_L

C946

SI: change 2n7002 to dual package

R602
1

150U_D_6.3VM

+VDDA_CODEC

to 150uF

SI2: Add cap & 44.2 ohm for dock

2
R47
10K_0402_5%

0.01U_0402_25V7K
Q21
2
2N7002_SOT23-3 G

Title

Compal Electronics, Inc.

AMP & Audio Jack

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

37

of

53

@
R917

SI2: Change C980,C990 from 0.056u to 0.027u

1

0_0603_5%

C980
1
2
+VDDA_CODEC 0.027u_0402_16V7K

+VREF

SI2: Change C982 from 0.039u to 5600p

C981
1
2

SI2: Change C984 from 0.039u to 0.027u

+VREF

+VREF

TLV2464_TSSOP14

U41D
12

13

OUT

1U_0603_10V4Z

BASS_OUT

14

TLV2464_TSSOP14

SI2: Change C987 from 0.47u to 0.056u

C992
100P_0402_50V8J
C993
1
2

R927
1
2
30.1K_0402_1%

U41C

10

OUT

0.027u_0402_16V7K

+VREF

+VDDA_CODEC 0.027u_0402_16V7K

+VREF

0.056uF_0603_16V

C988
1

R926
1

11

C991

4
OUT

C985
R924
1
2
60.4K_0402_1%
C990
1
2

C987
1
2

U41A
3

R925
1
2
20K_0402_1%

11

36,37 LINE_OUT_L

C989
1
2
1U_0603_10V4Z

100P_0402_50V8J

36,37 LINE_OUT_R

R923
1
2
20K_0402_1%

+VDDA_CODEC

TLV2464_TSSOP14

R922
10K_0402_1%
C986
1
2
1U_0603_10V4Z

10K_0402_1%

10K_0402_1%

R918
1
2

11

OUT

100P_0402_50V8J

0.027u_0402_16V7K

+VDDA_CODEC

10K_0402_1%

C984
1
2

R919
1

R920
1
2
30.1K_0402_1%

U41B

11

5600P_0402_25V7K
R921
1
2

C983
100P_0402_50V8J

5600P_0402_25V7K
C982
1
2

10K_0402_1%
TLV2464_TSSOP14

R928
10K_0402_1%
2

R929
1
2
60.4K_0402_1%

+VDDA_CODEC

SI2: Change C984 from 0.039u to 0.027u

+VREF

R930
1

4.7U_0805_10V4Z

0.1U_0402_16V7K

10K_0603_5%

R932
10K_0603_5%

1
C995
2

1
C996
2
C1021
4.7U_0805_25V6-K
1
2
D82

B+

SI: Change D82 & D83 to LLDS package

D83

1 2

RLS4148_LLDS2

1
2

RLS4148_LLDS2

2
C1023

+VDDA_CODEC

1U_0805_25V4Z

R934
1K_0402_5%

C1024
1

1U_0805_25V4Z

@
R935
0_0402_5%
+VCC_WOOF

GAIN1

SHUTDOWN

VCLAMP

R942

1
C1014
0.22U_0402_10V4Z

1
2
51_0402_5%
1
2
51_0402_5%

BSN

17

BSP

16
9

OUTP
OUTP

14
15

OUTN
OUTN

10
11

2 220P_0402_50V7K
2 120K_0402_5%

C1009

C1017

C1016

18
19

AGND
AGND

JP13
SUBWOOF+

L57

SUBWOOF-

L59

PGND
PGND
PGND

6
12
13

SUBWOOF_L+

1
2
BLM18PG121SN1D_0603
1
2
BLM18PG121SN1D_0603

BAT54AW_SOT323-3~D

1
C1015
0.22U_0402_10V4Z

PVCC
PVCC

C1010 1
R939 1

C1008

2 0_1206_5%

Need check

C1011
1U_0603_10V4Z
R941

21
20

2 1U_0603_10V4Z
2 2.2U_0603_10V6K

COSC
ROSC

1
1

4.7U_0805_25V6-K

C1003
C1004

4.7U_0805_25V6-K

GAIN0

23
22

1U_0805_25V6K
2
1

VREF
BYPASS

SUBWOOF_L-

C1012

D44

SI: Change D44 to dual package

C1013

1000P_0402_50V7K

37,41 EC_MUTE#
36 SUB_ENABLE

2 10K_0402_5%
2 0_0402_5%
2@ 0_0402_5%

INP

R931 1

1000P_0402_50V7K

R940 1
R633 1
R632 1

INN

+VCC_WOOF

R937 1
2
0_0402_5%
@ R938 1
2
0_0402_5%

24

2
0.47U_0603_16V6K
2
0.47U_0603_16V6K

VCC

1U_0805_25V6K
2
1

BASS_OUT 1
C1002
1
C1005

U60

1
2

1
2

3
4

GND
GND

ACES_88231-02001
CONN@

SUB wooffer

HPA00304PWR_TSSOP24

SI: Change C1012 & C1013 to 1000P to

reduce power consumption

Compal Secret Data

Security Classification
2006/10/26

Issued Date

2006/07/26

Deciphered Date

Title

EQ & Sub Woofer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Size Document Number

Custom
Date:

Rev
0.4

LA-4092P
Sheet

Thursday, February 21, 2008

E

38

of

53

Left side

USB CONNECTOR 0

+5VALW

Left side
+USB_VCCA

ESATA/USB combination Connector

GND
OUT
IN
OUT
IN
OUT
EN#
OC#
THERMAL_PAD

TPS2061IDGN_MSOP8~N

W=100mils
1
+
2

27

1000P_0402_50V7K
C791

+USB_VCCA

JP27

L46
8
7
6
5
9

0.1U_0402_16V4Z
C790

4.7U_0805_10V4Z

1
2
3
4

C789
150U_D_6.3VM

+USB_VCCA
U40

C788

27

USB20_N4

USB20_P4

4
1

USB20_N4_R
USB20_P4_R

WCM-2012-900T_0805
2
D8
+5VALW

USB_EN#

USB20_N4_R

VIN

IO1

IO2 GND

USB20_P4_R

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND
GND
GND
GND

WCM-2012-900T_0805
USB20_N2

27

USB20_P2

4
L51

28
28

SUYIN_020173MR004S50TZL_4P-T

1
2
3
4

USB20_N2_R
USB20_P2_R

C792 2
C793 2

1 0.01U_0402_16V7K SATA_RXN5
1 0.01U_0402_16V7K SATA_RXP5

SI: change new footprint

@ PRTR5V0U2X_SOT143-4

B_VCC
B_DB_D+
B_GND

5
6
7
8
9
10
11

SATA_TXP5
SATA_TXN5

SATA_TXP5
SATA_TXN5

28 SATA_RXN5_C
28 SATA_RXP5_C

CONN@

JP28

27

GND
A+
AGND
BB+
GND

USB

ESATA
12
13
14
15

SHIELD
SHIELD
SHIELD
SHIELD

TYCO_1759576-1
CONN@

SI: change new footprint

D11
+5VALW
SATA_TXN5

VIN

IO1

IO2 GND

SATA_TXP5

D9
4

+5VALW

@ PRTR5V0U2X_SOT143-4

USB20_N2_R3

IO1

IO2 GND

VIN

USB20_P2_R

@ PRTR5V0U2X_SOT143-4
D12

Touch screen

+5VALW
SATA_RXP5

JP18

USB Board Conn

2

1
2
3
4
5
GND1
GND2

JP47
1
2
3
4
5
6
7
8
9
10

+5VALW

41
27
27

USB_EN#
USB20_N0
USB20_P0

27
27

USB20_N1
USB20_P1

11
12

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7

VIN

IO1

IO2 GND

SATA_RXN5

SI: new add for ESD

@ PRTR5V0U2X_SOT143-4

+5VS
USB10_N12 27
USB10_P12 27

ACES_88266-05001
CONN@

GND1
GND2
ACES_87213-1000G
CONN@

BT Connector

CONN@
ACES_87213-0800G
10

Finger printer

USB20_N6

IO1

IO2 GND

USB20_P7

2
1

USB20_P6

+3VS

+3VAUX_BT

0.1U_0402_16V4Z

1
2
3
4
5
6
GND
GND

2
C798
1U_0603_10V4Z

3
1

1
2
3
4
5
6
7
8

C802

R519

SI2301BDS_SOT23

0.1U_0402_16V4Z

100K_0402_5%

C799

C800

0.01U_0402_16V7K

ACES_85201-06051
CONN@

PRTR5V0U2X_SOT143-4

IO1

IO2 GND

C801

VIN

VIN

2
@ 0_0603_5%

D21

USB20_N7

D16
+5VALW

JP39

1
R582

0612 no install

Q24

USB20_N7
USB20_P7

USB20_N7
USB20_P7

27
27
42
33
33

@ PRTR5V0U2X_SOT143-4

2
0_0603_5%

C832

2
27
27

USB20_P6
USB20_N6
BT_LED
CH_DATA
CH_CLK

1K_0402_5%
1K_0402_5%

2
2

USB_EN#

+5VALW

1
R581

@ R517 1
@R517
@R518
@
R518 1

0.1U_0402_16V4Z

41

+3VS_FB
1

+3VAUX_BT
USB20_P6
USB20_N6

1
@ SI2301BDS_SOT23

8
7
6
5
4
3
2
1

SI2: change form

+3VALW to +3VS

+3VS

2
@ 0_0603_5%

+3VALW

1
R622
Q31

GND 8
7
6
5
4
3
2
GND 1
JP32

4.7U_0805_10V4Z

R520

SI: Change finger print footprint

28

BT_OFF

10K_0402_5%
4

PV: Change PN to SC300000K00 for ESD request

SI: change to 10K ohm to make
sure MOS can turn on
Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

39

of

53

+3VL

SI2: Change from +3VL to +3VALW and unmount this EEPROM

+3VALW

C484
0.1U_0402_16V4Z

U29

R521
@ 100K_0402_5%

U31
8
7
6
5

6,41,42,45 SMB_EC_CK1
6,41,42,45 SMB_EC_DA1

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

41

SPI_CS#

41

SPI_CLK

SPI_CS#

1
R221
1
R227
2
R229

41 EC_SO_SPI_SI

INT_SPI_CS#
2
0_0402_5%
SPI_CLK_R
2
33_0402_5%
1 EC_SO_SPI_SI_R
0_0402_5%

VCC

HOLD

VSS

SI2: Change from +3VALW to +3VL

+3VL
C624
2

EC_SI_SPI_SO_R

2
R223

1
0_0402_5%

@ 0.1U_0402_16V4Z

EC_SI_SPI_SO 41

SST25LF080A_SO8-200mil

@ AT24C16AN-10SI-2.7_SO8

R526
@ 100K_0402_5%

SPI_CLK_R

SI2: chagne 0 ohm to 33ohm for EMI

SI2: Add 22p for EMI

INT_SPI_CS#

28 SB_INT_FLASH_SEL

@ 22_0402_5%

JP50
SPI_CS#
EC_SI_SPI_SO_R

U24

R385

C794
22P_0402_50V8J

@ 0.1U_0402_16V4Z

C803

20mils

G Vcc

+3VALW

SPI Flash (8Mb*1)

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

INT_FLASH_EN#
SPI_CLK_R
EC_SO_SPI_SI_R

INT_FLASH_EN#

R313 @ 100K_0402_5%
1
2

SPI_CS#

@ NC7SZ32P5X_NL_SC70-5

+3VL

@ E&T_2941-G08N-00E~D

C:Chg. PN to LTC00000200

LPC Debug Port

+3VS
JP41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

R137 1

CLK_14M_SIO 22

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ1#
PLT_RST#
2 @ 0_0402_5%

CLK_PCI_SIO2 26

SIRQ

@ ACES_85201-2005

LPC Debug Port

H31

+3VALW

26,41

SIRQ

26,41

LPC_AD3

26,41

LPC_AD1

PLT_RST#

LPC_AD3

LPC_AD2

LPC_AD1

LPC_AD0

LPC_FRAME#

10

CLK_PCI_SIO

LPC_DRQ1# 26
PLT_RST# 11,14,15,26,32,33,34,41
LPC_AD2 26,41
LPC_AD0 26,41
CLK_PCI_SIO 26,30

26,41 LPC_FRAME#

R232
22_0402_5%
@
1

@ DEBUG_PAD

2
4

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

C486
22P_0402_50V8J
@

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

40

of

53

SI2: Change keyboard conn

+3VL_EC

KBD CONN

1
+3VL

C809

2
2
1000P_0402_50V7K

+3VL_EC
R527
1

+3VL

SI2: Change from

SMB_EC_DA2 R531
SMB_EC_CK2 R532

1
1

2 4.7K_0402_5%
2 4.7K_0402_5%
C810
1

+3VS

R530
2

2
@ 33_0402_5%

@ 15P_0402_50V8J

27
GATEA20
27
KB_RST#
26,40
SIRQ
26,40 LPC_FRAME#
26,40 LPC_AD3
26,40 LPC_AD2
26,40 LPC_AD1
26,40 LPC_AD0

26,30 CLK_PCI_EC
11,14,15,26,32,33,34,40
2
47K_0402_5%
27
27,30

R533 1

+3VL

SYSON

SI2: Change from

10K to 100K

R539
100K_0402_5%

R538
100K_0402_5%
2

R536
100K_0402_5%

LID_SW#

0205_Add Pull down

R402 for SUSP#.

6,40,42,45
6,40,42,45
6,21
6,21

27
27
27
42
42
42

+3VL
ESB_CLK
ESB_DAT

R563
R576

1
1

2 4.7K_0402_5%
2 4.7K_0402_5%

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

42,43 DOCK_SLP_BTN#
32
R543
+3VL

LANPWR

42

4.7K_0402_5%

C813
15P_0402_50V8J
1
2

CRY2

1
2
3
4

LANPWR
E51_TXD

+5VL

INV_PWM
FAN_PWM

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BATT_TEMP
BATT_OVP

AD

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

OSC

NC

OSC

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

GPIO
SM Bus

GPI

XCLK1
XCLK0

0.01U_0402_16V7K
ECAGND
1
2
BATT_TEMP 45
BATT_OVP 45
ADP_I 46
ADP_ID 45
TP_BTN# 42
ANA_MIC_DET 37

TP_BTN#

27
28

DAC_BRIG 24
VCTRL 46
IREF
46
AC_SET 46

IREF

G1
G2

KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

AC_LED#

CIR_IN

BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
ACIN_D

100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

+5VS_LED
JP48

37,43

1
2
3
4
5
6

1
2
3
4
G1
G2

for AC_LED function

+3VS
R540
1

ACES_85201-0405N

EC_SI_SPI_SO 40
EC_SO_SPI_SI 40
SPI_CLK 40
SPI_CS# 40

FSTCHG

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

KB Back Light Conn

AC_LED# 45 PV:Add
DOCK_VOL_UP# 43
DOCK_VOL_DWN# 43
VGATE 51

CIR_IN

@ C213
@C213
@C609
@
C609
@C754
@
C754
@C756
@
C756
@C757
@
C757
@C758
@
C758
@C759
@
C759
@C764
@
C764
@C768
@
C768
@C769
@
C769
@C822
@
C822
@C823
@
C823
@C824
@
C824
@C825
@
C825
@C826
@
C826
@C875
@
C875
@C876
@
C876
@C877
@
C877
@C878
@
C878
@C884
@
C884
@C885
@
C885
@C886
@
C886
@C887
@
C887
@C888
@
C888
@C889
@
C889
@C890
@
C890

ACES_85201-26051

EC_MUTE# 37,38
USB_EN# 39
I2C_INT 42
MUTE_LED 43
TP_CLK 42
TP_DATA 42

TP_CLK
TP_DATA

KSO17
KSO9
KSO16
KSI6
KSO14
KSO11
KSO10
KSO15
KSO6
KSO3
KSO12
KSO13
KSO2
KSO4
KSO7
KSO8
KSI3
KSO5
KSO1
KSI0
KSI4
KSI5
KSO0
KSI2
KSI1
KSI7

TP_BTN#
CONN@
2
1
R554 10K_0402_5%

+5VL

FSTCHG 46
STD_ADP 46
CAPS_LED# 42
BAT_LED# 42
ON/OFFBTN_LED# 42
SYSON
33,44,48
VR_ON

2
10K_0402_5%

TP_CLK

R534
1

TP_DATA

R535
1

+5V_TP

2
10K_0402_5%
2
10K_0402_5%

51

2
1
R541 10K_0402_5%
EC_RSMRST#

EC_RSMRST# 27
EC_LID_OUT# 27
EC_ON
44,47
WL_BLUE_LED# 42
SB_PWRGD 6,27,51
BKOFF#
24

WL_BLUE_LED#
SB_PWRGD
BKOFF#
TP_LED#

1
R560
D33
2

2
150K_0402_5%
1

+3VL

AC_IN

28,46

CH751H-40PT_SOD323-2
3

TP_LED# 42

SUSP#
PWRBTN_OUT#

2
C814

ACIN_D

2
C326

VFIX_EN 51
ENBKL 16
EAPD_CODEC 36
EC_THERM# 28
SUSP# 33,36,44,46,49,52
PWRBTN_OUT# 27
2
R231

1
0_0402_5%

1
100P_0402_50V8J

PCI_SERR# 26

remove in MP
4.7U_0805_10V4Z

SI: Mount C814 for KB926C

KB926QFC0_LQFP128_14X14

+3VL_EC

C815
15P_0402_50V8J
+EC_AVCC

L80
0_0603_5%
2

ACES_85205-0400

24
4
36
46

CIR_IN

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

CRY1

1
C327

C812

SPI Flash ROM

@
R545
20M_0402_5%

INV_PWM
FAN_PWM
EC_BEEP
ACOFF

ACOFF

SPI Device Interface

NC

77
78
79
80

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

1
2
3
4

32.768KHZ_12.5PF_9H03200413

@
JP34

21
23
26
27

PWM Output

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

EC DEBUG port

E51_TXD
LANPWR

DIM_LED

Y7

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

BATT_OVP 2
100P_0402_50V8J

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

DA Output

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

6,27 H_THERMTRIP#
43
CONA#
44
VLDT_EN
42,43 ON/OFF

12
13
37
20
38

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

0.1U_0402_16V4Z

+3VALW

EC_SCI#
HDARST#

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

C811

SUSP#

PLT_RST#

GATEA20
1
KB_RST#
2
SIRQ
3
LPC_LFRAME# 4
LPC_AD3
5
LPC_AD2
7
LPC_AD1
8
LPC_AD0
10

GND
GND
GND
GND
GND

2 4.7K_0402_5%
2 4.7K_0402_5%

11
24
35
94
113

1
1

VCC
VCC
VCC
VCC
VCC
VCC

U33
SMB_EC_DA1 R528
SMB_EC_CK1 R529

For EMI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2
0_0805_5%

+5VL to +3VL

CONN@
JP33

+EC_AVCC

67

C808

AVCC

2
2
0.1U_0402_16V4Z

C807

AGND

C806

69

C805

1000P_0402_50V7K

ECAGND

0.1U_0402_16V4Z
1

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

1
C816

2
0.1U_0402_16V4Z

L81
1

2
0_0603_5%

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

EC KB926/KB conn

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

41

of

53

CAPS LOCK LED

MDC 1.5 Conn.

+5VS_LED

WHITE
D30
1

41 CAPS_LED#

Change type 4/25

R552
1

2
HT-F196BP5_WHITE

470_0402_5%

JP25
HDA_SDOUT_MDC

27 HDA_SYNC_MDC
27 HDA_SDIN1
27 HDA_RST#_MDC

HDA_SYNC_MDC
HDA_SDIN1_MDC

1 R495
2
33_0402_5%

1
3
5
7
9
11

+3VS

470_0402_5%

+5VS_LED

2
470_0402_5%

1
R551

1
R559

Amber
LED1

2
200_0402_5%

+3VS

SI2: Change from +5VS to +3VS

and change to 200 ohm

DIM LED

C845
0.1U_0402_16V4Z

ENE@

GND

VIN

PV: change from MOS to Diode

C795
1U_0402_6.3V4Z

VOUT

U55 ENE@

2
0_0603_5%
ENE@

Q51
2N7002_SOT23-3

2
G

DIM_LED

C185 ENE@ 0.33U_0603_10V7K

1
R248

D15

BP

EN

41

1
2
R578 10K_0402_5%

CH751H-40PT_SOD323-2

+3VL_LDO

SI: Change to +3VL to support Qplay

bottom boot in BATT mode

ENE@
1
R247

+3VL

T/P Board (Inculde T/P_ON/OFF)

2
0_0603_5%

SWITCH BOARD.

CYPR@

+3VL_LDO
+5VS_LED

2
D31

PSOT24C_SOT23-3

2
0_0603_5%

+5V_TP

R603 1
R604 1

2
2

0_0402_5%
0_0402_5%

R610 1
R611 1

2
2

0_0402_5%
0_0402_5%

41 ON/OFFBTN_LED#

+5VALW_LED
41
LID_SW#
41,43 ON/OFF
6,40,41,45 SMB_EC_CK1
6,40,41,45 SMB_EC_DA1

CAP_CLK
CAP_DAT
1

Q85

0.1U_0402_16V4Z

R609
@ 0_0402_5%

R608
@ 0_0402_5%

1
C948
220P_0402_50V7K
@ 2

@
C821
100P_0402_50V8J

13
14

PV: change to 12pin

D38
PSOT24C_SOT23-3
@

1
C947
220P_0402_50V7K
2 @

SI2: Add diode for EMI

PV: Add for EMI

CONN@

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

GND
GND

TP_CLK 41
TP_DATA 41
TP_BTN# 41
TP_LED# 41
1

1
2
3
4
5
6
7
8
9
10
11
12

ACES_85201-1205N
ON/OFF
ON/OFFBTN_LED#

TP_CLK
TP_DATA
TP_BTN#
TP_LED#

1
2
ON/OFFBTN_LED#
3
CAP_CLK
4
CAP_DAT
5
6
R_PWR_LED
7
1
2
R705
150_0402_5%
8
ON/OFF
9
R605 1
0_0402_5% 10
2
R606 1
0_0402_5% 11
2
12

43,44,50 SYSON#

+5VS_LED

@
C820
ACES_85201-08051 100P_0402_50V8J

ESB_CLK
ESB_DAT
I2C_INT

41
41
41

JP36

SI: Add +5VALW_LED to support

PWR LED S3 flash function

PV: Add for EMI

@ SI2301BDS-T1-E3_SOT23-3

1
R235

+5VALW

1 @
C819
JP37

C502 4.7U_0805_10V4Z

D32
PSOT24C_SOT23-3
@

+5V_TP

PV: change from Q85 to R235

TP_BTN#
TP_LED#
3

TP_DATA
TP_CLK

SI2: add 4.7u for

Cypress cap board

PV: Change PN to SCA00000G00 for ESD request

PV: Add LDO for ENE cap board

APL5151-33BC-TRL_SOT23-5

1
2
3
4
5
6
7
8
9
10

1
1

C836
0.1U_0402_16V4Z

+5VL

1
2
3
4
5
6
7
8
GND
GND

+5VS
1

Q55
2N7002_SOT23-3

R587
10K_0402_5%

+5VS_LED

Q58

SI2301BDS-T1-E3_SOT23-3

+5VALW

+5VALW_LED

Q32

SI2301BDS-T1-E3_SOT23-3

SATA_LED#

Q138A
2N7002DW-7-F_SOT363-6

2
G
3

HT-F196BP5_WHITE

Q138B 28 GSENSOR_LED#
2N7002DW-7-F_SOT363-6

R505
100K_0402_5%

+5VALW_LED
R550
1

QSMF-C16E_AMBER-WHITE
White

WL_BLUE_LED# 41

BAT_LED#

HDD LED(Left 3)

28

WHITE
41

10K_0402_5%
R577

WL_LED#

470_0402_5%

D28

Connector for MDC Rev1.5

C780
@4.7U_0805_10V4Z CONN@

+3VS

33

Battery Charge LED(Left 2)

BT_LED

R549
1

HT-F196BP5_WHITE

R631
10K_0402_5%

39

HDA_BITCLK_MDC 27
2
1
1
2
R496
C777
@ 10_0402_5%
@ 10P_0402_25V8K

+5VS

D27

ON/OFFBTN_LED#

GND
GND
GND
GND
GND
GND
1

+5VALW_LED

WHITE

POWER LED(Left 1)

+3VS

ACES_88018-124G

13
14
15
16
17
18

C779

0.1U_0402_16V4Z

C778

1000P_0402_50V7K

+3VS

2
4
6
8
10
12

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

27 HDA_SDOUT_MDC

Title

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

42

of

53

Atlas/ Saturn Dock

+DOCKVIN

JP38
43
44

1
R586
1
R585

+5VS
+3VALW

<BOM Structure>
2
1K_0402_5%
2
1K_0402_5%

USB20_P3
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0-

23

DOCK_PWR_ON

1
3

DAN202U_SC70
2
R588
10K_0402_5%

42,44,50 SYSON#

27
32
32
32
32
32
32
32
32

D43
2

Q145A
2N7002DW-7-F_SOT363-6

23
23
27
23

23
GREEN_L
23
RED_L
D_DDCDATA
23
BLUE_L
D_HSYNC
D_DDCCLK
USB20_N3
D_VSYNC

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off
2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

D_DDCDATA
D_HSYNC
D_DDCCLK
USB20_N3
D_VSYNC
USB20_P3
RJ45_MIDI3+
RJ45_MIDI3RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI1+
RJ45_MIDI1RJ45_MIDI0+
RJ45_MIDI0+V_BATTERY

PJP5
B+

1
@

43
44

+3VS

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
42

41
42

SHIELD
SHIELD

45
46

CIR_IN
DOCK_PWR_ON
MUTELED
DOCK_SLP_BTN#
R_VOL_UP#
R_VOL_DWN#
SPDIFO_L
AUDIO_OGND
DOCK_LOUT_R
DOCK_LOUT_L
DOCK_MIC_R_C
DOCK_MIC_L_C
AUDIO_IGND
DOCK_PRESENT

CIR_IN

DOCK_VOL_UP#
2
R589
DOCK_VOL_DWN# 2
R590

37,41

1
10K_0402_5%
1
10K_0402_5%
1

R591

R567 1
R568 1

MUTE_LED 41
DOCK_SLP_BTN# 41,42
JACK_DET# 36,37
DOCK_VOL_UP# 41
DOCK_VOL_DWN# 41

1K_0402_5%

2 200_0402_5%
2 200_0402_5%

DOCK_VOL_UP#
DOCK_VOL_DWN#

DOCK_LOUT_R 37
DOCK_LOUT_L 37

2
PAD-OPEN 2x2m

FOX_QL1122L-H212AR-7F
CONN@

need change to reverse type connector

+1.5VS

+3VL

R574
@ 33_0402_5%

R565
10K_0402_5%

SPDIFO_L

0720 Add dock_present_gnd

C943

MIC_Dock

Need 600 Ohm 500 mA

2
0_0402_5%

R_VOL_UP#

1
1

1
2
0.1U_0402_16V7K
C894
R573
110_0402_5%

1
R647

2
150_0402_5%

SPDIF_OUT 36

R_VOL_DWN#

R575

220P_0402_50V7K

C942

220P_0402_50V7K

R566
2K_0402_1%

2
B
E

DOCK_LOUT_R
DOCK_LOUT_L
1

2 22_0402_5%

DOCK_PRESENT

R572

41

Q145B
2N7002DW-7-F_SOT363-6

C944
220P_0402_50V7K

CONA#

C
Q7
@ MMBT3904_NL_SOT23-3

SI2:chang R572 to 22 ohm & R566 to

2K to fix dock usb issue

1 1

1
C843
1000P_0402_50V7K

C844
1000P_0402_50V7K
3

L94
FBM-11-160808-601-T_0603
DOCK_MIC_R_C
1
2

36 DOCK_MIC_R

DOCK_MIC_L_C

1
2
L93
FBM-11-160808-601-T_0603

36 DOCK_MIC_L

1
C922

C921
220P_0402_50V7K 2

2 220P_0402_50V7K

+3VS

SENSE_B# 36

1
1

Q18
4

MMBT3904_NL_SOT23-3

R912 MMBT3904_NL_SOT23-3
C
10K_0402_5%
DOCK_MIC_L_C 1
Q16
2
2
B
E
2
R913
C978
47K_0402_5%

Q100
2N7002_SOT23-3

2
G

2
B

1
1

R915

R914
10K_0402_5%

10K_0402_5%

1U_0603_10V6K

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DOCK CONN

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

43

of

53

B+

C834

H15
H_3P0
@

Q17
SUSP
2
2N7002_SOT23-3
G

H16
H_3P0

H18
H_3P0

H14
H_3P0
@
1

H13
H_3P0

H12
H_3P0

H11
H_3P0

@
1

H10
H_3P0

H9
H_3P0

H19
H_3P0
@

H21
4P0

H22
4P0

H23
4P0

H24
4P0

H30
H_3P3

@
1

H8
H_3P0

1U_0402_6.3V4Z
SI4800BDY_SO8 RUNON
2 R152
1
750K_0402_1%
1
1
D
C840

H7
H_3P0

H6
H_3P0

RUNON

S
S
S
G

H5
H_3P0

1
4.7U_0805_10V4Z

C838

C864

4.7U_0805_10V4Z

4.7U_0805_10V4Z

SI4800BDY_SO8
1

D
D
D
D

1U_0402_6.3V4Z

C839
1
2
3
4

8
7
6
5

H4
3P0N
@

C835

Q14

1
2
3
4

0.01U_0402_25V7K

S
S
S
G

+3VS

H3
H_3P4N
@

C833

D
D
D
D

Q35
8
7
6
5

H2
H_7P0X5P0N

@
1

+3VALW

4.7U_0805_10V4Z
1

H1
H_4P5X3P0N

+3VALW TO +3VS

+5VS

+5VALW

+5VALW TO +5VS

+1.8V TO +1.8VS
H25
H_3P0

Q11
IRF8113PBF_SO8

Q13
SUSP
2
2N7002_SOT23-3
G

C849

1U_0402_6.3V4Z

C847
2

R808
10M_0402_5%

2 R233
1
330K_0402_5%

B+
+5VL

+5VL

D
2

C837

Q12 VLDT_EN#
2
G 2N7002_SOT23-3

B+

4.7U_0805_10V4Z

R595

R596

100K_0402_5%

SI2: Add this resistor to meet MOS voltage

SYSON#

42,43,50 SYSON#

100K_0402_5%
2

1
1

R809
10M_0402_5%

R138 2
1
750K_0402_1%

CF4
1

0.01U_0402_25V7K

1.8VS_ENABLE

4.7U_0805_10V4Z

4
C842

C862

CF3
1

1U_0402_6.3V4Z

CF2
1

1
2
3

C846

8
7
6
5

CF1
1

C841
10U_0805_10V4Z

H33
H_4P0
@

C848

0.01U_0402_25V7K

1
1
2
3

4.7U_0805_10V4Z

8
7
6
5

Q4
IRF8113PBF_SO8
2

H32
H_3P3
@

+1.2V_HT

+1.2VALW

+1.8VS

H27
H_4P0

+1.2VALW TO +1.2V_HT
+1.8V

SUSP

SUSP

18,50

SI2: Add this resistor to meet MOS voltage

Q142B
2N7002DW-7-F_SOT363-6
5

Q142A
2N7002DW-7-F_SOT363-6
2
SUSP#

33,36,41,46,49,52

33,41,48 SYSON

Discharge circuit
+1.8VS

+5VS

+1.2V_HT

+1.8V

+1.2VALW
2

D
Q41
EC_ON#
2N7002_SOT23-3

2
G

Q42
2N7002_SOT23-3
@

+5VL
1

2
G

+5VL
1

1
Q37
SYSON#
2N7002_SOT23-3

VLDT_EN# 2
G

R368
470_0805_5%
@

Q48
2N7002_SOT23-3

1
D

2
G

R284
470_0805_5%

SUSP

Q46
2N7002_SOT23-3

2
G
3

SUSP

R280
470_0805_5%

R279
470_0805_5%

R239
470_0805_5%

+1.1VS

41

VLDT_EN

VLDT_EN#

EC_ON#

R294
470_0805_5%

Q50
2N7002_SOT23-3

2
G
S

SUSP

Q52
2N7002_SOT23-3

2
G
S

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

41,47

1
1

SUSP

Q143B
2N7002DW-7-F_SOT363-6
5
EC_ON

1
Q49
2N7002_SOT23-3

2
G
3

SYSON#

Q143A
2N7002DW-7-F_SOT363-6
VLDT_EN 2

D
1

Q47
2N7002_SOT23-3
S

R293
470_0805_5%

1
1

2
G
3

SUSP

VLDT_EN#

R292
470_0805_5%

R288
470_0805_5%

13

+1.5VS

R598
100K_0402_5%
2

R597
100K_0402_5%
+0.9V

+3VS

Title

Compal Electronics, Inc.

DC/DC Circuits

Size Document Number

Custom
LA-4092P
Date:

Rev
0.4
Sheet

Thursday, February 21, 2008

E

44

of

53

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

AC_LED# 41

BATT
1

ADPIN

3
2

105K_0402_1%
PR6 1
2

1
2

0.01U_0402_25V7K
PC6

PC5
1000P_0402_50V7K
2
1

PC4
100P_0402_50V8J
2
1

1
2

PC2
2
1

PC3
1000P_0402_50V7K

PJSOT24C_SOT23-3

100P_0402_50V8J

PJP1

PD1

PL2
SMB3025500YA_2P
2
1

0
-

PU1A
LM358ADT_SO8

PR5
10K_0402_5%
2
1

PL1
SMB3025500YA_2P
1
2

BATT_OVP 41

VIN

1
2
PR3
10K_0402_5%

1
2

+DOCKVIN

5
4
3
2
1

PC12
@1000P_0402_50V7K

ADP_SIGNAL

5
4
3
2
1

RLZ3.6B_LL34

+5VALW
0.01U_0402_16V7K
PC1

ACES_88334-057N

PD4
PR2
10K_0402_5%

2 1

ADP_ID 41
PR9
100K_0402_5%

PR8
100_0402_5%

499K_0402_1% 340K_0402_1%
PR4 1
PR1 1
2
2

VMB
PJP2

BATT

PL3
SMB3025500YA_2P
2

PD2
@ SM05_SOT23

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

EC_SMD
EC_SMC

1
2

PC8
1000P_0402_50V7K

PC9
0.01U_0402_25V7K

1
2
3
4
5
6
7
8
GND
GND

1
2
3
4
5
6
7
8
9
10

PR7
47K_0402_1%
1
2

+5VS

@ SUYIN_200275MR008GXOLZR

CPU

PD3
@ SM24.TC_SOT23-3

PH1
10K_TH11-3H103FT_0603_1%

1
-

PR11
150K_0402_1%
PR12
2.55K_0402_1%

PQ1
@SSM3K7002FU_SC70-3

2
G

PC11
1000P_0402_50V7K

PR15
150K_0402_1%

EN0

PC10
0.22U_0603_10V7K

1
1

+3VL

PR16
6.49K_0402_1%
1
2

+5VALW

ENTRIP1 47
D

SMB_EC_CK1 6,40,41,42

BAT_ID 46

PU1B
LM358ADT_SO8

PR10
15K_0402_1%
1
2

SMB_EC_CK1

SMB_EC_DA1 6,40,41,42

2
2

SMB_EC_DA1

PR14
100_0402_5%

PR13
100_0402_5%

PR17
1K_0402_5%

PQ2
SSM3K7002FU_SC70-3

2
G
BATT_TEMP 41

47

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

DC Connector/CPU_OTP

Size

Document Number

Rev
0.1

LA-4092P
Date:

Thursday, February 21, 2008

D

Sheet

45

of

53

P4

B+

BATT
VIN

P2
PQ102
AM4835EP-T1-PF_SO8

27

BST_CHG

HIDRV

26

DH_CHG

VREF

11

VDAC

PH

25

LX_CHG

12

VADJ

REGN

24

REGN

LODRV

23

DL_CHG

1
1
3

PC111
0.1U_0402_10V7K
1
2
4

PD102
2

PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2

EXTPWR

PQ110
AO4468_SO8

22

21

20

19

18

17

3
2
1

PC119

BATT

PR112
0.015_1206_1%
1
2

PC118
0.1U_0402_10V7K

1U_0603_10V6K
PR117
100K_0402_5%
1
2

BQ24740VREF
1

IADAPT

16

DPMDET

CELLS

SRP

SRN

BAT

IADAPT

47K_0402_5%
PR119
1

D
PQ111
SSM3K7002FU_SC70-3

BATT

2
G

BAT_ID

45

PC120
0.22U_0603_10V7K
2
1

ADP_I

PC121
100P_0402_50V8J
2
1

PR118
10K_0402_5%
1
2

Charge Detector
41

15

PR116
39K_0402_5%

PGND
SRSET

ISYNSET

14
PR115
100K_0402_1%

PQ106
DTC115EUA_SC70-3

13

41

PQ108
AO4466_SO8

3
2
1

10

ACOFF

PC116
4.7U_0805_25V6-K

28

BTST

PVCC

AGND

IADSLP

PC115
4.7U_0805_25V6-K
2
1

PU101
BQ24740RHDR_QFN28_5X5

PC110
1U_0805_25V6K
1
2

RLS4148_LL34-2

PC117
1U_0603_10V6K

1
2

PC105
4.7U_0805_25V6-K

4
29

5
6
7
8

1
CHGEN

2
ACN

3
ACP

4
LPMD

ACDET

TP

PC114
4.7U_0805_25V6-K

VCTRL

CHG_B+
PR108
10_1206_5%
1
2

41

VIN

PR105
10K_0402_5%
ACOFF#

PC113
4.7U_0805_25V6-K
2
1

PD101
RLS4148_LL34-2

PC104
4.7U_0805_25V6-K

1
2

PC108
0.1U_0603_25V7K

PC109
@ 0.1U_0603_25V7K

+3VL

VADJ

PR113
143K_0402_1%

PR114
@ 0_0402_5%
1
2

PR103
47K_0402_5%
1
2

5
6
7
8

PQ109
SSM3K7002FU_SC70-3

CHG_B+

PC103
4.7U_0805_25V6-K

PC102
1U_0603_6.3V6M

2
G

8
7
6
5

CHGEN#

BQ24740VREF

PC112
1
2

ACOFF#

100K_0402_5%

LPREF

SUSP#

1U_0603_6.3V6M
PR111
3K_0402_1%
1
2

1
2
3

PL101
HCB2012KF-121T50_0805
2

SSM3K7002FU_SC70-3

PACIN

PR140

PR110
0_0402_5%
1
2

PACIN_1 47

1
PC107
@ 0.01U_0402_16V7K

ACSET

AC_SET

PR109
33,36,41,44,49,52
150K_0402_5%

PQ107

1
S

PQ105
DTC115EUA_SC70-3

1
3

1
ACDET

PR104
0_0402_5%
1
2 ACSET

2
1
PR106
200K_0402_5%

PC106
0.22U_0603_16V7K
2
1

DTA144EUA_SC70-3
PQ104

2
G

PR102
0.012_2512_1%
1
2

8
7
6
5

41

1
2
3

PR101
47K_0402_5%
1
2

PC101
47P_0402_50V8J
PR107
47K_0402_1%
1
2

PQ103
AM4835EP-T1-PF_SO8

1
2
3

8
7
6
5

PQ101
AM4835EP-T1-PF_SO8

1
2

PC122
0.1U_0603_25V7K

1
2

PC124
0.1U_0603_25V7K

41

PR122
1M_0402_5%
1
2

@
3

VIN_1

IREF

PR121
200K_0402_1%
2

PR123
1M_0402_5%
1
2

PR120
2
1
133K_0402_1%

PC123
0.1U_0402_10V7K

PD104
RLS4148_LL34-2

VIN

+3VL

PR124
1K_0402_5%
1
2

VIN

VIN

PU102A
LM393DG_SO8

PACIN

PACIN

LM393DG_SO8

8
P

PU102B

PR134
10K_0402_5%

PD103
RLZ4.3B_LL34

S
FSTCHG#
1
2
G

FSTCHG

STD_ADP 41

PR136
60.4K_0402_1%
1
2

VIN_1

PQ113
SSM3K7002FU_SC70-3
3

41

1.24VREF

PR133
10K_0603_0.1%

28,41

PQ112
SSM3K7002FU_SC70-3

2
D

2
G

PR135
10K_0603_0.1%

1
-

PC126
0.047U_0402_16V7K

AC_IN

PR127
10K_0402_1%

CHGEN#

PR130
2.15K_0402_1%
1
2

PR132
100K_0402_5%
2
1

PC125
0.1U_0603_25V7K

+3VL

PR131
133K_0402_1%

PR129
10K_0402_1%
2
1

VIN

PR126
133K_0402_1%

PR128
10K_0402_5%
2
1

PR125
47_1206_5%

+3VL

S
PU103
4

ACDET

22P_0402_50V8J
2

100K_0402_1%
PR138

PC127
PR137
20K_0402_1%

CATHODE

NC

NC

1.24VREF

ANODE

LMV431ACM5X_SOT23-5

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

REF

Title

Compal Electronics, Inc.

Charger

Size

Document Number

Rev
0.1

LA-4092P
Date:

Thursday, February 21, 2008

D

Sheet

46

of

53

20

LX_5V

12

DRVL2

DRVL1

19

LG_5V

B++

D
PQ305
SSM3K7002FU_SC70-3

2
G

2VREF_51125

D
PQ306
SSM3K7002FU_SC70-3

2
G
3

1
2

PR317
0_0402_5%

PC311
10U_0805_10V6K

ENTRIP2

5
6
7
8

4.7U_0805_25V6-K
PC313

1
2

4.7U_0805_25V6-K
PC305
2
1

1
2

5
6
7
8
2

2
1
PC312
0.1U_0603_25V7K

PR312
@ 0_0402_5%

+5VALWP
PC310
150U_D_6.3VM

1
+

2
3
2
1

EN0

14

13

VL
1

PL303
10U_LF919AS-100M-P3_4.5A_20%
1
2

+3VL

TPS51125RGER_QFN24_4X4

EN0

3
2
1

21

LL1

PR308
PC308
0_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2

UG1_5V

DRVH1

LL2

1
2
3

ENTRIP1

PC304
2200P_0402_50V7K

1
ENTRIP1

DRVH2

11

45

45

VFB1

10

PR311
@620K_0402_5%
@
2
1

PC309
150U_D_6.3VM

PQ303
AO4468_SO8

VREF

22

1
+

23

VBST1

PR316
100K_0402_5%

LG_3V

PGOOD

VBST2

VCLK

UG_3V

PQ302
AO4466_SO8

VREG3

18

VREG5

VIN

BST_3V

17

8
7
6
5

PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1

16

1
2
3

UG1_3V

+3VALWP

PR307
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V

PR309
0_0402_5%
1
2

PR306
150K_0402_1%
2

24

OCP=4.59(min)
MOSTemperature Factor=1.3 (100C)

B++

VO1

GND

VO2

SKIPSEL

VFB2

P PAD

15

PQ301
AO4466_SO8

TONSEL

25
2

PU301

PC306
10U_0805_6.3V6M

8
7
6
5

1
2

PC303
4.7U_0805_25V6-K

1
2

PR305
180K_0402_1%
1
2

ENTRIP1

PR304
20K_0402_1%
1
2

ENTRIP2

PR303
20K_0402_1%
1
2

+3VLP

2
PC301
2200P_0402_50V7K

PR302
30.9K_0402_1%
1
2

PL301
HCB2012KF-121T50_0805

PR301
13.7K_0402_1%
1
2

ENTRIP2

B++

B+

PC302
0.22U_0603_10V7K

2VREF_51125

PQ304
FDS6690AS_NL_SO8

3/5V_OK 49

PR318 0_0402_5%
3

OCP=7.644(min)
MOSTemperature Factor=1.3 (100C)

+5VL

VL

PJP304

PJP302

VL
+5VALWP

PR313
100K_0402_5%
PQ307
2
G
SSM3K7002FU_SC70-3

2
2

+5VALW

(4.5A,180mils ,Via NO.= 9)

+3VALW

(3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m
PJP303

EC_ON 41,44

+3VALWP

+3VL

+3VLP
PJP301

1
PAD-OPEN 2x2m

100K_0402_5%
PR314

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m

PACIN_1

PC314
0.022U_0603_25V7K

46

PQ308
SSM3K7002FU_SC70-3
1
2
2
G
PR315
604K_0402_1%

Title

Compal Electronics, Inc.

3.3VALWP/5VALWP

Size

Document Number

Rev
0.1

LA-4092P
Date:

Thursday, February 21, 2008

Sheet
E

47

of

53

HCB1608KF-121T30_0603
1
2

B+

1
2

1
2

1
2

5
6
7
8

14

1
4

V5DRV

10

+5VALW

DL_1.8V

DRVL

PR408 18.2K_0402_1%

PR410
4.7_1206_5%

PC415
4.7U_0805_10V6K

3
2
1

TPS51117RGYR_QFN14_3.5x3.5

+1.8VP

1
+

PQ402
FDS6690AS_NL_SO8

PC410
680P_0603_50V7K

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)
PC409
330U_4V_M

11

PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

12

2
0_0402_5%

2 2

LX_1.8V

LL
TRIP

1
PR407

3
2
1

DH_1.8V_1

PGOOD

13

VFB

PC405
680P_0402_50V7K

DRVH

DH_1.8V

VBST

TP

15

EN_PSV

V5FILT

PR411
1
2
14.3K_0603_0.1%

VOUT

PGND

+1.8VP

PQ401
AO4466_SO8

0.1U_0402_10V7K

PC411
1U_0603_10V6K

TON

GND

2
2

2
1
0_0402_5%

5
6
7
8

1+5VALW

PU401
PR405
255K_0402_1%
1
2

PR406

+1.8VP

PC404
2200P_0402_50V7K

PR403
316_0402_1%
2

PR404
0_0402_5%

PC403
4.7U_0805_25V6-K

BST_1.8V
1

PC406
4.7U_0805_25V6-K

PC407

+5VALW

PC408
3300P_0402_50V7-K

PC401
@ 1000P_0402_50V7K

1.8V_B+

33,41,44 SYSON

PL401

PR401
0_0402_5%
1
2

1
2
PC413
@ 10P_0402_50V8J

PR409
10K_0603_0.1%

PJP401
+1.8VP

+1.8V

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

1.8VP

Size

Document Number

Rev
0.1

LA-4021P
Date:

Thursday, February 21, 2008

D

Sheet

48

of

53

PR501
11.5K_0402_1%
+1.2VALWP

B+++

PR502
18.7K_0402_1%

PR503
24.9K_0402_1%

PR504
11.5K_0402_1%

B+++

+1.1VSP

B+++

B+

PL502
HCB2012KF-121T50_0805
2
1

1
2
3

+1.2VALWP
PL503
3.3UH_SIQB74B-3R3PF_5.9A_20%

UG1_1.2V

2
0_0402_5%

1
PR508

BST_1.2V

UG_1.2V

10

23

VBST2

VBST1

22

BST_1.1V

DR VH2

DR VH1

21

UG_1.1V

LL1

20

LX_1.1V

DR VL1

19

LG_1.1V

11

LL2

LG_1.2V

12

DR VL2

PC507
0.1U_0402_10V7K

PR507
0_0402_5%
2
1

2
UG1_1.1V

1
PR509
0_0402_5%

1
2

1
2

VFB1

24

EN1

LX_1.2V

5
6
7
8

3
GND

VO1

PGOOD1

PC516
4.7U_0805_25V6-K

EN2

PC504
4.7U_0805_25V6-K

PGOOD2

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

+1.1VSP

PGND1

OCP=9.6(min)
MOSTemperature Factor=1.3 (100C)

+5VALW

PC513
0.1U_0402_10V7K

SUSP# 33,36,41,44,46,52

PC512
@ 0.1U_0402_10V7K

PC515
4.7U_0805_10V6K

PC514
1U_0603_10V6K

PR513
21K_0402_1%
1
2

PR514
3.3_0402_5%

3/5V_OK

PR512
0_0402_5%
2

47

PC511
220U_6.3VM_R15

PQ504
AO4468_SO8
PR510
19.1K_0402_1%

OCP=4.487(min)
MOSTemperature Factor=1.3 (100C)

3
2
1

1
2
3

PR511
19.1K_0402_1%
1
2

PC510
4.7U_0805_6.3V6K

TPS51124RGER_QFN24_4x4

18

TRIP1

AO4468_SO8

17

V5FILT

V5IN
16

PQ503

15

PC509
4.7U_0805_6.3V6K

13

PC508
220U_D2_4VM

TRIP2

14

PGND2

5
6
7
8

8
7
6
5

PQ502
AO4466_SO8

2200P_0402_50V7K
PC505

PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1

TONSEL

P PAD

1.1VS_POK 18
PC503
0.022U_0603_25V7K

3
2
1

VO2

PQ501
AO4466_SO8

PU501

25

VFB2

8
7
6
5

2200P_0402_50V7K
PC502

1
2

PC501
4.7U_0805_25V6-K

PR505
0_0402_5%

PJP501

+1.1VSP

+1.1VS

(6A,240mils ,Via NO.=12)

PAD-OPEN 4x4m
PJP502

+1.2VALWP

+1.2VALW

(4A,160mils ,Via NO.=8)

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

1.1VSP/1.2VALWP

Size

Document Number

Rev
0.1

LA-4092P
Date:

Thursday, February 21, 2008

Sheet
1

49

of

53

+1.8V
+1.8V

VOUT

NC

TP

1
PC603
1U_0603_10V6K

PC613
10U_0805_10V6K

G2992F1U_SO8

PR606
1K_0402_1%

VREF

NC

VOUT

NC

TP

+5VALW

PC612
1U_0603_10V6K

+1.5VSP

2
G

PR607
5.1K_0402_1%

2
1
PC611
0.1U_0402_10V7K

1
PR608
0_0402_5%

18,44 SUSP

PQ602
SSM3K7002FU_SC70-3
PC605
10U_0805_10V6K

+0.9VP

1
2

2
3

PC604
0.1U_0402_10V7K

PC614
10U_0805_10V6K
C

PC606
@ 0.1U_0402_10V7K

PC610
@ 0.1U_0402_10V7K

PR603
1K_0402_1%

2
G
1

PR604
@ 0_0402_5%

PQ601
SSM3K7002FU_SC70-3

18,44 SUSP

VREF1.5V

0_0402_5%

NC

G2992F1U_SO8

PR602

42,43,44 SYSON#

VCNTL

GND

PR601
1K_0402_1%

VIN

NC

VREF

PU603

+5VALW

PC609
10U_0805_10V6K

NC

VCNTL

GND

VIN

2
1

1
2

PC602
10U_0805_10V6K

PC601
10U_0805_10V6K

PU601

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

PAD-OPEN 3x3m
PJP602

+2.5VSP

+2.5VS

(500mA,40mils ,Via NO.= 1)

+1.5VS

(1A,40mils ,Via NO.= 2)

PAD-OPEN 3x3m

OUT

+2.5VSP
B

GND
1

IN

PR605
@150_1206_5%

(2A,80mils ,Via NO.= 4)

+0.9V

+0.9VP

PC607
1U_0603_6.3V6M

PJP601

PC608
4.7U_0805_6.3V6K

+3VS

PJP603

+1.5VSP

2
PAD-OPEN 3x3m

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

0.9VSP/2.5VSP/1.5VSP

Size

Document Number

Rev
0.2

LA-4092P
Date:

Thursday, February 21, 2008

1

Sheet

50

of

53

PL201
4.7UH_SIQB74B-4R7PF_4A_20%
1

8
7
6
5

CPU_B+

1
2
3

1
2
3

PC202
220U_B2_2.5VM
<BOM Structure>

1
2

10U_0805_10V6K
PC201

6 VDD_NB_FB_L

PQ202
AO4466_SO8

PQ201
AO4468_SO8
8
7
6
5

6 VDD_NB_FB_H

+CPU_CORE_NB

PC204
4.7U_0805_25V6-K

2
UGATE NB 1

0_0402_5%

3
2
1

PQ205
FDS6676AS _SO8

PQ207

PQ208
FDS6676AS _SO8

3
2
1

+CPU_CORE_1
ISP 1

PC226
680P_0603_50V8J

1
PR241

2
0_0402_5%

PC238
@1000P_0402_50V7K
RTN0

1
PR236
6.81K_0402_1%

1
2

PC211
68U_25V_M_R0.44

PC240
68U_25V_M_R0.44

PC215
1000P_0402_50V7K

PC214
2200P_0402_50V7K
2
1

PC244
3300P_0402_50V7-K
2
1

PC243
820P_0402_50V7K
2
1

PR233
4.02K_0402_1%
1
2

PC229
0.1U_0603_25V7K

ISP 1

1
PR238
54.9K_0402_1%
2
1

PC232
1200P_0402_50V7K
PR240
1K_0402_1%
2
1

RTN1

2
0_0402_5%

+CPU_CORE_1

FDS6676AS_SO8

2
0_0402_5%

PC236
2
1

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1
PL204
PR229
4.7_1206_5%

VSEN0

2
1
PR237

4.7U_0805_25V6-K

4
3
2
1
5
6
7
8

PC224
0.22U_0603_10V7K

PC230
1000P_0402_50V7K
2
1

6 CPU_VDD0_FB_L

CPU_B+

UGATE1_1

1 2

TP

PR226
1
2
0_0603_5%
2
1
2

49

ISN1

ISP0

1
PR228
2.2_0603_5%

4.7U_0805_25V6-K

BOOT1

2
0_0402_5%

PC237
2
1

25

2200P_0402_50V7K

BOOT1

4.7U_0805_25V6-K
PC222
2
1

VW0

PR231
16.5K_0402_1%
2
1

UGATE1

12

PC221
2
1

26

1
PR235

6 CPU_VDD1_FB_H

1
ISP 0

PC231
180P_0402_50V8J

PR217
4.02K_0402_1%
1
2

PC219
0.1U_0603_25V7K

4.7U_0805_25V6-K

UGATE1

PC220
2
1

COMP0

6 CPU_VDD0_FB_H

+CPU_CORE_0

PL203

5
6
7
8
D
D
D
D
PHASE1

11

PQ206
SI4684DY-T1-E3_SO8

G
S
S
S

28
27

PR239

PC213
4.7U_0805_25V6-K
2
1

PR221
16.5K_0402_1%
2
1

1
1 2

3
2
1

4
PQ204
FDS6676AS_SO8

PC218
680P_0603_50V8J

PR220
4.7_1206_5%

5
6
7
8

5
6
7
8
PGND1
PHASE1

1
2
PC228
1000P_0402_50V7K

6 CPU_VDD1_FB_L

PC212
4.7U_0805_25V6-K
2
1

PC234
4.7U_0805_25V6-K
2
1

5
6
7
8
D
D
D
D
G
S
S
S

LGATE1

FB0

6.81K_0402_1%

2
<BOM Structure>

LGATE0

10

ISL6265IRZ-T_QFN48_6X6

SI4684DY-T1-E3_SO8

3
2
1

VDIFF0

0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1

5
6
7
8

OCSET

4
3
2
1

BOOT_NB
BOOT0

PHASE_NB

UGATE_NB

PGND_NB

LGATE_NB

PC235
4.7U_0805_25V6-K
2
1

1
2
UGATE NB
37

PHASE NB

LGATE NB
39

40

38

41
OCSET_NB

PC242
3300P_0402_50V7-K
2
1

PC241
820P_0402_50V7K
2
1

1
2

BOOT_NB1

0_0402_5%

2
PR209

PR207
15.4K_0402_1%

1
2
PR206

RTN_NB

VSEN_NB

LGATE1

29

ISP1

82.5K_0402_1%

PR232
1

42

30

PC225
1
2

1200P_0402_50V7K
1
2
PC227
180P_0402_50V8J

RTN_NB

31

PVCC

24

VSEN_NB

LGATE0

RBIAS

54.9K_0402_1%

FSET_NB

ENABLE

13

PR230

FB_NB

VW1

1K_0402_1%

COMP_NB

PHASE0

32

COMP1

34.8K_0402_1%~N
<BOM Structure>

47

33

PGND0

23

VCC

PHASE0

SVC

PR224
2

PR227

SVD

4700P_0402_25V7K

22

255_0402_1%

UGATE0

21

PC223
1
2

35
34

FB1

PR225
1

BOOT0
UGATE0

20

PR223
1

36

UGATE0_1

1
2
0_0603_5%
PR219

PWROK

VDIFF1

VR_ON

PC210
2.2U_0603_6.3V6K

2.2_0603_5% 0.22U_0603_10V7K
PR214
PC217
1
2 1
2

PGOOD

RTN1

41

PQ203

OFS/VFIXEN

17

1
PR222

PR211
1_0603_5%

BOOT_NB

B+
PL202
SMB3025500YA_2P

+5VS

RTN0

1
PR218

CPU_B+

VSEN0

PR234

CPU_SVD
CPU_SVC

2 ISL6265_PWROK
100K_0402_5%
SVD
2
0_0402_5%
SVC
2
0_0402_5%

15

PC206
0.1U_0603_16V7K

+CPU_CORE_014

VIN

VGATE

6,27,41 SB_PWRGD
6

PU201

ISP 0

41

PR215
@ 10K_0402_5%

ISN0

PR216
10K_0402_1%
2
1

46

2
PR212
0_0402_5%
1
2
PR213
@ 0_0402_5%
1
2
48

16

+5VS

+3VS

44

PC216
0.1U_0603_25V7K

45

CPU_B+

2
1
PR210
44.2K_0402_1%

PR208
2_0402_5%
1
2

2
1
PC208
1200P_0402_50V7K

1
2

33P_0402_50V8K
PC209
2
1

PC207
0.1U_0402_10V7K

43

PR205
2_0402_5%
1
2

+5VS

PHASE NB

LGATE NB

VSEN1

Connect to EC Pin 110.

PC205
1000P_0402_50V7K

19

2
G

18

PR204
22K_0402_1%
1
2

PQ115
SSM3K7002FU_SC70-3

VFIX_EN

ISL6265_PWROK

41

PC203
2200P_0402_50V7K

PR203
0_0402_5%

PC239
@1000P_0402_50V7K
VSEN1
2

PR243
255_0402_1%
2
1

4700P_0402_25V7K
PC233

Compal Secret Data

Security Classification

2006/11/23

Issued Date

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

+CPU_CORE

Size

Document Number

Rev
0.2

LA-4092P
Date:

Sheet

Thursday, February 21, 2008

1

51

of

53

PR701
0_0402_5%
1
2

33,36,41,44,46,49 SUSP#

PL701

10

DRVL

+5VALW

2
PR706
17.4K_0402_1%

1
2

PL702
1UH_PCMC063T-1R0MN_11A_20%
1
2

PR710
4.7_1206_5%

PC707
4.7U_0805_10V6K

3
2
1

15

14
V5DRV

2 DH_VGA_1
PR707
0_0402_5%

DL_VGA

3
2
1

+VGA_COREP

PQ702
FDS6690AS_NL_SO8

1
+

PC709

680P_0603_50V7K

+5VALW

PR712
49.9K_0402_1%

PR716
100K_0402_5%

OCP=10.098(min)
MOSTemperature Factor=1.3 (100C)

PR717

2
G

PQ703

10K_0402_1%

11

TPS51117RGYR_QFN14_3.5x3.5

PR711
37.4K_0402_1%

+VGA_COREP 2

PR713
10_0402_5%

+VGA_CORE

TRIP

PGND

2
PC713

@1000P_0402_50V7K
PR714
0_0402_5%

LX_VGA

PC708
330U_4V_M

PGOOD

DH_VGA

12

VFB

13

LL

2 2

PC705
@ 680P_0402_50V7K

V5FILT

DRVH

PR708
10K_0402_1%

TP

VOUT

TON

GND

+VGA_COREP1

B+

5
6
7
8

PR703
2
1
0_0402_5%

VBST

PR705
255K_0402_1%
1
2

EN_PSV

PU701

PC706
0.1U_0402_10V7K

2
5
6
7
8

1+5VALW
PR702
316_0402_1%

PQ701
AO4466_SO8

PC710
2200P_0402_50V7K

PR704
0_0402_5%

PC702
1U_0603_10V6K

2 1

PC704
4.7U_0805_25V6-K

BST_VGA 1

PC703
4.7U_0805_25V6-K

VGA_B+

+5VALW

+VGA_COREP

HCB1608KF-121T30_0603
1
2

PC701
@ 1000P_0402_50V7K

PQ704
SSM3K7002FU_SC70-3
2
1
G
PR715
0_0402_5%

VGA_PWRSEL 16

SSM3K7002FU_SC70-3

PC715
0.022U_0402_16V7K

PJP701
+VGA_COREP

+VGA_CORE

(7A,280mils ,Via NO.= 14)

High: VGA_CORE 0.9V

Low: VGA_CORE 1.1V

PAD-OPEN 4x4m
PJP702

Compal Secret Data

Security Classification

PAD-OPEN 4x4m

Issued Date

2007/05/29

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

VGA_CORE

Size

Document Number

Rev
0.1

LA-4092P
Date:

Thursday, February 21, 2008

D

Sheet

52

of

53

Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
1

Title

Date

Request
Owner

Issue Description

Solution Description

Rev.

48

1.8VP

10/23

Compal

for power requset

PU401 change the IC from "S IC RT8204PQW WQFN 16P" to

"S IC TPS51117RGYR QFN 14P".

46

Charger

10/30

Compal

for power requset

PQ104 swap the PQ104 1,3 Pin

47

3V/5V

10/30

Compal

for power requset

Change PR301 to 13.7K

47

3V/5V

10/30

Compal

for power requset

Change PR305 to 180K

modify OCP

47

3V/5V

10/30

Compal

for power requset

Change PR306 to 150K

modify OCP

47

3V/5V

10/30

Compal

for power requset

Change PR311 to 620K

47

3V/5V

10/30

Compal

for power requset

Change PR315 to 604K

49

+1.1VSP

10/30

Compal

for power requset

Change PR510 to 19.1K

modify OCP

49

+1.2VALWP

10/30

Compal

for power requset

Change PR511 to 19.1K

modify OCP

10

46

Charger

10/30

Compal

for power requset

Del PR119

11

51

CPU_CORE

10/30

Compal

for power requset

Change PC202 to B2 type for ME limit

12

51

CPU_CORE

10/30

Compal

for power requset

Change PR223 to 17.8K and PR224 to 100K

13

51

CPU_CORE

10/30

for power requset

Change PR221,PR231 to 16.5K and PR217,PR233 to 4.02K

for CPU_CORE compensation

14

45

DC connector 10/30

Compal

for power requset

Add PR3,PD4,PC12 for ADP_ID function

15

47

3V/5V

10/30

Compal

for power requset

Add PR317,PR318

16

46

Charger

10/30

Compal

for power requset

Change net from +3VLP to +3VL

17

49

+1.1VSP

10/30

Compal

for power requset

Change PR513 to 21K for HW power scquence.

18

46

Charger

11/09

Compal

for power requset

Pop PR119 Unpop PR9

19

50

0.9VSP

11/09

Compal

for power requset

Change PC601,PC605,PC611,PC603,PC613,PC614,PC612,
PC201 for common part

20

46

Charger

11/09

Compal

for power requset

Change PR112 to 0.015 Ohm

21

49

+1.2VALWP

11/09

Compal

for power requset

Change PC508 to D2 size for ME limit

22

51

CPU_CORE

12/05

Compal

for EMI requset

Add PR220,PR229 for EMI

23

49

CPU_CORE

12/05

Compal

for EMI requset

Add PC218,PC226 for EMI

Compal

modify output voltage

modify sequence

modify OCP

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Power Changed-List History-1

Size Document Number

Custom
LA-4111P
Date:

Rev
0.1
Sheet

Thursday, February 21, 2008

E

53

of

52

Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
1

Title

Date

Request
Owner

Issue Description

Rev.

Solution Description
Change PR120 to 133K to change charger current

46

Charger

12/05

Compal

for power requset

47

3V/5V

12/05

Compal

for power requset

Change PR302 to 30.9K for common part

47

3V/5V

12/05

Compal

for power requset

Change PR304 to 20K

48

+1.8VP

12/05

Compal

for power requset

Change PR408 to 18.2K

52

VGA_CORE

12/05

Compal

for power requset

Change PR306 to 150K

52

VGA_CORE

12/05

Compal

for power requset

Change PR714 to 0 Ohm

52

VGA_CORE

12/05

Compal

for power requset

Add PR713 100 Ohm

45

12/25

Compal

for power requset

Del PR9

46

Charger

12/25

Compal

for power requset

Reconnect from BQ24740VREF to +3VL

10

47

3V/5V

12/25

Compal

for power requset

Add PU302

11

52

VGA_CORE

12/25

Compal

for power requset

Del PC714

12

51

CPU_CORE

12/27

Compal

for power requset

ADD PC204 & PC211 68uF

13

48

+1.8VP

1/2

Compal

for EMI requset

Add PR410 4.7ohm and PC410 680P

14

48

+1.8VP

1/2

Compal

for EMI requset

Add PC405 680P and 408 3.3nF

15

51

CPU_CORE

1/2

Compal

for EMI requset

ADD PC241 820p & PC242

16

52

VGA_CORE

1/2

Compal

for EMI requset

Add PR710 and PC709

17

51

CPU_CORE

1/2

Compal

for EMI requset

ADD

PC243 to 3.3n

18

51

CPU_CORE

1/3

Compal

for power requset

ADD

PR234 & PQ115

DC Connector
/CPU_OTP

for common part

modify OCP
modify OCP

Change PC715 to 0.022u

& PR713 to 10 Ohm

3300p

PC244 to 820p

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Power Changed-List History-1

Size Document Number

Custom
LA-4111P
Date:

Rev
0.1
Sheet

Thursday, February 21, 2008

E

54

of

54

HW4 Product Improvement Record (P.I.R.)

D

1. Change R538 Pull high from +3VL to +3VALW

2. New add R563,R571 Pull high +3VS
3. Unmount BKOFF# Pull high R483
4. Unmount CPU_LDT_REQ# Pull high R318
5. Change LED1 P/N to SC500004C00
6. Change JP36 Pin2 from +5VS_LED to +5VALW_LED
7. Change C1012 & C1013 from 4700P to 1000P
8. Change R186 size from 0603 to 0402
9. Delete TV function and relation component
10. Add R554 for CIR pull high
11.Add C327 on BATT_OVT
12.Change L57 & L59 to 0603 BLM18PG121SN1D
13. exchange TV & WLAN mini card location
14.add LAN cable detect circuit
15.update ODD CONN footporint and symbol
16.delete Lid switch baord Conn
17.Change Cap sensor board power to +3VL to support Qplay boot

ZZZ2

RTC
45@ RTC

ZZZ

PCB
A

PCB 03X LA-4092P REV0 M/B

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/5/18

Issued Date

Deciphered Date

2008/5/18

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR
Size
Date:

Document Number
Thursday, February 21, 2008

Rev
0.4
Sheet
1

55

of

54