library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY alu8bit IS
port(j, k : in std_logic_vector(7 downto 0);
operator : in std_logic_vector(1 downto 0);
hasil : out std_logic_vector(15 downto 0);
sisa : out std_logic_vector(7 downto 0));
END alu8bit;
architecture behavioral of alu8bit is
procedure div(
numer: in std_logic_vector(7 downto 0);
denom: in std_logic_vector(3 downto 0);
quot: out std_logic_vector(3 downto 0);
remain: out std_logic_vector(3 downto 0)) is
variable d, n1: std_logic_vector(4 downto 0);
variable n2: std_logic_vector(3 downto 0);
begin
d := '0' & denom;
n2 := numer(3 downto 0);
n1 := '0'&numer(7 downto 4);
for i in 0 to 3 loop
n1 := n1(3 downto 0)&n2(3);
n2 := n2(2 downto 0)&'0';
if n1 >= d then
n1 := n1-d;
n2(0) := '1';
end if;
end loop;
quot := n2;
remain := n1(3 downto 0);
end procedure;
begin
process(j, k, operator)
variable remH, remL, quotH, quotL: std_logic_vector(3 downto 0);
begin
case operator is
when "00" =>
hasil <= ("00000000" & j) + ("00000000" & k);
sisa <= "00000000";
when "01" =>
hasil <= ("00000000" & j) - ("00000000" & k);
sisa <= "00000000";
when "10" =>
hasil <= j*k;
sisa <= "00000000";
when others =>
div("0000"&j(7 downto 4), k(3 downto 0), quotH, remH);
div(remH&j(3 downto 0), k(3 downto 0), quotL, remL);
hasil(15 downto 8) <= "00000000";
hasil(7 downto 4) <= quotH;
hasil(3 downto 0) <= quotL;
sisa <= "0000"&remL;
end case;
end process;
end behavioral;