do do.

do
# Model Technology ModelSim SE vlog 6.5f Compiler 2010.06 Jun 16 2010
# -- Compiling module testbench
#
# Top level modules:
#
testbench
# vsim -novopt work.testbench
# Refreshing /home/imspired/Desktop/TEST/PLL/work.testbench
# Loading work.testbench
# Loading work.clocks
# ** Warning: (vsim-3009) [TSCALE] - Module 'clocks' does not have a `timescale
directive in effect, but previous modules do.
#
Region: /testbench/uut
# Loading work.TCITSMCN40GGPMPLLA1
# Loading work.CKLNQD20BWP
# Loading work.sl_sync_reset_1
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_1' does not have a `t
imescale directive in effect, but previous modules do.
#
Region: /testbench/uut/pll_output_clk_rst_sync_inst
# Loading work.MUX2D1BWPHVT
# Loading work.sl_sync_level_ar_1_0_10
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_10' does not h
ave a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/pll_output_clk_rst_sync_inst/inst_sync
# Loading work.SDFCNQD1BWPHVT
# Loading work.DFCND1BWPHVT
# Loading work.clk_div_4_0
# ** Warning: (vsim-3009) [TSCALE] - Module 'clk_div_4_0' does not have a `times
cale directive in effect, but previous modules do.
#
Region: /testbench/uut/word_clk_divider_inst
# Loading work.CKMUX2D2BWP
# Loading work.INVD1BWPHVT
# Loading work.ND2D1BWPHVT
# Loading work.AOI221D1BWPHVT
# Loading work.AN2XD1BWPHVT
# Loading work.MAOI22D1BWPHVT
# Loading work.sl_sync_reset_13
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_13' does not have a `
timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/word_clk_ungated_rst_sync_inst
# Loading work.sl_sync_level_ar_1_0_9
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_9' does not ha
ve a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/word_clk_ungated_rst_sync_inst/inst_sync
# Loading work.DFCNQD1BWPHVT
# Loading work.clk_div_2
# ** Warning: (vsim-3009) [TSCALE] - Module 'clk_div_2' does not have a `timesca
le directive in effect, but previous modules do.
#
Region: /testbench/uut/compression_clk_divider_inst
# Loading work.MUX2D2BWPHVT
# Loading work.clk_div_4_3
# ** Warning: (vsim-3009) [TSCALE] - Module 'clk_div_4_3' does not have a `times
cale directive in effect, but previous modules do.
#
Region: /testbench/uut/fifo_clk_divider_inst
# Loading work.clk_div_4_2
# ** Warning: (vsim-3009) [TSCALE] - Module 'clk_div_4_2' does not have a `times
cale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_divider_inst
# Loading work.sl_sync_reset_12
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_12' does not have a `

timescale directive in effect, but previous modules do.

#
Region: /testbench/uut/compensation_clk_ungated_first_divider_rst_sync
_inst
# Loading work.sl_sync_level_ar_1_0_8
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_8' does not ha
ve a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_ungated_first_divider_rst_sync
_inst/inst_sync
# Loading work.clk_div_4_1
# ** Warning: (vsim-3009) [TSCALE] - Module 'clk_div_4_1' does not have a `times
cale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_divider2_inst
# Loading work.sl_sync_level_ar_144
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_144' does not have
a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/psm_clk_en_sync_inst
# Loading work.sl_sync_level_ar_143
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_143' does not have
a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/dma_clk_en_sync_inst
# Loading work.sl_sync_reset_11
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_11' does not have a `
timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/fifo_clk_ungated_rst_sync_inst
# Loading work.sl_sync_level_ar_1_0_7
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_7' does not ha
ve a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/fifo_clk_ungated_rst_sync_inst/inst_sync
# Loading work.sl_sync_level_ar_142
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_142' does not have
a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/fifo_clk_en_sync_inst
# Loading work.sl_sync_reset_10
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_10' does not have a `
timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compression_clk_ungated_rst_sync_inst
# Loading work.sl_sync_level_ar_1_0_6
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_6' does not ha
ve a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compression_clk_ungated_rst_sync_inst/inst_sync
# Loading work.sl_sync_level_ar_141
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_141' does not have
a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compression_clk_en_sync_inst
# Loading work.DFCNQD2BWPHVT
# Loading work.sl_sync_reset_9
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_reset_9' does not have a `t
imescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_ungated_rst_sync_inst
# Loading work.sl_sync_level_ar_1_0_5
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_1_0_5' does not ha
ve a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_ungated_rst_sync_inst/inst_syn
c
# Loading work.sl_sync_level_ar_140
# ** Warning: (vsim-3009) [TSCALE] - Module 'sl_sync_level_ar_140' does not have
a `timescale directive in effect, but previous modules do.
#
Region: /testbench/uut/compensation_clk_en_sync_inst
# Loading work.BUFFD3BWPHVT
# Loading work.BUFFD2BWPHVT

# ** Warning: (vsim-3017) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(395): [TFM

PC] - Too few port connections. Expected 34, found 32.
#
Region: /testbench/uut/pll_inst
# ** Warning: (vsim-3722) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(395): [TFM
PC] - Missing connection for port 'VDD'.
# ** Warning: (vsim-3722) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(395): [TFM
PC] - Missing connection for port 'VSS'.
# Loading work.tsmc_dla
# Loading work.tsmc_xbuf
# Loading work.tsmc_mux
# Loading work.tsmc_dff
# ** Warning: (vsim-3017) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(11): [TFMP
C] - Too few port connections. Expected 5, found 4.
#
Region: /testbench/uut/pll_output_clk_rst_sync_inst/inst_sync/sig_dela
y_reg
# ** Warning: (vsim-3722) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(11): [TFMP
C] - Missing connection for port 'QN'.
# ** Warning: (vsim-3017) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(155): [TFM
PC] - Too few port connections. Expected 5, found 4.
#
Region: /testbench/uut/compensation_clk_ungated_first_divider_rst_sync
_inst/inst_sync/sig_delay_reg
# ** Warning: (vsim-3722) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(155): [TFM
PC] - Missing connection for port 'QN'.
# ** Warning: (vsim-3017) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(268): [TFM
PC] - Too few port connections. Expected 5, found 4.
#
Region: /testbench/uut/compression_clk_ungated_rst_sync_inst/inst_sync
/sig_delay_reg
# ** Warning: (vsim-3722) /home/imspired/Desktop/TEST/PLL/clocks3.0.v(268): [TFM
PC] - Missing connection for port 'QN'.
run -all
#
0.000 ns testbench.uut.pll_inst >
0 ns reset pulse too short -- minimum
reset pulse 5000 ns
#
RESET MODE IS DONE
# |-----------------------------------------------------------------------------------------|
#
TEST MODE IS DONE
#
# |-----------------------------------------------------------------------------------------|
#
BYPASS MODE IS DONE
# |-----------------------------------------------------------------------------------------|
#
NORMAL MODE
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 400Mhz from 20Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 600Mhz from 20Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 800Mhz from 20Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 400Mhz from 40Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 600Mhz from 40Mhz Ref
# |-----------------------------------------------------------------------------------------|

#
Frequency Locked to 800Mhz from 40Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 400Mhz from 60Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 600Mhz from 60Mhz Ref
# |-----------------------------------------------------------------------------------------|
#
Frequency Locked to 800Mhz from 60Mhz Ref
# |-----------------------------------------------------------------------------------------|
# Break in Module testbench at testbench.v line 69