1. Complete the following problem. Show all steps.

i. Draw the state diagram for a Moore machine that can recognize the input sequences 0010
and 0111.
b.

Derive the state table for the Mealy state diagram in Figure 1. The labels are input/output, e.g.
1/0 means that a 1 was detected on the input and produces a 0 on the output.
Figure 1
0/1

1/0

0/0

1/0

1/0

0/0
1/0

Present
State

Next State
x=0 x=1

Output
y

A
B
C
D

B A
C C
B D
B A

0
0
0
1

c. Derive the state assignment table from (b). Use sequential encoding.

d. Derive the equation for Y1 and z from (c).

2. Write the VHDL necessary to implement the circuit in Figure 2. Be sure to consider what the black box
of the design is (what is the interface?).

Figure 2

You can start with the code below and fill in the missing pieces. You should provide proof (a timing
diagram?) that your solution is correct.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------ENTITY muxOuts IS
PORT
(
(a, b: in std_logic_vector(N-1 downto 0);
sel: in std_logic;
z: out std_logic_vector (downto 0);
);
END ENTITY;
ARCHITECTURE circuitDesign OF muxOuts IS
BEGIN
Z<=a when (sel =1 ) else b;
END ARCHITECTURE circuitDesign;

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