library ieee;

use ieee.std_logic_1164.all;
entity tff is
port(t,preset,clear,clk:in bit;
q:inout bit);
end tff;

architecture behav of tff is

begin
process(preset,clear,clk)

variable a,b:bit;
begin
a:=q;
if(clear = '0') then
a:='0';
elsif(preset = '0') then
a:='1';
elsif(clk='0' and clk'event) then
if(t='1') then
a:=not a;
end if;
end if;

q<=a;

end process;
end behav;